Switch mode power supply systems

Abstract

Methods and apparatus for sensing the output current in a switch mode power supply (SMPS) using primary side sensing are described. A system includes a primary current sense input, a charge input to sense a charging time of an SMPS transformer; a discharge input to sense a discharging time of the transformer; at least one averager; and a calculator. The primary current is averaged by the averager over at least a switching cycle of the SMPS and the calculator estimates the output current of the SMPS using the averaged primary current, the charge signal and the discharge signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which:

FIG. 1 shows an example of a switch mode power supply incorporating an embodiment of an SMPS error signal generating system according to the invention;

FIG. 2 shows an alternative voltage sensing arrangement for the SMPS of FIG. 1;

FIG. 3 shows an alternative current sensing arrangement for the SMPS of FIG. 1;

FIG. 4 shows a set of waveforms illustrating the operation of the SMPS of FIG. 1;

FIG. 5 shows an example implementation of the timing signal generator (timer) module of FIG. 1;

FIG. 6 shows an example implementation of the current model (CM) module of FIG. 1 using low-pass filters;

FIG. 7 shows a first alternative implementation of the current model (CM) module of FIG. 1 using low-pass filters;

FIG. 8 shows a second alternative implementation of the current model (CM) module of FIG. 1 using low-pass filters;

FIG. 9 shows a delta-sigma circuit implementation of the multiplier/divider of FIGS. 6 and 7;

FIG. 10 shows a translinear circuit implementation of the multiplier/divider of FIGS. 6 and 7;

FIG. 11 shows an example implementation of the controller (CTRL) module of FIG. 1;

FIG. 12 shows primary-side charge and secondary-side discharge waveforms for an SMPS as shown in FIG. 1 operating in a Discontinuous Conduction Mode (DCM), illustrating average primary- and secondary-side currents;

FIG. 13 illustrates a translinear circuit core.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Broadly speaking, we will describe techniques for estimating current on the secondary side of a transformer in a switched mode power supply (SMPS) using low-pass filters. The techniques we describe average the primary-side current. The techniques may also average the charge and discharge signals.

In embodiments the technique uses a sigma-delta analogue-to-digital converter to estimate the current on the secondary side of a transformer in a switched-mode power-supply by multiplying the average of the primary-side current with the quotient of the discharge-time (on the secondary side) by the charge-time (on the primary side). Preferably, the drive signal is used for sensing the charge-time, the current on the primary side is used for sensing the average of the primary current and the reflected voltage from the secondary winding is used for sensing the discharge-time on the secondary side. In alternative embodiments, the charge-time is sensed by sending the drive signal and sensing a zero-crossing in a winding on the primary side.

Referring to FIG. 1, this shows the simplified block diagram of a typical single-switch flyback SMPS. A DC source 20 is connected to the primary winding of a transformer 21 in series with a primary side switch 31 and a current sensing resistor 30. The secondary winding of the transformer 21 is connected to an output diode 22 in series with a capacitor 23. A load 24 is connected across the output capacitor 23. An auxiliary winding on the transformer 21 is connected between the negative terminal of the DC supply 20 and the timer 27 generating the voltage-sense signal VS. The primary current IP produces a voltage across resistor 30, generating the current-sense signal CS. The Driver 25 controls the on-times and the off-times of the switch 31 with the DRIVE signal.

The timer block 27 generates two timing signals, T₀ and T₁, by sensing the DRIVE and VS signals. T₀ represents the charge-time, i.e. the time when a current is flowing through the primary side of the transformer 21. T₁ represents the discharge-time, i.e. the time when a current is flowing through the secondary side of the transformer 21.

The signals T₀, T₁, CS, and OCT are used in the current model (CM) block 28 to produce an error signal, ERR. The (constant) OCT signal represents the target output current of the secondary winding. The ERR signal is a difference between OCT and the output current OC. The ERR signal is then used in the control block 26 to control the Driver 25 in such a way that the error signal ERR converges towards zero.

One alternative way to sense the current is to put the current sensing resistor 31 in the return path, as shown in FIG. 3. This configuration is particularly advantageous when switch 31 is a bipolar device; with the current sensing resistor in the return path, the primary current is being measured directly. One alternative way to sense the voltage is use a resistive divider (resistors 32 and 33) on the primary, as shown in FIG. 2, thus eliminating the auxiliary winding.

Timer Block

The timer block 27 generates two timing signals, T₀ and T₁, by sensing the DRIVE and VS signals. T₀ represents the charge-time, i.e. the time when a current is flowing through the primary side of the transformer 21. T₁ represents the discharge-time, i.e. the time when a current is flowing through the secondary side of the transformer 21. The waveforms of the signals are plotted in FIG. 4. FIG. 5 shows one example implementation of the timer. In this example, DRIVE is used directly for generating T₀ and the reflected secondary-side voltage sensed on the auxiliary (or primary) winding of transformer 21 is used to generate the discharge-time signal T₁. It is preferable to employ primary-side sensing for the discharge time since this enables the construction of an SMPS in which only primary-side sensing is employed. Nonetheless, in other embodiments secondary-side sensing may be employed to determine the discharge time.

FIG. 5 shows one way in which the discharge time may be determined, using an output voltage model (OVM) block 40, which has an output, OV, which approximated the output voltage of the SMPS (see FIG. 4) and which can be compared with the sensed voltage signal VS by comparator 41 to generate signal T₁. In general, an SMPS controller which incorporates primary-side sensing for output voltage regulation will already include some form of output voltage model.

A simple alternative to the use of an output voltage model per se is simply to compare the sensed voltage waveform with a reference level in order generate the discharge-time signal T₁.

Some further techniques are described that may be used to generate T₁. Referring again to FIG. 4 (DCM mode) it can be seen that the OC waveform falls to zero at the knee in the curve of VS (auxiliary winding voltage) against time. This is also the time at which the secondary side current falls to zero. Following this point VS exhibits ringing, first passing through zero at a point, a quarter of a cycle of the ringing on (later) from the knee point. The knee of the VS curve can be identified, for example using the techniques described in PCT/GB2005/050242 (incorporated by reference); or the zero crossing can be identified and (for example by keeping sampled values of VS in a shift register) the point a quarter of a ringing cycle before this can be identified to generate a transition of T₁ (once the period of the ringing cycle has been measured); or T₁ may be initiated by the opening of the power switch (signal T₀) and terminated by the first zero crossing, which approximates the true knee position.

Output Current Model Theory

It is helpful first to consider some theory underlying embodiments of the invention.

The relation between the primary and the secondary winding of the transformer 21 can be used for estimating the output current. A plot of the input (IP) and output (OC) currents is shown in FIG. 12. The average of the current in the primary winding during t₀ (IP₀) equals the average of the current in the secondary winding during t₁ (OC₁):

$\begin{array}{cc}\begin{array}{c}{\mathrm{nIP}}_0=n\frac{1}{T0}{\int }_{T0}^{}\mathrm{IP}t\\ =\frac{1}{T1}{\int }_{T1}^{}\mathrm{OC}t\\ ={\mathrm{OC}}_1\end{array}& \mathrm{Equation}1\end{array}$

where n is the turns-ratio between the secondary and primary winding (i.e. number of primary turns divided by the number of secondary turns). The average output current for the whole (SMPS) period T (OC_T) is:

$\begin{array}{cc}\begin{array}{c}{\mathrm{OC}}_T=\frac{1}{T}{\int }_{T_1}^{}\mathrm{OC}t\\ ={\mathrm{OC}}_1\frac{T1}{T}\\ ={\mathrm{nIP}}_0\frac{T1}{T}\end{array}& \mathrm{Equation}2\end{array}$

The average output current also can be rewritten in terms of the average input current over period T, IP_T using the equality:

$\begin{array}{cc}\begin{array}{c}{\mathrm{IP}}_0=\frac{1}{T0}{\int }_{T0}^{}\mathrm{IP}t\\ =\frac{T}{T0}\frac{1}{T}{\int }_T^{}\mathrm{IP}t\\ =\frac{T}{T0}{\mathrm{IP}}_T\end{array}& \mathrm{Equation}3\end{array}$

Now the average output current can be calculated from:

$\begin{array}{cc}\begin{array}{c}{\mathrm{OC}}_T={\mathrm{nIP}}_0\frac{T1}{T}\\ ={\mathrm{nIP}}_T\frac{T1}{T0}\end{array}& \mathrm{Equation}4\end{array}$

Current Model Block

Returning now to the CM block 28, the equation for estimating the output current is:

$\begin{array}{cc}\mathrm{OCM}=\frac{<\mathrm{CS}><T_1>}{<T_0>}& \mathrm{Equation}5\end{array}$

where <CS> is the average of the current sense signal, <T₁> is the average of a discharge signal depending on the discharge time and <T₀> is the average of a charge signal depending on the charge time. Averages are taken over at least a whole SMPS period T. Alternatively, T₁ and T₀ may replace <T₁ > and <T₀> respectively to estimate the output current.

Equation 5 is used to implement an error function, the results of which can be used to control the output current of the SMPS. There are three ways to implement the error function; all of which can be used for the controlling the output current:

The first implementation of the error function is shown in FIG. 6. The error function for the first implementation is:

$\begin{array}{cc}\mathrm{ERR}=\frac{<\mathrm{CS}><T1>}{<T0>}-\mathrm{OCT}& \mathrm{Equation}6\end{array}$

In this implementation, CS, T₀, and T₁ are fed through respective low-pass filters 12, 13 and 14, to generate the average of the three signals: <CS>, <T₀>, and <T₀>. The averaged signals are used in the multiplier/divider 11 to produce OCM. OCM is then compared to the output current target OCT in 15 to produce the error signal ERR.

As discussed above, <T₁> and <T₀> can be replaced by T₁, and T₀ respectively. If T₁, and T₀ are used instead of <T₀> and <T₀>, low-pass filters 13 and 14 are removed from the implementation.

The second implementation of the error function is shown in FIG. 7. By multiplying the right-hand side of Equation 6 by <T₀>/<T₁> the error signal becomes:

$\mathrm{ERR}=<\mathrm{CS}>-\frac{\mathrm{OCT}<T0>}{<T1>}$

Equation 7

The difference in this implementation that <T₀> and <T₁> have been switched on the input of the multiplier/divider 11. Also OCT and <CS> have been switched. In this implementation the signal path carrying OC_T is subtracted from <CS> in 15.

As will be appreciated, the ERR signal produced in the second implementation will differ in absolute value to the ERR signal produced in the first implementation. However, as will be described later, the absolute value of the ERR signal does not adversely affect the operation of the surrounding circuitry.

As discussed above, <T₁> and <T₀> can be replaced by T₁, and T₀ respectively. If T₁, and T₀ are used instead of <T₁> and <T₀>, low-pass filters 13 and 14 are removed from the implementation.

The third implementation of the error function is shown in FIG. 8. The right-hand side of Equation 6 can be multiplied by <T₀> in order to avoid the need for a division operation. The error signal becomes:

ERR=<CS><T1>−OCT<T0>  Equation 8

In this implementation, the multiplier/divider 11 has been replaced by two multipliers, 16 and 17. In this implementation the signal path carrying OCT is subtracted in 15.

As will be appreciated, the ERR signal produced in the third implementation will differ in absolute value to the ERR signal produced in the first and second implementations. However, as will be described later, the absolute value of the ERR signal does not adversely affect the operation of the surrounding circuitry.

As discussed above, <T₁> and <T₀> can be replaced by T₁, and T₀ respectively. If T₁, and T₀ are used instead of <T₁> and <T₀>, low-pass filters 13 and 14 are removed from the implementation.

The low-pass filters 12, 13, and 14 may be implemented using a variety of techniques. For example using switched-capacitor filters.

Multiplier/Divider Block

There are many alternative implementations of the multiplier/divider block. Two implementations are a delta-sigma (Δ Σ) circuit and a translinear circuit.

A delta-sigma (Δ Σ) circuit implementation of the multiplier/divider block is shown in FIG. 9.

The DC transfer function of the Δ Σ in FIG. 9 is:

$\begin{array}{cc}\mathrm{VOUT}=\frac{G1}{G2}\frac{V1·V3}{V2}& \mathrm{Equation}9\end{array}$

The transfer function of the Δ Σ is derived as follows. The input voltage V1 is transferred into a current I1 by the transconductance 31. The input voltage V2 is transferred into a current I2 by the transconductance 32 and the switch 33. The sum of the two currents is integrated in 34. The output of the integrator is quantized in 35 into a bitstream Q. The ADC 35 is clocked at time instants defined by the clock signal FS. The clock signal FS is generated by the oscillator 37. The bitstream is fed back to the input via the switch 33. This is a feedback system with an infinite gain at DC. Therefore the two currents I1 and I2 must be equal at DC.

Q·G2·V2=G1·V1   Equation

10

The voltage V3 is multiplied by bitstream Q with the switch 36. Therefore, the output voltage is:

VOUT=Q·V3   Equation 11

Solving for VOUT, using the equations Equation 10 and Equation 11, yields equation Equation 9.

A translinear circuit implementation of the multiplier/divider block is shown in FIG. 10.

The transfer function of the translinear circuit in FIG. 10 is:

$\begin{array}{cc}\mathrm{VOUT}=R·\mathrm{IC}4=R\frac{G1·G3}{G2}\frac{V1·V3}{V2}& \mathrm{Equation}12\end{array}$

The transfer function of the translinear circuit is derived as follows. The base-emitter diodes of the transistors 51-54 form a translinear loop. Assuming that the transistors has a zero base current and an infinite Early voltage, the relationship between the collector currents is:

IC1·IC3=IC2·IC4   Equation 13

It is helpful to consider the theory underlying the above equation.

The translinear circuit exploits the exponential relation between the collector current and the base-emitter voltage of bipolar transistors. A translinear core is shown in FIG. 13. The base-emitters of the four transistors form a voltage loop:

V _BE1 −V _BE2 +V _BE3 −V _BE4=0   Equation 14

The base-emitter voltage is:

$\begin{array}{cc}{V}_{\mathrm{BE}}=V_T\ln \frac{I_C}{I_S}& \mathrm{Equation}15\end{array}$

By inserting Equation 15 in Equation 14, the relation of the collector currents can be expressed as:

$\begin{array}{cc}\frac{I_{C1}·I_{C3}}{I_{C2}·I_{C4}}=1& \mathrm{Equation}16\end{array}$

However, this equation does not take into account for the base current and the Early voltage of the transistors.

Returning now to the translinear circuit, IC2 and IC3 are set by the transconductances 55 and 57 respectively. IC1 is set by the combined action of 55, 58, and 59. Because the emitter current of transistor 53 is cancelled by the transconductance 58 the collector current IC1 is set by the transconductance 59. The relations between the input voltages and the collector currents are:

$\begin{array}{cc}\{\begin{array}{c}\mathrm{IC}1=G1·V1\\ \mathrm{IC}2=G2·V2\\ \mathrm{IC}3=G3·V3\end{array}& \mathrm{Equation}17\end{array}$

Solving for IC4, using the equations Equation 13 and Equation 17, yields equation Equation 12.

In the translinear circuit implementation of the multiplier/divider block, the voltage source 61 is the power supply and the voltage source 60 is used to bias the emitter voltages to an appropriate voltage.

Controller

An example embodiment of the controller 26 of FIG. 1 is shown in FIG. 11. The main function of the controller is the integration of the ERR signal, performed by action of the resistor 70, the capacitor 72, and the amplifier 73. Together they form an inverting integrator. If the output current is too high, the error voltage ERR will be positive, and the signal CC will decrease which reduces the output power of the SMPS (and vice versa for a too low output current).

The purpose of resistor 71 is to cancel the residual pole from the CM 28 by inserting a zero. This way the transfer function from OC to CC only has one dominant pole at zero frequency.

Alternatively, the controller may be implemented without resistor 71 by replacing resistors 71 with a wire. In this alternative implementation of the controller, the low-pass filter 14 in the current module CM 28 is no longer required. In effect, removing the low-pass filter 14, i.e. letting the time constant τ₃ go to zero, reduces the required value of the resistor 71 to zero.

Driver

The driver 25 in FIG. 1 may comprise a pulse-width and/or pulse-frequency modulator that controls the DRIVE signal. The DRIVE signal turns on and off the primary side switch 31. The width and frequency of the DRIVE signal controls the power delivered to the secondary side of the transformer 21. The input signal CC preferably controls the driver 25 such that the power delivered to the secondary side is linearly dependent on (increases monotonically with respect to) the input signal CC. For further details reference may be made to the applicant's co-pending applications PCT/GB2005/050244, PCT/GB2005/050242 and GB0526118.5 (all of which applications are hereby incorporated by reference in their entirety).

Broadly speaking, we will describe techniques for estimating current on the secondary side of a transformer in a switched mode power supply (SMPS) using low-pass filters. The techniques we describe average the primary-side current. The techniques may also average the charge and discharge signals.

Broadly speaking we have described a method of using low-pass filters to produce an output current model for a switch mode power supply and hence estimate the output current of the switch mode power supply, in particular by means of primary-side sensing. In some preferred embodiments the output current model may be implemented using switched-capacitor filters. In embodiments three signals are employed in order to create the output current model, the charge time of the primary side of the magnetic energy storage device (transformer), a primary winding current signal, and the discharge time of the secondary side. These signals may be generated using a voltage sense signal comprising a reflected voltage of the secondary of the transformer, a current sense signal that represents the current on the primary side, and a DRIVE signal that represents the on-time of the primary (power) switch. In preferred embodiments a controller for an SMPS uses this current model to control the secondary side output current of the SMPS.

However embodiments may also be employed in conjunction with a voltage control loop, preferably a primary-side sensing voltage control loop, to implement constant-voltage, constant-current control. We have previously described a number of different techniques which may be employed for output voltage regulation using primary side feedback, for example in UK patent applications numbers 0610206.5, 0610210.7, 0610208.1 and 0610211.5 all filed by the present applicant on 23 May 2006, all hereby incorporated by reference in their entirety. For example, in one technique a decaying peak detector is employed to provide a signal approximating a tangent to the decaying secondary side waveform (reflected in the primary or an auxiliary winding waveform), the output voltage being sampled at the knee in the reflected secondary side voltage waveform, at which point because substantially no current is flowing to the SMPS output the secondary side voltage accurately reflects the output voltage of the SMPS. In another technique the primary (or an auxiliary) voltage waveform is integrated from a point of known zero flux (and hence current) in the transformer immediately prior to switching on the power device, the point at which the integrated signal is again equal to zero corresponding to the next point at which the flux (and hence secondary current) in a transformer is zero. This signals at the point at which to sample the voltage on the auxiliary (or a primary) winding in order to obtain an accurate indication of the SMPS output voltage.

The operation of embodiments of the above-described output current estimation technique in the context of an example of an SMPS operating in a Discontinuous Conduction Mode (DCM) are described, but the techniques also work in Critical Conduction Mode and in Continuous Conduction Mode (CCM) since no particular shape is assumed for the waveforms involved; instead the described signal processing employs the actual, sensed signal waveforms.

No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with each other. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

All documents, patents, and other references listed above are hereby incorporated by reference for any purpose. However, were any statement of these incorporated documents conflicts with the present disclosure, the present disclosure governs interpretation.

Claims

1. A system for estimating the output current of a Switch Mode Power Supply (SMPS), the SMPS including a transformer with at least a primary winding coupled to an input of the SMPS and a secondary winding coupled to an output of the SMPS and having a power switching device to switch power to the primary winding of the transformer, the system comprising: a primary current sense input to sense a primary current in the primary winding of the transformer;a charge signal input to sense a charge signal dependent on a charging time of the transformer;a discharge signal input to sense a discharge signal dependent on a discharging time of the transformer;at least one averager; anda calculator;

2. The system of claim 1, wherein each of the charge and discharge signals are averaged over at least a switching cycle of the SMPS by an averager.

3. A system according to claim 1, wherein the calculator estimates the output current of the SMPS by dividing a multiplied product of the averaged primary current and the discharge signal by the charge signal.

4. A system according to claim 1, wherein the calculator comprises a multiplier and divider having a plurality of inputs to receive a plurality of input signals, and adapted to multiply and divide the input signals to produce an output signal.

5. A system according to claim 4, wherein the multiplier and divider is a delta-sigma circuit.

6. A system according to claim 4, wherein the multiplier and divider is a translinear circuit.

7. A system according to claim 1, wherein the averager is a low-pass filter.

8. A system according to claim 7, wherein the low-pass filter is a switched-capacitor filter.

9. A method of estimating the output current of a Switched Mode Power Supply (SMPS), the SMPS including a transformer with at least a primary winding coupled to an input of the SMPS and a secondary winding coupled to an output of the SMPS and having a power switching device to switch power to the primary winding of the transformer, the method comprising: sensing a primary current in the primary winding of the transformer;sensing a charge signal that depends on a charging time of the transformer;sensing a discharge signal that depends on a discharging time of the transformer;averaging the primary current over at least a switching cycle of the SMPS; andcalculating the output current of the SMPS using each of the averaged primary current, the charge signal, the discharge signal.

10. The method of claim 9, wherein each of the charge and discharge signals are averaged over at least a switching cycle of the SMPS.

11. The method of claim 9, wherein the calculation comprises: dividing a product of the averaged primary current and the discharge signal by the charge signal.

12. A system for producing an error signal for controlling the output current of a Switch Mode Power Supply (SMPS), the SMPS including a transformer with at least a primary winding coupled to an input of the SMPS and a secondary winding coupled to an output of the SMPS and having a power switching device to switch power to the primary winding of the transformer, the system comprising: a primary current sense input to sense a primary current in the primary winding of the transformer;a charge signal input to sense a charge signal dependent on a charging time of the transformer;a discharge signal input to sense a discharge signal depending on a discharging time of the transformer;a desired output current signal input to sense a desired output current;at least one averager; anda calculator;

13. The system of claim 12, wherein each of the charge and discharge signals are averaged over at least a switching cycle of the SMPS by an averager.

14. The system of claim 12, wherein the calculator calculates the error signal by: dividing a product of the averaged primary current and the discharge signal by the charge signal; andsubtracting the desired output current signal from the divided product.

15. The system of claim 12, wherein the calculator calculates the error signal by: dividing a product of the desired output current signal and the charge signal by the discharge signal; andsubtracting the divided product from the averaged primary current.

16. The system of claim 12, wherein the calculator calculates the error signal by: subtracting a product of the desired output current signal and the charge signal from a product of the averaged primary current and the discharge signal.

17. The system according to claim 12, wherein the calculator comprises a multiplier and divider having a plurality of inputs to receive a plurality of input signals, and adapted to multiply and divide the input signals to produce an output signal.

18. The system according to claim 17, wherein the multiplier and divider is a delta-sigma circuit.

19. The system according to claim 17, wherein the multiplier and divider is a translinear circuit.

20. A system according to claim 12, wherein the averager is a low-pass filter.

21. A system according to claim 20, wherein the low-pass filter is a switched-capacitor filter.

22. A method for producing an error signal for controlling the output current of a Switch Mode Power Supply (SMPS), the SMPS including a transformer with at least a primary winding coupled to an input of the SMPS and a secondary winding coupled to an output of the SMPS and having a power switching device to switch power to the primary winding of the transformer, the method comprising: receiving a primary current in the primary winding of the transformer;receiving a charge signal, the charge signal depending on a charging time of the transformer;receiving a discharge signal, the discharge signal depending on a discharging time of the transformer;receiving a desired output current input signal;averaging the primary current over at least a switching cycle of the SMPS; andcalculating an error signal for controlling the output current of the SMPS using each of the averaged primary current, the charge signal, the discharge signal and the desired output current signal.

23. The method of claim 22, wherein each of the charge and discharge signals are averaged over at least a switching cycle of the SMPS.

24. The method according to claim 22, wherein the calculation comprises: dividing the product of the averaged primary current and the discharge signal by the charge signal; andsubtracting the desired output current signal from the divided product.

25. The method according to claim 22, wherein the calculation comprises: dividing a product of the desired output current signal and the charge signal by the discharge signal; andsubtracting the divided product from the averaged primary current.

26. The method according to claim 22, wherein the calculation comprises: subtracting the product of the desired output current signal and the charge signal from the product of the averaged primary current and the discharge signal.

27. A controller for controlling the output current of a Switch Mode Power Supply (SMPS) including the system of claim 12, wherein the output current of the SMPS is regulated in response to the error signal.

28. A controller according to claim 27, further comprising a module adapted to estimate an output voltage of the SMPS.

29. A controller according to claim 28, wherein the module receives a voltage-sense signal from a winding on the primary side of the transformer that represents a signal on the secondary side of the transformer, and wherein the module estimates the output voltage of the SMPS using the voltage-sense signal.

30. A controller according to claim 29, wherein the voltage-sense signal and the estimated output voltage of the SMPS are compared to produce the discharge signal.

31. A controller according to claim 27, wherein the charge signal is dependent on a drive signal that represents an on-time of the power switching device.

32. A system for regulating the output current of a Switch Mode Power Supply, comprising: means for calculating an error signal using an averaged primary current signal from a primary winding of a transformer comprising the SMPS, a charge signal depending on the charging time of the transformer, a discharge signal dependent on a discharging time of the transformer, and a desired output current input signal;means for regulating the output current of a SMPS in response to the error signal.

33. A Switch Mode Power Supply (SMPS), comprising: a transformer having at least a primary winding coupled to an input of the SMPS and a secondary winding coupled to an output of the SMPS;a switch that electrically couples and decouples the primary winding of the transformer to a power source; anda system according to claim 12,

34. A multiplier and divider for use in a Switch Mode Power Supply (SMPS) comprising: a plurality of inputs for receiving a plurality of input signals;an output;a dividing stage receiving at least two input signals, the dividing stage being adapted to generate a divided signal that represents a quotient of the at least two input signals; anda multiplying stage receiving at least one other input signal and being adapted to multiply the at least one other input signal by the divided signal,

35. A multiplier and divider according to claim 34, wherein the multiplying stage includes a switching device coupled between the at least one other input signal and an output of the multiplier and divider, the switching device having a control input receiving the divided signal from the dividing stage to provide the multiplied output.

36. A multiplier and divider according to claim 34, further comprising a switching device disposed between one of the at least two input signals to the input of the delta-sigma circuit, and having a control input coupled to the feedback path of the delta-sigma circuit, wherein the divided signal is fed back via the feedback path to control the switching device to selectively couple and decouple the one of the at least two input signals to the input of the delta-sigma circuit.