Patent Application
20150155784
This application claims the benefit of CN application No. 201310642504.9, filed on Dec. 3, 2013, and incorporated herein by reference.
The present invention generally relates to electrical circuit, and more particularly but not exclusively relates to transient response control circuit and control method in switch mode power supply.
Direct-Current to Direct-Current (DC-DC) Switch Mode Power Supply (SMPS) is used for converting a DC input voltage into a DC output voltage with predetermined value via controlling ON and OFF actions of a switch. Fixed frequency control is a conventional switching control method used in a SMPS and adopts a clock signal which has a fixed frequency. The clock signal is used to trigger a switching signal which controls the switch into a falling edge or a leading edge at each cycle, thus the switching signal has a fixed frequency. Fixed frequency control has advantage of low Electronic Magnetic Interference (EMI) effect, and thus is widely used, for example, in power supply for data communication system which is sensitive to the EMI noise.
When load changes, the response usually has some delay, and the output voltage would contain fluctuant ripples before it stabilizes at a predetermined level. However, some applications require that the output voltage stabilizes quickly.
Accordingly a control circuit having fast response speed is required to address one or some of the above deficiencies.
In one embodiment, a SMPS comprises: a switching circuit having a power input terminal configured to receive an input voltage and a power output terminal configured to provide an output voltage for supplying a load, the switching circuit having a switch; an adding circuit having a first input, a second input and an output, the first input of the adding circuit coupled to the power output terminal configured to receive an output voltage feedback signal indicative of the output voltage, the second input of the adding circuit configured to receive an output current feedback signal indicative of an output current of the switching circuit, and the adding circuit configured to add the output voltage feedback signal into the output current feedback signal and provide a combined feedback signal at the output of the adding circuit; a comparing circuit having a first input, a second input and an output, the first input of the comparing circuit coupled to the output of the adding circuit configured to receive the combined feedback signal, the second input of the comparing circuit configured to receive a reference signal, and the comparing circuit configured to compare the combined feedback signal with the reference signal and provide a comparing signal at the output of the comparing circuit; a logic circuit having an input and an output, the input of the logic circuit coupled to the output of the comparing circuit configured to receive the comparing signal; and a driving circuit having an input and an output, the input of the driving circuit coupled to the output of the logic circuit, and the output of the driving circuit coupled to the switch of the switching circuit configured to control ON and OFF of the switch.
In another embodiment, a control circuit for controlling a switch in a switching circuit, the switching circuit having a power input terminal configured to receive an input voltage and a power output terminal configured to provide an output voltage for supplying a load, the control circuit comprising: an adding circuit having a first input, a second input and an output, the first input of the adding circuit coupled to the power output terminal configured to receive an output voltage feedback signal indicative of the output voltage, the second input of the adding circuit configured to receive an output current feedback signal indicative of an output current of the switching circuit, and the adding circuit configured to add the output voltage feedback signal into the output current feedback signal and provide a combined feedback signal at the output of the adding circuit; a comparing circuit having a first input, a second input and an output, the first input of the comparing circuit coupled to the output of the adding circuit configured to receive the combined feedback signal, the second input of the comparing circuit configured to receive a reference signal, and the comparing circuit configured to compare the combined feedback signal with the reference signal and provide a comparing signal at the output of the comparing circuit; and a logic circuit having an input and an output, the input of the logic circuit coupled to the output of the comparing circuit configured to receive the comparing signal, the output of the logic circuit is coupled to the switching circuit configured to turn ON and OFF of the switch.
In yet another embodiment, a transient response control method of controlling a switch in a SMPS comprising: detecting an output voltage of the SMPS to obtain an output voltage feedback signal; detecting an output current of the SMPS to obtain an output current feedback signal; adding the output voltage feedback signal into the output current feedback signal to obtain a combined feedback signal; comparing the combined feedback signal to a reference signal to obtain a comparing signal; and turning ON and OFF the switch according to the comparing signal.
Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are only for illustration purpose. Usually, the drawings only show part of the system or circuit of the embodiments.
The use of the same reference label in different drawings indicates the same or like components.
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
The phrase “couple” in the description may refer to direct connection or indirect connection via interim media. The interim media may include conductor which may has resistance, parasitic capacitance and/or parasitic inductance. The interim media may include diode or other component/ circuit. The phrase “circuit” in the description may have forms of Integrated Circuit (IC), device, printed circuit board system or others.
Continuing with
Switching circuit 50 is a buck-type switching circuit. Switching circuit 50 comprises a switch Q1, a rectifier Q2, an output inductor L and an output capacitor Co. Switch Q1 has a first end, a second end and a control end, wherein the first end of switch Q1 is coupled to a power input terminal configured to receive input voltage Vin, the second end of switch Q1 is coupled to a switching node SW, and the control end of switch Q1 is coupled to driving circuit 56. Rectifier Q2 has a first end, a second end and a control end, wherein the first end of rectifier Q2 is coupled to switching node SW, the second end of rectifier Q2 is coupled to reference ground GND and the control end of rectifier Q2 is coupled to driving circuit 56. In another embodiment, rectifier Q2 may be replaced by a non-synchronous rectifier such as a diode. Switch Q1 and rectifier Q2 each comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). A MOSFET may comprise an enhanced N-channel MOSFET. In another embodiment, the switch and the rectifier each may comprise a P-channel MOSFET. In yet other embodiments, the switch and the rectifier each may comprise other type of device, such as Junction Field Effect Transistor (JFET) or Bipolar Junction Transistor (BJT). Output inductor L has a first end and a second end, wherein the first end of inductor L is coupled to switching node SW, and the second end of inductor L is coupled to output capacitor Co. Output capacitor has a first end and a second end, wherein the first end of Output capacitor Co is coupled to output inductor L and the second end of output capacitor Co is coupled to reference ground GND. The first end of output capacitor Co is coupled to the power output terminal and provides output voltage Vout. Switching circuit 50 may further comprise an input capacitor Cin configured to filter an input voltage Vin. Besides power input terminal Vin and power output terminal Vout, switching circuit 50 further has a first control signal terminal configured to receive a first control signal HS and a second control signal terminal configured to receive a second control signal LS, wherein the first control signal terminal is coupled to the control end of switch Q1, and the second control signal terminal is coupled to the control end of rectifier Q2. When switch Q1 is ON, rectifier Q2 is OFF, the voltage at switching node SW increases to approximate the level of input voltage Vin, current flows though output inductor L from switching node SW to power output terminal Vout, and load current lo increases. At the meantime, output capacitor Co may be charged, and output voltage Vout may increase. Then, switch Q1 is in OFF state, rectifier Q2 is in ON state, current flows through output inductor L and rectifier Q2 from the power output terminal to reference ground GND. At the meantime, output capacitor Co may be discharged and output voltage Vout may decrease. The voltage at switching node SW is regulated by the PWM signal outputted by logic circuit 55, and the signal waveform shape of the voltage at switching node SW is similar to the shape of the PWM signal. The voltage at switching node SW is filtered by output inductor L and output capacitor Co into a substantial DC output voltage Vout. This DC output voltage Vout may be affected by the change of load LD. For example, when load LD increases, the resistance of load LD decreases, and output voltage Vout decreases. And when load LD decreases, the resistance of load LD increases and output voltage Vout increases. And further due to the existence of Equivalent Series Resistance (ESR) of output capacitor Co, output voltage Vout has ripple with the same frequency of the PWM signal. In some other embodiments, switching circuit may comprise a step up (boost) converter or other type of converter.
Adding circuit 52 adds an output current feedback signal CS indicative of the output current flowing through switch Q1, an output voltage feedback signal FB indicative of the output voltage Vout, and a slope signal SLP together to get a combined feedback signal FB2. In one embodiment, adding circuit 52 adds up output current feedback signal CS, output voltage feedback signal FB and slope signal SLP with a proportion of 1:1:1. In other embodiments, adding circuit 52 may add up output current feedback signal CS, output voltage feedback signal FB and slope signal SLP with any other proportion. Output current feedback signal CS may be obtained by detecting the current flowing through switch Q1, and the increasing stage of current flowing through switch Q1 can represent the change of output current. In another embodiment, output current feedback signal CS may be obtained by detecting the current flowing through output inductor L. Output current feedback signal may be obtained by any type of suitable current detecting circuit or current detecting method.
Slope signal SLP is generated and outputted by slope signal generator 521. In one embodiment, slope signal SLP has the same frequency with a clock signal CLK, and has a slope at least at the period when output current is increasing.
DC correction circuit 53 comprises a trans-conductance amplifier 531 and a compensation circuit 532. Trans-conductance amplifier 531 has a first input, a second input and an output. Where the first input of amplifier 531 is coupled to the power output terminal configured to receive output voltage feedback signal FB, and the second input of amplifier 531 is coupled to a reference voltage Vref. In the shown embodiment, trans-conductance amplifier 531 has a non-inverting input coupled to reference voltage Vref and has an inverting input coupled to output voltage feedback signal FB. Trans-conductance amplifier 531 integrates and amplifies the difference between output voltage feedback signal FB and reference voltage Vref and outputs a current signal. This current signal is converted by compensation circuit 532 into an output voltage correction signal V1 provided at the output of trans-conductance amplifier 531. Compensation circuit 532 comprises a capacitor Cc and resistor Rc coupled in series, and one end of the compensation circuit 52 or said the serially coupled capacitor Cc and resistor Rc is coupled to reference ground GND, and the other end of the serially coupled capacitor Cc and resistor Rc is coupled to the output of trans-conductance amplifier 531. Wherein capacitor Cc is coupled to reference ground GND and resistor Rc is coupled to the output of trans-conductance amplifier 531. Compensation circuit 532 is set to have low frequency pass filtering characteristic and the outputted output voltage correction signal V1 has low frequency, or in other words, the shape of output voltage correction signal V1 is flat. When load increases, output voltage feedback signal FB decreases, and output voltage correction signal V1 increases slowly. And in another embodiment, when output voltage Vout decreases, the output voltage feedback signal may increase in contrary, accordingly the output voltage feedback signal is supplied to non-inverting input of trans-conductance amplifier and output voltage correction signal also increases slowly.
Comparing circuit 54 has a non-inverting input, an inverting input and an output, wherein the non-inverting input of comparing circuit 54 receives combined feedback signal FB2, the inverting input of comparing circuit 54 receives reference signal V1 (or output voltage correction signal V1 in this embodiment), and the output of comparing circuit 54 provides comparing signal CP coupled to logic circuit 55 for controlling the ON and OFF of switch Q1. When combined feedback signal FB2 is higher than output voltage correction signal V1, comparing signal CP is set to logic HIGH, and logic circuit 55 outputs the PWM signal in logic LOW to turn OFF switch Q1. And in another embodiment, the signal received by the non-inverting input and the signal received by the inverting input of comparing circuit 54 may be exchanged as would be known to person of ordinary skill in the art.
Logic circuit 55 comprises a clock signal generator 551 and a flip latch 552. Clock signal generator 551 generates the clock signal CLK. Clock signal CLK presents a HIGH logic pulse at the beginning of each cycle, and turns ON switch Q1 at each cycle. Flip latch 552 has a set input S, a reset input R and an output Q, wherein the set input S is coupled to clock signal generator 551 to receive clock signal CLK, the reset input R is coupled to the output of comparing circuit 54 to receive comparing signal CP, and output Q provides PWM signal for controlling the ON and OFF of switch Q1. When clock signal CLK is in logic HIGH, PWM signal at output Q of flip latch 552 is set in logic HIGH. The PWM signal would keep in logic HIGH until when comparing signal CP turns in logic HIGH and then PWM signal is reset in logic LOW. When the next HIGH logic pulse of the clock signal CLKI comes, PWM signal is set HIGH again. In another embodiment, the set input S of flip latch 552 receives the comparing signal and the reset input R of flip latch 552 receives the clock signal, and switch Q1 turns ON when the PWM signal outputted by flip latch 552 is in logic LOW.
Driving circuit 56 converts the logic signal PWM outputted by logic circuit 55 into the first control signal HS at a voltage level suitable for driving switch Q1, and into the second control signal LS at a voltage level suitable for driving rectifier Q2. In another embodiment, switching circuit 50 comprises a non-synchronous rectifier and the driving circuit outputs one control signal HS to switching circuit 50.
Control circuit 51 may further comprise an output voltage feedback circuit 57. Output voltage feedback circuit 57 is coupled to the power output terminal of switching circuit 50 and converts output voltage Vout into an output voltage feedback signal FB. Output voltage feedback circuit 57 comprises a resistor divider comprising a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is coupled to power output terminal Vout of switching circuit 50, a second end of the first resistor R1 is coupled to the second resistor R2, the other end of the second resistor R2 is coupled to reference ground GND. And the common end of the first resistor R1 and the second resistor R2 forms the output of output voltage feedback circuit 57 to provide output voltage feedback signal FB. Accordingly, output voltage feedback signal FB is proportional to output voltage Vout as FB=R2/(R1+R2)*Vout. In other embodiments, output voltage feedback circuit 57 may be any other suitable circuit, or comprise other type of sensing element.
At time t1, clock signal CLK has a HIGH logic pulse, flip latch 552 is set HIGH, and output Q provides the PWM signal in logic HIGH. Accordingly, switch Q1 turns ON, and output current feedback signal CS increases. And combined feedback signal FB2 also increases. At time t2, when combined feedback signal FB2 increases to be higher than reference signal V1, comparing signal CP outputted by comparing circuit 24 is in logic HIGH to reset flip latch 552, the PWM signal outputted by flip latch 552 is in logic LOW, and switch Q1 turns OFF. When the logic HIGH pulse comes at the next cycle, PWM signal is set HIGH again to turn ON switch Q1.
At time t3, load current lo increases, output voltage feedback signal FB decreases. At that time, PWM signal is in logic LOW and switch Q1 is in OFF state. At time t4, clock signal CLK has a high pulse, and PWM signal turns to logic HIGH to turn ON switch Q1. Since output voltage feedback signal FB at time t4 is lower than that at time t1, combined feedback signal FB2 has a lower initial value at time t4 than that at time t1, longer time is needed from combined feedback signal FB2 increases to be higher than reference signal V1 after time t4. This directly leads to higher duty cycle of the PWM signal and is desirable for load increase. From
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201310642504.9 | Dec 2013 | CN | national |
