Switched-Capacitor Circuit

Abstract

A low-power switched-capacitor circuit is disclosed. The low-power switched-capacitor circuit includes a p-channel switched-capacitor integrator and an n-channel switched-capacitor integrator. The p-channel switched-capacitor integrator includes a first set of input transistors controlled by a first set of capacitors and switches. The n-channel switched-capacitor integrator includes a second set of input transistors controlled by a second set of capacitors and switches. The p-channel switched-capacitor integrator and the n-channel switched-capacitor integrator function together in a push-pull fashion such that a required transconductance as well as width and drain current of the first and second sets of input transistors are reduced by half of those in a conventional switch-capacitor circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 a is a schematic diagram of a switched-capacitor circuit, according to the prior art;

FIG. 1 b is a two-phase non-overlapping clock scheme;

FIG. 2 is a schematic diagram of a switched-capacitor circuit, in accordance with a preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a common-mode feedback circuit for the switched-capacitor circuit from FIG. 2, in accordance with a preferred embodiment of the present invention; and

FIG. 4 is a schematic diagram of a voltage reference circuit for the switched-capacitor circuit from FIG. 2, in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring now to the drawings and in particular to FIG. 1a, there is depicted a schematic diagram of a switched-capacitor circuit, according to the prior art. As shown, a switched-capacitor circuit 100 includes an operational amplifier 134, sampling capacitors C_S1, C_S2, integration capacitors C_I1, C_I2, and switches S₁, S₂, S₃, S₄, S₅, S₆, S₇ and S₈. Operational amplifier 134 can be a telescopic amplifier or a folded-cascode amplifier. Switches S₁-S₄ are collectively referred to as signal conducting switches, and switches S₅-S₈ are collectively referred to as summing junction switches.

Referring now to FIG. 1b, there is illustrated a two-phase non-overlapping clock scheme defined by four clock waveforms: φ₁, φ_1D, φ₂ and φ_2D, The position of each of switches S₁-S₈ from FIG. 1a at any given time is determined by its corresponding one of clock waveforms. For the present embodiment, a switch is open when its corresponding clock waveform is in a “low” state, and a switch is close when its corresponding clock waveform is in a “high” state. Clock waveforms φ₁ and φ_1D are in “high” states when φ₂ and φ_2D are in “low” states. Clock waveforms φ_1D and φ_2D are similar to clock waveforms φ₁ and φ₂, respectively. However, the falling edges of clock waveforms φ_1D and φ_2D are not initiated until after clock waveforms φ₁ and φ₂ have returned to their “low” states. Together, clock waveforms φ₁ and φ_1D define a sampling phase of a clock scheme while clock waveforms φ₂ and φ_2D define a transferring phase of the clock scheme.

With reference now to FIG. 2, there is depicted a schematic diagram of a switched-capacitor circuit, in accordance with a preferred embodiment of the present invention. As shown, a switched-capacitor circuit 200 includes a split-path pseudo-differential amplifier 210, sampling capacitors C_SPA, C_SNA, C_SPB, C_SNB, integration capacitors C_IPA, C_INA, C_IPB, C_INB, and switches S1A, S2A, S3A, S4A, S5A, S6A, S1B, S2B, S3B, S4B, S5B, S6B. Preferably, the capacitance of each of sampling capacitors C_SPA, C_SNA, C_SPB and C_SNB is half the capacitance of C_S1 or C_S2 from FIG. 1a, and the capacitance of each of integration capacitors C_IPA. C_INA, C_IPB and C_INB is half the capacitance of C_I1 or C_I2 from FIG. 1a. The position of each of switches S1A-S6A and S1B-S6B at any given time is determined by its corresponding one of the clock waveforms from FIG. 1b.

Split-path pseudo-differential amplifier 210 includes p-channel transistors M4A, M3A and n-channel transistors M2A, M1A connected in series between a power supply V_DD and a power supply V_SS. Split-path pseudo-differential amplifier 210 also includes p-channel transistors M4B, M3B and n-channel transistors M2B, M1B connected in series between power supply V_DD and power supply V_SS. The gate of transistor M3A is connected to the gate of transistor M3B, and the gate of transistor M2A is connected to the gate of transistor M2B. Although split-path pseudo-differential amplifier 210 is shown to have p-channel transistors M4A, M3A, M4B, M3B and n-channel transistors M2A, M1A, M2B, M1B, each of transistors M3A, M3B, M2A, M2B is not essential for the operation of the present invention and can be replaced by a shorted wire without affecting the functionality of split-path pseudo-differential amplifier 210.

The gate of input transistor M4A is connected to integration capacitor C_IPA, and is selectively connected to sampling capacitor C_SPA via switch S4A. The gate of input transistor M1A is connected to integration capacitor C_INA, and is selectively connected to sampling capacitor C_SNA via switch S2A. The gate of input transistor M4B is connected to integration capacitor C_IPB, and is selectively connected to sampling capacitor C_SPB via switch S4B. The gate of input transistor M1B is connected to integration capacitor C_INB, and is selectively connected to sampling capacitor C_SNB via switch S2B.

Split-path pseudo-differential amplifier 210 includes four inputs V_in1⁺, V_in2⁺, V_in1⁻, V_in2⁻ and two outputs V_out⁺ and V_out ⁻. Input V_in1⁺ is selectively connected to sampling capacitor C_SPA via switch S5A. Input V_in2⁺ is selectively connected to sampling capacitor C_SNA via switch S6A. Input V_in1⁻ is selectively connected to sampling capacitor C_SPB via switch S5B. Input V_in1⁻ is selectively connected to sampling capacitor C_SNB via switch S6A. Output V_out ⁺ is connected to integration capacitors C_IPA, C_INA and a node located between transistors M3A and M2A. Output V_out ⁻ is connected to integration capacitors C_IPB, C_INB and a node located between transistors M3B and M2B.

Bias voltage V_bpd is selectively connected to sampling capacitor C_SPA via switch S3A, and is selectively connected to sampling capacitor C_SPB via switch S3B. Bias voltage V_bpd is selectively connected to input transistor M4A via switches S3A, S4A, and is selectively connected to input transistor M4B via switches S3B, S4B. Bias voltage V_bnd is selectively connected to sampling capacitor C_SNA via switch S1A, and is selectively connected to sampling capacitor C_SNB via switch S1B. Bias voltage V_bnd is selectively connected to input transistor M1A via switches S1A, S2A, and is selectively connected to input transistor M1B via switches S1B, S2B. Bias voltages V_bpd and V_bnd are generated by a feedback circuit 300 from FIG. 3 along with its complementary circuit.

Split-path pseudo-differential amplifier 210 reduces power consumption through current reuse. During operation, each of the sampling capacitors (i.e., capacitors C_SPA, C_SNA, C_SPB and C_SNB) and integration capacitors (i.e., capacitors C_IPA, C_INA, C_IPB and C_INB) are split into two equal parts. One part is connected to the gates of n-channel input transistors (i.e., transistors M1A and M1B) and the other part is connected to the gates of p-channel input transistors (i.e., transistors M4A and M4B). As a result, both input transistors M1A and M4A (or transistors M1B and M4B) contribute signal amplification, while sharing the same drain current.

From an operating principle standpoint, the left half of switched-capacitor circuit 200 can be viewed as an n-channel switched-capacitor integrator (formed by transistors M1A, M2A, capacitors C_SNA, C_INA, and switches S1A, S2A) and a p-channel switched-capacitor integrator (formed by transistors M3A, M4A, capacitors C_SPA, C_IPA, and switches S3A, S4A) in parallel. Similarly, the right half of switched-capacitor circuit 200 can be viewed as an n-channel switched-capacitor integrator (formed by transistors M1B, M2B, capacitors C_SNB, C_INB, and switches S1B, S2B) and a p-channel switched-capacitor integrator (formed by transistors M3B, M4B, capacitors C_SPB, C_IPB, and switches S3B, S4B) in parallel. On both halves, each of the n-channel and p-channel switched-capacitor integrators, which together work in a push-pull fashion, only drives half of the capacitances that a conventional operational amplifier (such as operational amplifier 134 from FIG. 1) needs to drive in order to meet specific signal-to-noise ratio (SNR) specifications. Thus, the required transconductance is reduced by half, as well as the width and drain current of input transistors, which effectively reduces the power dissipation and silicon area of split-path pseudo-differential amplifier 210. The gate bias voltages for the p-channel and n-channel input transistors are generated through switched-capacitor bias network.

Bias voltages V_bpd and V_bnd are dynamically passed to the gates of p-channel transistors M4A, M4B and n-channel transistors M1A, M1B, respectively. Bias voltage V_bnd is connected to V_bnc in feedback circuit 300 from FIG. 3, and bias voltage V_bpd is connected to an equivalent node of a complementary version of feedback circuit 300 from FIG. 3.

Referring now to FIG. 3, there is illustrated a schematic diagram of a common-mode feedback circuit for switched-capacitor circuit 200 from FIG. 2, in accordance with a preferred embodiment of the present invention. As shown, feedback circuit 300 is a common-mode feedback circuit having a direct-charge transfer circuit 310 and an amplifier 320.

With reference now to FIG. 4, there is depicted a schematic diagram of a voltage reference circuit for switched-capacitor circuit 200 from FIG. 2, in accordance with a preferred embodiment of the present invention. As shown, a voltage reference circuit 400 includes p-channel transistors M4, M3 and n-channel transistors M2, M1 connected in series between power supplies V_DD and V_SS. The gate of transistor M3 is connected to voltage V_CP, and the gate of transistor M2 is connected to voltage V_CN. Bias voltage V_bp is selectively connected to transistor M4 via switches S41 and S42. Bias voltage V_bn is selectively connected to transistor M1 via switches S45 and S46. Input V_I is selectively connected to output V_O via switches S43 and S44.

Voltage reference circuit 400 also includes capacitors C41-C44. Capacitor C41 is connected between bias voltage V_bp and input V_I, and capacitor C42 is connected between input V_I and bias voltage V_bn. Capacitor C33 is connected between the gate of transistor M4 and output V_O, and capacitor C44 is connected between output V_O and the gate of transistor M1. Preferably, the capacitance of each of capacitors C41-C42 is half the capacitance of C_S1 or C_S2 from FIG. 1a, and the capacitance of each of capacitors C43-C44 is half the capacitance of C_I1 or C_I2 from FIG. 1a.

As has been described, the present invention provides a switched-capacitor circuit having a split-path pseudo-differential amplifier. For the same transconductance, the input referred noise of the split-path pseudo-differential amplifier of the present invention is smaller than those of conventional telescopic amplifiers and folded-cascode amplifiers. Therefore, comparing to conventional switched-capacitor circuits that employ telescopic and folded-cascode amplifiers, the switched-capacitor circuit of the present invention consumes less power, occupies smaller silicon area, and has lower input referred noise.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A switched-capacitor circuit comprising: a p-channel switched-capacitor integrator having a first set of input transistors controlled by a first set of capacitors and switches; andan n-channel switched-capacitor integrator having a second set of input transistors controlled by a second set of capacitors and switches, wherein said p-channel switched-capacitor integrator and said n-channel switched-capacitor integrator function together in a push-pull fashion such that a required transconductance as well as width and drain current of said first and second sets of input transistors are reduced by half.

2. The circuit of claim 1, wherein said p-channel switched-capacitor integrator includes two sampling capacitors and two integration capacitors.

3. The circuit of claim 2, wherein each of said integration capacitors is directly connected to one of two input transistors within said p-channel switched-capacitor integrator, and each of said sampling capacitors is selectively connected to said one of two input transistors within said p-channel switched-capacitor integrator.

4. The circuit of claim 1, wherein said n-channel switched-capacitor integrator includes two sampling capacitors and two integration capacitors.

5. The circuit of claim 4, wherein each of said integration capacitors is directly connected to one of two input transistors within said n-channel switched-capacitor integrator, and each of said sampling capacitors is selectively connected to said one of two input transistors within said n-channel switched-capacitor integrator.