Patent Application
20220014098
This application claims priority to R.O.C. Patent Application No. 109123183 titled “Switched-capacitor dc-dc voltage converter and control method thereof,” filed on Jul. 9, 2020, with the Taiwan Intellectual Property Office (TWO).
The present disclosure relates to a voltage converter, and particularly, to a switched-capacitor dc-dc voltage converter and control method thereof.
Low power consumption is an important feature for current microprocessors and consumer electronics product. In the future, most of the microprocessors or IC used in the Internet of Things will operate with light loads current output range. Therefore, the design of light load and high efficiency will be one of the design priorities of the switched-capacitor DC-DC converter as the power circuit.
Take a conventional switched-capacitor DC-DC voltage converter as an example, a conventional switched-capacitor DC-DC voltage converter 1 with a conversion ratio of 2:1 as shown in
For those familiar with the field of switched-capacitor DC/DC converter, to produce different switched-capacitor DC/DC voltage converters with different conversion ratios, four terminals of the switch circuit 10 (comprising a first terminal P being the terminal of the first switch SW1 not connected to the capacitor C, a second terminal Q being the terminal of the second switch SW2 not connected to the capacitor C, a third terminal R being the terminal of the fourth switch SW4 not connected to the capacitor C, and a fourth terminal S being the terminal of the third switch SW3 not connected to the capacitor C) can be connected with other switch arrays or electrically connected to an input voltage, an output voltage, and a ground as shown in
Referring to
In view of this, how to provide a switched-capacitor DC-DC power converter with low output ripple and high conversion efficiency is an important and valuable technology.
One aspect of the present disclosure provides a switched-capacitor DC-DC voltage converter with low output ripple, which can improve energy usage efficiency, computing performance and operational robustness of the loading circuitry.
In order to achieve the above object, an embodiment of the present invention provides a switched-capacitor DC/DC voltage converter comprising at least one switch array and a control circuit. The switch array comprises a capacitor, a first switch group, a second switch group, a third switch group, and a fourth switch group, wherein each of the first, second, third, and fourth switch groups comprises a plurality of power switches connected to one another in parallel, one end of the capacitor is electrically connected to the first switch group and the second switch group, another end of the capacitor is electrically connected to the third switch group and the fourth switch group. The control circuit converts an input control signal to a first control signal set and a second control signal set, and outputs the first control signal set to the first and third switch groups and the second control signal set to the second and fourth switch groups, wherein each of the first control signal set and the second control signal set comprises a plurality of control signals with the phase delayed sequentially and the duty cycle reduced sequentially.
In some embodiments of the present disclosure, the power switches have the same area cost.
In some embodiments of the present disclosure, the power switches are field effect transistors.
In some embodiments of the present disclosure, the power switches have the same sizing ratio.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and the control circuit comprises:
a clock divider, dividing the control signal into N control signals with equal phase difference, comprising a first clock signal and N−1 control signals with equal phase difference;
a non-overlapping signal generator, converting the first clock signal into a first main clock control signal and a second main clock control signal; and
an AND gate array, converting the first main clock control signal and the N−1 control signals with equal phase difference into the first control signal set, and converting the second main clock control signal and the N−1 control signals with equal phase difference into the second control signal set.
In some embodiments of the present disclosure, the clock divider comprises N flip-flops and an inverter.
In some embodiments of the present disclosure, the non-overlapping signal generator comprises an inverter, two NAND gates, and two delay units.
In some embodiments of the present disclosure, the AND gate array comprises 2(N−1) AND gates.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and a delay time between each of the signal members in the first and second control signal sets is ½N cycle time.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and duty cycles of each of the first and second control signal sets are sequentially reduced by 1/N duty cycle.
In order to achieve the above object, another embodiment of the present invention provides a control method of a switched-capacitor DC-DC voltage converter, wherein at least one switch array in the switched-capacitor DC-DC voltage converter is controlled by a control circuit, the switch array comprises a capacitor, a first switch group, a second switch group, a third switch group, and a fourth switch group, each of the first, second, third, and fourth switch groups comprises a plurality of power switches connected to one another in parallel, one end of the capacitor is electrically connected to the first switch group and the second switch group, another end of the capacitor is electrically connected to the third switch group and the fourth switch group, and the method comprises:
converting an input control signal into a first control signal set and a second control signal set; and
outputting the first control signal set to the first and third switch groups and the second control signal set to the second and fourth switch groups,
wherein each of the first control signal set and the second control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and the step of converting the control signal into the first control signal set and the second control signal set comprises:
dividing an input control signal into N control signals with equal phase difference, comprising a first clock signal and N−1 control signals with equal phase difference;
converting the first clock signal into a first main clock control signal and a second main clock control signal; and
converting the first main clock control signal and the N−1 control signals with equal phase difference into the first control signal set, and converting the second main clock control signal and the N−1 control signals with equal phase difference into the second control signal set.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and a delay time of each of the first and second control signal sets is ½N cycle time.
In some embodiments of the present disclosure, the number of the power switches of each of the first, second, third, and fourth switch groups is N, and duty cycles of each of the first and second control signal sets are sequentially reduced by 1/N duty cycle.
In order to achieve the above object, another embodiment of the present invention provides a switched-capacitor DC-DC voltage converter, which comprise:
at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of signals with phase delayed sequentially and the duty cycle reduced sequentially.
In order to achieve the above object, another embodiment of the present invention provides a control method of a switched-capacitor DC-DC voltage converter, wherein at least one switch array in the switched-capacitor DC-DC voltage converter is controlled by a control circuit, the switch array comprises a capacitor, and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group, and the method comprises: converting an input control signal into a first control signal set and a second control signal set; and outputting the first control signal set to the first and third switch groups and the second control signal set to the second and fourth discharge switch groups, wherein each of the first control signal set and the second control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.
Exemplary embodiments will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features. Persons having ordinary skill in the art will understand other varieties for implementing example embodiments, including those described herein. The drawings are not limited to specific scale and similar reference numbers are used for representing similar elements. As used in the disclosures and the appended claims, the terms “example embodiment,” “exemplary embodiment,” and “present embodiment” do not necessarily refer to a single embodiment, although it may, and various example embodiments may be readily combined and interchanged, without departing from the scope or spirit of the present disclosure. Furthermore, the terminology as used herein is for the purpose of describing example embodiments only and is not intended to be a limitation of the disclosure. In this respect, as used herein, the term “in” may include “in” and “on”, and the terms “a”, “an” and “the” may include singular and plural references. Furthermore, as used herein, the term “by” may also mean “from”, depending on the context. Furthermore, as used herein, the term “if” may also mean “when” or “upon”, depending on the context. Furthermore, as used herein, the words “and/or” may refer to and encompass any and all possible combinations of one or more of the associated listed items.
In order to reduce the output ripple of the switched-capacitor DC/DC voltage converter more efficiently, the present invention provides a design method of a switched-capacitor DC-DC voltage converter in accordance with some embodiments of the present disclosure. Referring to
The following will specifically describe how the distributed control signal controls the switch array. Referring to
More specifically, the switch array 210 comprises a capacitor Cfly and at least one switch group. For example, the switch array 210 comprises one switch group and a single switch. According to one embodiment, the switch array 210 comprise four switch groups, a first switch group G1, a second switch group G2, a third switch group G3, and a fourth switch group G4. Each of the first switch group G1, the second switch group G2, the switch group G3, and the fourth switch group G4 comprises a plurality of power switches. For example, each switch group comprises the same number (for example, N) of power switches S1, S2, . . . , SN in parallel, but not limited to this, but each switch group also can comprises a different number of switches.
For those familiar with the field of switched-capacitor DC/DC converter, to produce different switched-capacitor DC/DC voltage converters with different conversion ratios, four terminals of the switch array 210 (comprising a first terminal p being the terminal of the first switch group G1 not connected to the capacitor Cfly, a second terminal q being the terminal of the second switch group G2 not connected to the capacitor Cfly, a third terminal r being the terminal of the fourth switch group G4 not connected to the capacitor Cfly, and a fourth terminal s′ being the terminal of the third switch group G3 not connected to the capacitor Cfly) can be connected with other switch arrays or electrically connected to an input voltage, an output voltage, and a ground as shown in
More specifically, the plurality of power switches S1, S2, . . . , SN of the first switch group G1 have a first common terminal and a second common terminal, the plurality of power switches S1, S2, . . . , SN of the second switch group G2 have a first common terminal and a second common terminal, the plurality of power switches S1, S2, . . . , SN of the third switch group G3 have a first common terminal and a second common terminal, and the plurality of power switches S1, S2, . . . , SN of the fourth switch group G4 have a first common terminal and a second common terminal. One terminal of the capacitor Cfly is electrically connected to the first common terminal of the first switch group G1 and the first common terminal of the second switch group G2, and anther terminal of the capacitor Cfly is electrically connected to the first common terminal of the third switch group G3 and the first common terminal of the fourth switch group G4. The second common terminal of the first switch group G1 is the first terminal p of the switch array 210. The second common terminal of the second switch group G2 is the second terminal q of the switch array 210. The second common terminal of the fourth switch group G4 is the third terminal r of the switch array 210. The second common terminal of the third switch group G3 is the fourth terminal s′ of the switch array 210.
The control circuit 220 may comprise a control signal generator 221 and logic gates 223. In one embodiment, the control circuit 220 may comprise logic gates 223 and be connected to a control signal generator 221 outside the control circuit 220. The control signal generator 221 can generate a control signal (for example, a square wave, a triangle wave or a sine wave signal) to the logic gates 223. The logic gates 223 can convert the control signal into a first control signal set ϕ1,k and a second control signal set ϕ2,k, and output the first control signal set ϕ1,k to the first and third switch groups G1, G3 and the second control signal set ϕ2,k to the second and fourth switch groups G2, G4. In which, k={x|0≤x≤N−1, x∈Z}.
The first control signal set ϕ1,k comprises a plurality of control signals ϕ1,0, ϕ1,1, . . . , ϕ1,N-1 with the phase delayed sequentially and the duty cycle reduced sequentially. The second control signal set ϕ2,k comprises a plurality of control signals ϕ2,0, ϕ2,1, . . . , ϕ2,N-1 with the phase delayed sequentially and the duty cycle reduced sequentially. The first main clock control signal ϕ1,0 of the first control signal set ϕ1,k and the second main clock control signal ϕ2,0 of the second control signal set ϕ2,k are reverse phase signals or independent signals.
Next, embodiments of multiple power switches S1, S2, . . . , SN will be further described. Referring to
According to one embodiment, source terminals s of the plurality of power switches S1, S2, . . . , SN are electrically connected to one another, and drain terminals d of the plurality of power switches S1, S2, . . . , SN are electrically connected to one another. The logic gates 223 output the first control signal set ϕ1,k to the gate terminals g of the power switches S1, S2, . . . , SN of the first switch group G1, respectively, and generally synchronously outputs the first control signal set ϕ1,k to the gates g of the power switches S1, S2, . . . , SN of the third switch group G3, respectively, in which the control signals ϕ1,0, ϕ1,1, . . . , ϕ1,N-1 of the first control signal set ϕ1,k have a one-to-one relationship with the plurality of power switches S1, S2, . . . , SN. According to one embodiment, sources of the plurality of power switches S1, S2, . . . , SN are electrically connected to one another, and drains of the plurality of power switches S1, S2, . . . , SN are electrically connected to one another. The logic gates 223 output the first control signal set ϕ1,k to the gates g of the power switches S1, S2, . . . , SN of the first switch group G1, respectively, and generally synchronously outputs the first control signal set ϕ1,k to the gates g of the power switches S1, S2, SN of the third switch group G3, respectively, in which the control signals ϕ1,0, ϕ1,1, . . . , ϕ1,N−1 of the first control signal set ϕ1,k have a one-to-one relationship with the plurality of power switches S1, S2, . . . , SN.
According to one embodiment, the capacitor is a total flying capacitance, but not limited to this.
In conjunction with
The clock divider 2231 divides the control signal CLK into N control signals with equal phase difference, comprising a first clock signal ϕ0 and N−1 control signals ϕj with equal phase difference. The clock divider 2231 outputs the first clock signal ϕ0 to the non-overlapping signal generator 2235 and outputs the N−1 control signals ϕj with equal phase difference to the AND gate array 2239, in which j={xπ/N|1≤x<N−1, x∈N}.
According to one embodiment, the clock divider 2231 may be shown in
The non-overlapping signal generator 2235 converts the first clock signal ϕ0 into two positive half-periods and non-overlapping first main control signal ϕ1,0 and the second main control signal ϕ2,0, so that the first main control signal ϕ1,0 and the second main control signal ϕ2,0 are mutually inverted signals or independent signals.
According to one embodiment, the non-overlapping signal generator 2235 may comprises an inverter 2236, two inverters 2237, and two delay units 2238 as shown in
The AND gate array 2239 converts the first main control signal ϕ1,0 and the N−1 control signals ϕj with equal phase difference into the first control signal set ϕ1,k, and converts the second main control signal ϕ2,0 and the N−1 control signals ϕj with equal phase difference into the second control signal set ϕ2,k.
According to one embodiment, the AND gate array 2239 may be shown in
With the above design and arrangement, the phases of the first and second control signal sets ϕ1,k, ϕ2,k are delayed in sequence by ½N cycle time T, respectively, and the duty cycles of the first and second control signal sets ϕ1,k, ϕ2,k are reduced in sequence by 1/N duty cycle T/2 (as shown in
In summary, the switched-capacitor DC/DC voltage converter and the control method disclosed in the present invention have low output ripple, and the voltage conversion circuit maintains a conventional simple structure and reduced cost. The control signal of the control circuit can be generated by the existing interleaved clock signal with simple logic gates, thereby reducing the production complexity. The control characteristics are scalable, and can be applied to a wide range of interleaved control stages after being stacked number. In addition, the switched-capacitor DC/DC voltage converter and its control method disclosed in the present invention only modulate the charging and discharging process of the voltage conversion circuit in an open-loop manner, so it is compatible with the existing closed-loop ripple reduction technology.
While various embodiments in accordance with the disclosed principles are described above, it should be understood that they are presented by way of example only, and are not limiting. Thus, the breadth and scope of exemplary embodiment(s) should not be limited by any of the above-described embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.
Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 109123183 | Jul 2020 | TW | national |
