Switched capacitor integrator that shares a capacitor for input signal and reference signal

Abstract

A switched capacitor integrator that shares a switched capacitor CAP1 at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor CAP1 with a first clock signal CK3; transferring an input voltage IN onto the capacitor CAP1 with a second clock signal CK1′; applying a reference voltage REF to a first end of the capacitor CAP1 with a third clock signal CK2; and coupling a second end of the capacitor CAP1 to the integrator with the third clock signal CK2 while the reference voltage REF is applied to the first end of the capacitor CAP1.

Description

FIELD OF THE INVENTION

This invention generally relates to electronic systems and in particular it relates to an improved switched capacitor integrator circuit.

BACKGROUND OF THE INVENTION

For low power, it is desirable to share the input and reference capacitors in a switched-capacitor integrator. Unfortunately, this means that the circuit driving the integrator input must discharge this capacitor of the reference charge left over from the previous cycle, then charge it with the input signal. This requires higher bandwidth and power from the driver.

For low power, it is desirable to share a single switched capacitor at the input of an integrator for both the signal input and the reference capacitor. This reduces the total input capacitance by a factor of 4 (for the same KT/C noise) and greatly reduces the load, which the integrator's opamp must drive, thereby allowing it to use less power. Unfortunately, this capacitor sharing causes a few problems. One is the fact that the circuit which drives the input to the integrator must not only charge the input capacitor with signal charge, it must also discharge this capacitor of the charge left on the capacitor from the reference feedback of the previous half-cycle. Normally this would require a high-bandwidth (high power) driving circuit to charge this capacitor.

SUMMARY OF THE INVENTION

A switched capacitor integrator that shares a switched capacitor at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor with a first clock signal; transferring an input voltage onto the capacitor with a second clock signal; applying a reference voltage to a first end of the capacitor with a third clock signal; and coupling a second end of the capacitor to the integrator with the third clock signal while the reference voltage is applied to the first end of the capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is schematic circuit diagram of a portion of a preferred embodiment switched capacitor integrator circuit;

FIG. 2 is a phase diagram of the clocking signals for the circuit of FIG. 1 ;

FIG. 3 is a schematic circuit diagram of a preferred embodiment differential switched capacitor integrator circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A portion of a preferred embodiment switched capacitor integrator circuit is shown in FIG. 1 . In order to simplify the description of the circuit, only the portion of the circuit connected to one of the differential inputs and one of the differential outputs of the amplifier is shown. The circuit of FIG. 1 includes: amplifier AMP; transistors M 1 -M 5 ; capacitors CAP 1 -CAP 3 ; resistor R; input IN; reference node REF; clocking signals CK 1 , CK 2 , CK 3 , and CK 1 ′; and output OUT. The operation of the circuit of FIG. 1 is described using the phase diagram shown in FIG. 2 . CK 1 is the sampling phase. CK 2 is the reference and integrate phase. CK 3 is the discharge phase. CK 1 ′ is the modified sampling phase. The circuit of FIG. 1 uses a third clock phase CK 3 to discharge the input capacitor CAP 1 before phase CK 1 ′ switches high to begin the input sampling phase. This greatly relaxes the bandwidth requirement for the input driver, and even allows the use of a passive anti-alias filter. For example, the resistor R and capacitor CAP 3 , shown in FIG. 1 , provide a simple first order passive anti-alias filter. In the prior art devices, an active filter or buffer is required because otherwise the filtered input signal would be corrupted by the reference charge remaining on the input sampling capacitor from the previous integration cycle. Many other passive filter configurations, which are well known in the art, could be used in place of resistor R and capacitor CAP 3 .

Shown in FIG. 3 is a preferred embodiment differential switched capacitor integrator circuit. The circuit of FIG. 3 includes: amplifier AMP 1 ; capacitors C 0 -C 3 ; switches (transistors) MN 0 , MN 1 , MN 6 , and MN 7 ; switches S 1 -S 4 which include transistors MN 4 , MP 0 , MN 5 , MP 2 , MN 9 , MP 3 , MN 8 , and MP 4 ; inverters INV 1 and INV 2 which include transistors MN 18 , MP 20 , MN 19 and MP 21 ; inputs INP and INM; references REFP and REFM; clocking signals N 1 , N 2 , N 3 , N 1 D, N 2 D, P 1 D, and P 2 D; input middle voltage VMIDI; output middle voltage VMIDO; outputs OUTP and OUTM; bias current IBIAS; power down signal PDN; and supply voltages AVDD and AVSS.

The operation of the differential integrator shown in FIG. 3 consists of three distinct phases: a reset phase, a sampling phase, and an integration phase. During the reset phase, the differential charge remaining on the input sampling capacitors C 1 and C 2 from the previous integration phase is discharged by turning on transistors MN 0 , MN 7 and MN 25 . During the sampling phase, the differential input voltage INP and INM is sampled onto the input sampling capacitors C 1 and C 2 by turning on transistors MN 0 , MN 4 , MN 7 , MN 9 , MP 0 and MP 3 . During the integration phase, the differential reference voltage REFP and REFM is applied to the bottom plates of the input sampling capacitors C 1 and C 2 and the top plates of these capacitors C 1 and C 2 are connected to the inputs of the differential amplifier AMP 1 by turning on transistors MN 1 , MN 5 , MN 6 , MN 8 , MP 2 and MP 4 . This allows the differential charge ((INP−REFP)*C 2 ,(INM−REFM)*C 1 ) to be transferred to the integrating capacitors C 3 and C 0 .

This operation is accomplished by providing the following clock signals, controlling the switching transistors:

	Phases
	Clock	Reset	Sampling	Integration	Controls
	N1	HI	HI	LO	MN0, MN7
	N1D	LO	HI	LO	MN4, MN9
	P1D	HI	LO	HI	MP0, MP3
	N2	LO	LO	HI	MN1, MN6
	N2D	LO	LO	HI	MN5, MN8
	P2D	HI	HI	LO	MP2, MP4
	N3	HI	LO	LO	MN25

Note that clocks P 1 D and P 2 D are complementary versions of clocks N 1 D and N 2 D respectively. Also, clocks N 2 and N 2 D appear to be the same, but in the actual implementation clock N 2 D is a slightly delayed version of clock N 2 . This difference is important to the performance of the integrator. Although switches S 1 -S 4 are complementary (parallel NMOS and PMOS transistors), and switches MN 0 , MN 1 , MN 7 , and MN 6 are NMOS transistor only, other types of switches can be used.

The integrator circuit of FIG. 1 shows a switch M 3 controlled by clock phase CK 3 going from the sampling capacitor CAP 1 to ground. This switch M 3 and its mate in the other half of the differential circuit are replaced by a single switch MN 25 in the differential circuit of FIG. 3 which differentially connects the bottom plates of the sampling capacitors C 1 and C 2 . Either scheme—two switches to ground or a single differential switch—can be used.

One of the advantages of the preferred embodiment circuit is that it does not add power to the integrator or the driver, and it only requires a small amount of area.

While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A circuit comprising:an amplifier; a first capacitor coupled between a first input of the amplifier and a first output of the amplifier; a first switch coupled to the first input of the amplifier and controlled by the first clock signal; a second capacitor, the first switch is coupled between a first end of the second capacitor and the first input of the amplifier; a second switch coupled to a second end of the second capacitor for discharging the second capacitor in response to a second clock signal; a third switch coupled to the second end of the second capacitor for transferring a first input voltage onto the second capacitor in response to a third clock signal; a forth switch coupled between the second end of the second capacitor and a first reference node, the fourth switch is controlled by the first clock signal; a third capacitor coupled between a second input of the amplifier and a second output of the amplifier; a fifth switch coupled to the second input of the amplifier and controlled by the first clock signal; a fourth capacitor, the fifth switch is coupled between a first end of the fourth capacitor and the second input of the amplifier, the second switch is coupled between a second end of the fourth capacitor and the second end of the second capacitor for discharging the second and fourth capacitors in response to a second clock signal; a seventh switch coupled to the second end of the fourth capacitor for transferring a second input voltage onto the fourth capacitor in response to the third clock signal; and an eighth switch coupled between the second end of the fourth capacitor and a second reference node, the eighth switch is controlled by the first clock signal.

2. The circuit of claim 1 further comprising:a ninth switch coupled between the first end of the second capacitor and a common node, and controlled by the fourth clock signal; and a tenth switch coupled between the first end of the fourth capacitor and the common node, and controlled by the fourth clock signal.