Claims
- 1. A switched capacitor integrator electronic circuit comprising:a first unity gain buffer having an input and an output; a capacitor having first and second terminals; a first switch coupled between the output of the first unity gain buffer and the first terminal of the capacitor; a second unity gain buffer having an input and an output, the input being coupled to the first terminal of the capacitor; a second switch coupled between the second terminal of the capacitor and a first voltage node external to said electronic circuit; and a third switch coupled between the second terminal of the capacitor and a second voltage node external to said electronic circuit.
- 2. The circuit of claim 1 wherein the first switch and the third switch are controlled by a first clock signal, while the second switch is controlled by a second clock signal non-overlapping with the first clock signal.
- 3. The circuit of claim 1 wherein the second and third switches are controlled by a two phase non-overlapping clock.
- 4. The circuit of claim 3 wherein the first switch is controlled by the same phase of the clock as the third switch.
- 5. The circuit of claim 1 and further comprising a fourth switch coupled between the output of the second unity gain buffer and the input of the first unity gain buffer.
- 6. The circuit of claim 5 wherein the first switch and the third switch are controlled by a first clock signal, while the second switch and the fourth switch are controlled by a second clock signal non-overlapping with the first clock signal.
- 7. The circuit of claim 1 wherein the first, second and third switches comprise MOS transistors.
- 8. The circuit of claim 1 wherein the first and second buffers each comprise unity gain buffers.
- 9. The circuit of claim 8 wherein the first and second buffers each include a source follower.
- 10. A switched capacitor integrator electronic circuit comprising:a first unity gain buffer having an input and an output; a capacitor having first and second terminals; a first switch with a current path coupled between the output of the first unity gain buffer and the first terminal of the capacitor; a second unity gain buffer having an input and an output, the input being directly connected to the first terminal of the capacitor; a second switch with a current path coupled between the second terminal of the capacitor and a first voltage node external to said electronic circuit; and a third switch with a current path coupled between the second terminal of the capacitor and a second voltage node external to said electronic circuit.
- 11. A method of accumulating voltages, the method comprising:sampling a first externally applied input voltage and a second externally applied input voltage with a switched capacitor; adding the sampled voltage to a third voltage by coupling the switched capacitor to a first unity-gain amplifier; and providing a sum value of the sampled differential voltage and the third voltage to a second unity-gain amplifier.
- 12. The method of claim 11 wherein the third voltage is provided from an output of the second unity-gain amplifier.
- 13. The method of claim 11 wherein the third voltage is provided from an output of a third unity-gain amplifier.
Parent Case Info
This application claims priority under 35 U.S.C. §119(e)(1) of provisional application No. 60/173,162 filed Dec. 27, 1999.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
Entry |
M.S. Ghausi, “Electronic Device and Circuits: Discrete and Integrated” University of California at Davis, pp. 405-408, 429-435, 1985. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/173162 |
Dec 1999 |
US |