Switched-capacitor multilevel inverter with self-voltage-balancing for high-frequency power distribution system

Abstract

Switched capacitor multilevel inverter (SCMLI) configuration for high-frequency medium voltage applications is presented. A 5L-SCMLI basic configuration is further extended to 9L operation with a reduced number of active switches having self voltage boosting and balancing ability. Further, the proposed 9L-SCMLI is extended up to n level being considered as the basic configuration for the extension of horizontal extension (HE) and vertical extension (VE). A generalized switching table is provided for the proposed extensions. Design of the size of capacitor demonstrated for the proposed 9L-SCMLI.

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention generally relates to a switched capacitor multilevel inverter (SCMLI) and, more particularly, to a new family of hybrid SCMLI for high frequency power distribution system.

Background Description

NASA has introduced the high-frequency AC (HFAC) power distribution system (PDS) for space applications, as it offers several merits over the conventional DC power distribution. HFAC PDS is also an attractive solution to other applications like telecom, electric vehicles and renewable energy micro grids. The high frequency inverters have advantages like reduced high order hat monies and low current ripple harmonics in induction motor drives. Power converters play a major role in microgrids due to their advantages like being efficient, reliable, managed heat distribution and high power density. Multilevel inverters (MLIs) are one of the emerging converters owing to their several structural benefits in terms of easy extension, reduced voltage stress (dv/dt) and having equal load sharing and efficient energy harvesting making them highly suitable for various renewable energy applications. Among several MLIs, switched capacitor MLIs (SCMLI) are the most widely used because of the features of voltage boosting over conventional ones with reduced number of de sources. To generate a higher number of voltage levels, cascaded MLIs are taken into consideration aiming for reduced number of devices but it ends up having high blocking voltage and does not ensure the voltage boosting feature.

Hybrid MLIs having reduced semiconductor devices ensures their ability to have an increased number of levels either by cascading multiple units into each other or by providing a backend H-Bridge, but they suffer from the problems of high blocking voltage with an increased number of semiconductor elements. Cascading subunits of the SCMLI to obtain a desired output voltage with an increased number of capacitors attaining parallel connection attains high boosting ratio but suffers high blocking voltage, results in increased switching losses, conduction losses. However, the increased number of de sources with asymmetric configuration is capable to generate a desired output voltage level, but at the price of no boosting ability. A quasi Z-multilevel inverter with multiple switched capacitors are connected in series/parallel to generate high number of voltage level. Even though, the topology uses single dc source, the choosing of resonance circuit (both capacitance and inductance) value is difficult. A boost type inverter with increased number of switches and capacitors to generate a desired output voltage, which results in high cost of implementation as compared to others, is presented in. Several SC cells are being cascaded containing the same number of units in each cell having higher gain ratio with increased power losses, which results in lower efficiency and high heat dissipation because of high blocking voltage. A topology to generate a step up in voltage by providing isolation on both input and output side switching losses and high dv/dt has been presented. Increasing number of power switches with an aim of generating desired output voltage. Cross-switched MLI having high blocking voltage with reduced number of components with multiple structural configuration has been proposed. Employing a single dc source, topology in is very elegant for high frequency AC power source, however, at the price of increased number of semiconductor devices. An interesting way of cascading H-Bridge to acquire higher number of levels requires high cost of implementation with increased number of sources and capacitor count. Multiple dc sources connected in parallel to each other with series conversion for voltage step up results in high blocking voltage and low efficiency. Despite several attempts to reduce the complexity of the SCMLIs for HFAC PDS, the component count stands still high.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a new family of hybrid SCMLI employing a single voltage source with reduced components resulting in less implementation complexity and lower cost.

According to the invention, there is provided a novel five-level (5L) SCMLI for generating higher number of voltage levels with reduced number of components. The 5L SCMLI circuit generates a peak output voltage of magnitude twice the input voltage in five distinct voltage levels. This basic 5L SCMLI circuit is extended to the generation of a nine-level (9L) voltage SCMLI circuit. This extension of the 9L-SCMLI is made on the basis of structural modification of the basic 5L SCMLI circuit and generates a peak output voltage of magnitude twice the input voltage in nine distinct voltage levels. The 9L SCMLI circuit can be further extended horizontally (HE) or vertically (VE) by replicating a cell within the basic circuit to generate a higher number of higher voltage levels in multiple distinct voltage levels, the number of voltage levels being a function of the number of cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 is a schematic diagram of the hybrid 5L SCMLI circuit according the basic implementation of the invention;

FIG. 2 is a schematic diagram of the 9L SCMLI circuit derived from the 5L SCMLI shown in FIG. 1;

FIGS. 3A to 3D are schematic diagrams of the 9L SCMLI circuit of FIG. 2 showing modes of operation for a positive half cycle;

FIG. 4 is a schematic diagram illustrating a horizontal extension (HE) of the 9L SCMLI circuit based on a structural point of view to generate higher number of levels;

FIG. 5 is a schematic diagram illustrating a vertical extension (VE) of the 9L SCMLI circuit based on a structural point of view to generate higher number of levels;

FIG. 6 is a graph illustrating the nine-level output voltage waveform of the 9L SCMLI circuit;

FIGS. 7A to 7C are graphs illustrating variation of optimal capacitance versus resistive load (RL), frequency (f), and phase angle (Φ), respectively;

FIGS. 8A to 8D are schematic diagrams of the equivalent circuit of the 9L SCMLI at different modes;

FIGS. 9A to 9D are bar graphs illustrating power loss comparison at for the 9L SCMLI at a fundamental frequency of f=50 Hz;

FIGS. 10A to 10D are graphs of simulation waveforms of the 9L SCMLI circuit;

FIGS. 11A to 11C are graphs of experimental waveforms of the 9L SCMLI circuit;

FIGS. 12A to 12C are graphs of experimental waveforms of the 9L SCMLI circuit;

FIGS. 13A to 13C are graphs of experimental waveforms of the 9L SCMLI circcuit;

FIGS. 14A and 14B are graphs of experimental waveforms of the 9L SCMLI circuit;

FIGS. 15A to 15C are graphs of experimental waveforms of the 9L SCMLI circuit;

FIGS. 16A to 16D are graphs of experimental waveforms of a 13L SCMLI circuit;

FIGS. 17A to 17C are graphs of experimental waveforms of the 13LSCMILI circuit;

FIG. 18 is a pictorial representation of an experimental prototype model; and

FIG. 19 is a graph illustrating efficiency analysis of the 9L SCMLI w.r.t. to load variation at f=50 Hz.

DETAILED DESCRIPTION THE INVENTION

Referring now to the drawings, and more particularly to FIG. 1, there is shown the basic unit of the hybrid 5L SCMLI circuit according to the invention. It consists of a single DC power supply V_dc, a capacitor C_F, and seven switches S₁ to S₄ and P₁ to P₃ to generate a peak output voltage of magnitudetwice the input voltage. The circuit arrangement is topologically that of a bridge circuit within a bridge circuit. The outer bridge circuit comprises switches S₁ and P₁ in one series arm and switches S₃ and P₃ in a second series parallel arm, with switches S₁ and S₃ connected to a first junction 11 of the bridge, switches P₁ and P₃ connected to a second junction 12 of the bridge, switches S₁ and P₁ connected to a third junction 13 of the bridge, and switches S₃ and P₃ connected to a fourth junction 14 of the bridge. The inner bridge circuit, hereinafter referred to as the boosting circuit, comprises switch S₂ and power supply V_dc in one series arm and capacitor C_F and switch S₄ in a second series parallel arm, with switch S₂ and capacitor C_F each connected to the first junction 11 and power supply V_dc, and switch S₄ each connected to the second junction 12. Switch P₂ is connected between a fifth junction 15 of switch S₂ and power supply V_dc and a sixth junction 16 of capacitor C_r and switch S₄. Finally, a load is connected across the third and fourth junctions 13 an 14 to complete the circuit.

For the 5L SCMLI circuit of FIG. 1, the switching scheme listed in Table 1 includes the state of the diode and capacitor to have a better and quick understanding of the current path for each cycle. At level +1 Vdc, capacitor CF gets charged. Similarly, at level 0 the capacitor CF also gets charged. At level ±2 Vdc capacitor CF is discharging and its voltage remains unchanged for level −1 Vdc. Therefore the 5L SCMLI inverter is equipped with self-voltage balancing and voltage boosting ability with reduced semiconductor elements, decreasing the cost of implementing and as such does not required additional circuitry for balancing capacitor voltage, which reduces the complexity in the converter design.

TABLE 1
Switching Scheme of 5L SCMLI
Voltage	Switches	Capacitor
levels	S1	S2	S3	S4	P1	P2	P3	CF
+1 Vdc	0	1	1	1	1	0	0	C
+2 Vdc	0	0	1	0	1	1	0	D
0	1	1	1	1	0	0	0	C
−1 Vdc	1	1	0	1	0	0	1	—
−2 Vdc	1	0	0	0	0	1	1	D

A 9L SCMLI inverter is shown in FIG. 2, and it is derived from the 5L SCMLI inverter of FIG. 1 by adding an H-bridge in the backend to change the polarity and capacitors are attached in series/parallel to each other to achieve the desired output voltage. The 9L SCMLI inverter topology comprises two parallel bridge circuits and comprises eight switches, two diodes and two capacitors for generating a peak output of twie the input voltage which comprises nine distinct output voltage levels: ±2 V_dc, ±3 V_dc/2, ±V_dc, ±V_dc/2, and 0. The first bridge circuit comprises a first arm of the power supply V_dc connected in series with a diode D₁ and a second parallel arm of a switch S₈ connected in series with two series connected capacitors C₁ and C₂. Diode D₁ and capacitor C₂ are connected to a first junction 21, and power supply V_dc and switch S₈ are connected to a second junction 22. Switch S₁ is connected between a third junction 23 of power supply V_dc and diode D₁ and a fourth junction 24 of switch S₈ and capacitor C₁. The second bridge circuit comprises a first arm of switches S₆ and S₄ connected in series and a second parallel arm of switches S₇ and S₅ connected in series. Switches S₄ and S₅ are connected to a fifth junction 25, while switches S₆ and S₇ are connected to a sixth junction 26. The fifth junction 25 is connected to the first junction 21 via switch S₂, while the sixth junction 26 is directly connected to the second junction 22. In addition, a seventh junction 27 between capacitors C₁ and C₂ is connected to the fifth junction 25 via series connected switch S₃ and diode D₂. Finally, the load is connected between an eighth junction 28 between switches S₄ and S₆ and a ninth junction 29 between switches S₅ and S₇.

The different modes of operation for the 9L SCMLI inverter shown in FIG. 2 and, for a better understanding, current path is also shown in FIGS. 3A to 3D for positive half cycle, where i₀ represents the direction of current. During +V_dc/2, FIG. 3A first positive level, and +V_dc, FIG. 3B second positive level, both capacitors C₁ and C₂ are charged initially generating an output voltage equivalent to +V_dc/2 and +V_dc, respectively. While, during +3 V_dc/2, FIG. 3C third positive level, capacitor C₁ is discharged to generate output voltage equivalent to +3 V_dc/2. Then, during +2V_dc, FIG. 3D fourth positive level, both capacitors C₁ and C₂ are discharged collectively generating output voltage equivalent to +2 V_dc and so on, as during +V_dc and +2V_dc both capacitors are charged and discharged collectively sharing the same charging and discharging current; therefore, maintaining the constant output current. Whereas, the primary function of the backend H-bridge is to operate at fundamental cycle and change the polarity of the output voltage switching S₄ and S₇ on for positive half, S₅ and S₆ on for negative half and also to generate zero level as switches S₄ and S₅ are turned on. Some of the prominent features of the 9L-SCMLI inverter has the following features:

• • Generates output voltage of magnitude twice the input voltage (V_out=2 V_in).
  • Only eight power switches, two diodes, single source and two capacitors are used to generate desired output voltage requiring reduced number of components are required.
  • Does not require additional circuits for balancing capacitors voltage as it has self-balancing and self-voltage boosting ability with reduced complexity.

The 9L-SCMLI inverter can be further extended based on the structural point of view to generate higher number of levels in all possible directions to generate desired output voltage. The possible ways of extension can be achieved in two ways: horizontal extension (HE) and vertical extension (VE), which are discussed in detail below.

FIG. 4 shows the extension of the 9L-SCMLI inverter in the horizontal direction to generate higher number of levels and is here after referred to as 9L-SCMLI (HE). It can be extended up to N^th cell as 1^st cell, 2^nd cell . . . N^th cell. Each cell contains a desired number of units having same configuration throughout the circuit up to its extension, which can be extended as switches S₁₁, S₁₂, S₁₃ . . . , S_1n. Similarly, switches S₂₁, S₂₂, S₂₃, . . . , S_2n, switches S₃₁, S₃₂, S₃₃, . . . , S_3n and switches S₄₁, S₄₂, S₄₃, . . . , S_4n, diodes D₁₁ and D₂₁ and capacitors C₁₁ and C₂₁ are extended in the same manner. As capacitors C₁₁ and C₂₁ are connected in parallel to each other, it provides a step up in voltage. Further, operation of the 9L-SCMLI (HE) is discussed in brief.

Generalised switching pattern of the proposed 9L-SCMLI (HE) is listed in Table 2, which can be generated with the help of FIG. 4 as it represents the extension of the 9L-SCMLI inverter in the horizontal direction up to n. Further, the charging and discharging of capacitors C₁₁, C₁₂, C₁₃, . . . , C_1n and capacitors C₂₁, C₂₂, C₂₃, . . . , C_2n) are similar to Table 2. When opted for higher number of voltage levels, capacitors are charged for a longer period. While, discharging period of capacitors decreases for higher number of voltage levels. In order to validate the following results, generalized equations (1) to (6) are provided.N_L=4n+1  (1)N_cap=2(n−1)  (2)N_d=2(n−1)  (3)N_sw=N_driver=4n  (4)V_max=nV_dc  (5)V_in:V_ont=1:n  (6)where N_sw represents number of switches, k_cap is the number of capacitors, N_d is the number of diodes, N_L is the number of voltage levels and V_max is the maximum output voltage, where, n is dependent upon maximum gain to be generated as it satisfies the condition n=2.

TABLE 2
Generalized Switching Pattern for HE
Output	On state of switches
Voltage	S11,	S21,	S31,		S4, S5,	Diodes conducting state	Capacitor States
(Vo)	S12, . . . , S1n	S22, . . . , S2n	S32, S3n	S41, . . . , S4n	S6, S7	D11, . . . , D1n	D21, . . . , D2n	C11, . . . , C1n	C21, . . . , C2n
+Vdc/2	-, . . . , -	S21 . . . S2(n−1)	S3n, -. . .-	S41 . . . S4n	S4, S7	D11 . . . D1n	-. . .-, D2n	C, C . . . , C	C, C . . . , C
+Vdc	-, . . . , -	S21 . . . S2n	-. . .-	S41 . . . S4n	S4, S7	D11 . . . D1n	-, . . . , -	C, C . . . , C	C, C . . . , C
+3 Vdc/2	-. . .-, S1n	S21 . . . S2(n−1)	S3n, -. . .-	S41 . . . S4(n-1)	S4, S7	D11 . . . D1(n−1)	-. . .-, D2n	C, . . . , C, D	C, . . . C, -
+2 Vdc	-. . .-, S1n	S21 . . . S2(n−1)	-, . . .-	S41 . . . S4(n-1)	S4, S7	D11 . . . D1(n−1)	-, . . . , -	C, . . . , C, D	C . . . C, D
+5 Vdc/2	-. . .-S1(n−1)	S21 . . . S2(n−2)	S3(n−1),	S41 . . . S4(n-2)	S4, S7	D11 . . . D1(n−2)	-. . .-, D2(n−1)	C . . . C, D, D	C . . . C, -, D
	S1n		-. . .-
+3 Vdc	-. . .-S1(n−1)	S21 . . . S2(n−2)	-, . . .-	S41 . . . S4(n-2)	S4, S7	D11 . . . D1(n−2)	-, . . . , -	C . . . C, D, D	C . . . C, D D
	S1n
. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .
+(n + 1)	S11 . . . S1n	S21 . . . S2n	-, . . . , -	-, . . . , -	S4, S7	-, . . . , -	-, . . . , -	D, D, . . . , D	D, D, . . . , D
Vdc
−(n + 1)	S11 . . . S1n	S21 . . . S2n	-, . . . , -	-, . . . , -	S5, S6	-, . . . , -	-, . . . , -	D, D, . . . , D	D, D, . . . , D
Vdc
0 · Vdc	-, . . . , -	-, . . . , -	-, . . . , -	-, . . . , -	S4, S5	-, . . . , -	-, . . . , -	-, . . . , -	-, . . . , -
* - = OFF state and . . . = Continuation of previous states.

FIG. 5 shows the extension of the 9L-SCMLI inverter in a vertical configuration and hereafter referred to as 9L-SCMLI (VE). As it can be extended up to N^th cell, each cell containing an acquired number of units of two switches S₁₂, S₂₂, . . . , S_n2) and switches S₁₄, S₂₄, . . . , S_n4), three diodes D₁₁, D₂₁, . . . , D_n1) and diodes D₁₂, D₂₂, . . . , D_n2) and two capacitors C₁₁, C₁₂, . . . , C_1n) and capacitors C₁₂, C₂₂, . . . , C_n2) connected in parallel to each other to provide a stepped up output voltage. Equations (7) to (12) correspond to 9L-SCMLI (VE) for extending up to n and can be validated with the help of FIG. 5, where, n is dependent upon maximum gain to be generated as it satisfies the condition n≥2. Generalized switching pattern of the proposed extension can be seen from Table 3 for generating (n+1) V_d, voltage levels. Charging and discharging of capacitors with respect to desired voltage level can be seen from Table 3N_L=4n+1  (7)N_cap=2(n−1)  (8)N_d=2(n−1)  (9)N_sw=N_driver=3n+2  (10)V_max=nV_dc  (11)V_in:V_out=1:n  (12)

The determination of a suitable capacitance value is another important factor for SCMLI topologies. Here, the determination of capacitance for the proposed 9L-SCMLI is discussed. For determining the value of capacitance, longest discharging cycle (LDC) of each capacitor is taken into account. To aid this, FIG. 6 representing the waveform of the proposed 9L-SCMLI at fundamental frequency is included.

TABLE 3
Generalized Switching Pattern for the VE
Output	On state of switches	Diodes conducting state	Capacitor States
Voltage		Sn2 . . . S22,	Sn3 . . .		S4, S5,	Dn2, . . . D22,		Cn1 . . . C21,	Cn2 . . . C22,
(Vo)	S11	S12	S32S13	Sn4 . . . S24, S14	S6, S7	D21	D21, . . . , D2n	C11	C12
+Vdc/2	-, . . . , -	-, . . . , -	S3n, -, . . . , -	Sn4 . . . S24, S14	S4, S7	D11, D21 . . . Dn1	Dn2, -, . . . , -	C, C, . . . , C	C, C, . . . , C
+Vdc	-, . . . , -	Sn2, - . . . -	-. . .-	Sn4 . . . S24, S14	S4, S7	D11, D21 . . . Dn1	-, . . . , -	C, C, . . . , C	C, C, . . . , C
+3 Vdc/2	-, . . . , -	S(n−1)2, - . . . -	S3n, -, . . . , -	S(n−1)4, . . . S14	S4, S7	D(n−1)1, . . . , D11	Dn2, -, . . . , -	D, C, . . . , C	-, C, C, . . . C
+2 Vdc	-, . . . , -	Sn2, S(n−1)2 - . . .	-, . . ., -	S(n−1)4, . . . S14	S4, S7	D(n−1)1, . . . , D11	-, . . . , -	D, C, . . . , C	D, C, . . . , C
+5 Vdc/2	S11	-, . . . , -	S(n−1)3, -. . .-	S(n−2)4, . . . S14	S4, S7	D(n−2)1, . . . , D11	D(n−1)2, . . . ,	D, D, C, . . . , C	D, -, C, . . . , C
							D12
+3 Vdc	S11	Sn2, -, S(n−2), - .	-, . . . , -	S(n−2)4, . . . S14	S4, S7	D(n−2)1, . . . , D11	-, . . . , -	D, D, C, . . . , C	D, D, C, . . . , C
. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .	. . .
+(n + 1)	-, S11 . . .	Sn2, . . . , S12	-, . . . , -	S(n−1)4, . . . S14	S4, S7	D(n−1)1, . . . , D11	-, . . . , -	D, D, . . . , D	D, D, . . . , D
Vdc
−(n + 1)	-, S11 . . .	Sn2, . . . , S12	-, . . . , -	S(n−1)4, . . . S14	S5, S6	D(n−1)1, . . . , D11	-, . . . , -	D, D, . . . , D	D, D, . . . , D
Vdc
0 · Vdc	-, . . . ,-	-, . . . , -	-, . . . , -	-, . . . , -	S4, S5	-, . . . , -	-, . . . , -	-, . . . , -	-, . . . , -

As evident, LDC for both capacitors C₁ and C₂ occur in both positive and negative cycles at different time intervals from different voltage levels. Therefore, maximum discharging value for each capacitor can be concluded from the following equations:

$\begin{array}{cc}{Q}_{C1}=2\times {\int }_{T_3}^{T/4}{I}_L\left(t\right)\mathrm{dt}& \left(13\right)\\ Q_{C2}=2\times {\int }_{T4}^{T/4}{I}_L\left(t\right)\mathrm{dt}& \left(14\right)\end{array}$ Here, Q_Ci for =1, 2 represents the maximum discharging amount of capacitors. In equation, k×V_dc represents maximum allowable voltage ripple of capacitors, optimum value of capacitors can be obtained from

$\begin{array}{cc}{C}_{\mathrm{opt}}i\ge \frac{Q_{Ci}}{k\times V_{dc}}& \left(15\right)\end{array}$ Considering the equation of load current for a pure resistive load (R_L) at third and fourth positive output voltages at steady-state conditions, the following can be derived:

$\begin{array}{cc}\begin{array}{cc}{I}_L\left(t\right)=\frac{3V_{dc}}{2R_L},& t_3\le t\le \frac{T}{4}\end{array}& \left(16\right)\\ \begin{array}{cc}{I}_L\left(t\right)=\frac{2V_{dc}}{R_L},& t_4\le t\le \frac{T}{4}\end{array}& \left(17\right)\end{array}$ Further, the fundamental switching timing instants t₃ and t₄ are equal to 3 T/20 and T/5 and are obtained from cutting of DC levels to sinusoidal function of reference waveform. For resistive inductive loading condition function IL(t) can be expressed asI_L(t)=I_max sin(ωt−φ)  (18)

By solving (13) to (18) at given conditions, the optimum value of capacitors at pure resistive load and resistive-inductive load are shown in the following equation:

$\begin{array}{cc}{C}_{\mathrm{opt},i}\ge \frac{7\pi }{10R_L\times k\times \tilde{\omega }}& \left(19\right)\\ C_{\mathrm{opt},i}\ge \frac{2I_{\max }}{k\times V_{dc}\times \tilde{\omega }}\left[\cos \left(\frac{\pi }{10}-\phi \right)+\sin \left(2\frac{\pi }{5}+\phi \right)\right]& \left(20\right)\end{array}$

It is worth mentioning that equations (19) and (20) represent the optimum value of capacitors for the 9L-SCMLI, inverter which shows an inverse relation with k, ω and R_L from equation (19). To have a better understanding for determining appropriate value of capacitance, a graph is shown in FIG. 7A between C_opt and R_L at different values for an allowable voltage ripple keeping co fixed at the value 100π. From FIG. 7B, it can be concluded that a larger rate of allowable voltage ripple has led to smaller capacitance. By increasing the output frequency at different values of R_L, the value of optimum capacitance gets reduced but may lead to increase in switching losses at higher output frequency. In order to provide a better clarification, a graph is being plotted between different variations of C_opt at different values of output frequency at fixed resistive load R_L=200Ω for higher frequency at allowable voltage ripple.

On the other hand, optimum capacitance is varied for different angles of φ at allowable voltage ripple of 5 and 10%, where k=0.05 and k=0.1, considering a constant value for I_max=5 A, V_dc, =100 V, f=50 Hz and w=100 π at fundamental frequency. It can be concluded that as q) increases the value of capacitance decreases for the SCMLI as shown in FIG. 7C.

Power loss analysis of the 9L-SCMLI includes overall loss calculation, switching losses P_Sw, conduction losses P_Con and ripple losses P_Rip for both capacitors at fundamental frequency as maximum loss conditions are considered during calculations.

In general, switching losses occur during ON and OFF transition state of switches. To reduce the complexity, a linear approximation between voltage and current of switches is being considered for switching period. As an outcome, following equations are considered for switching losses:

$\begin{array}{cc}\begin{array}{c}{P}_{\mathrm{Sw},\mathrm{on},i}={\int }_0^{t_{on}}v\left(t\right)i\left(t\right)\mathrm{dt}\\ ={\int }_0^{t_{on}}\left[\left(\frac{V_{\mathrm{sw},i}}{t_{\mathrm{on}}}t\right)\left(-\frac{I_i}{t_{\mathrm{on}}}\left(t-t_{\mathrm{on}}\right)\right)\right]\mathrm{dt}\\ =\frac{1}{6}{V}_{\mathrm{sw},i}{I}_i{t}_{\mathrm{on}}\end{array}& \left(21\right)\\ \begin{array}{c}{P}_{\mathrm{Sw},\mathrm{off},i}={\int }_0^{t_{\mathrm{off}}}v\left(t\right)i\left(t\right)\mathrm{dt}\\ ={\int }_0^{t_{\mathrm{off}}}\left[\left(\frac{V_{\mathrm{sw},i}}{t_{\mathrm{off}}}t\right)\left(-\frac{{I^{\prime }}_i}{t_{\mathrm{off}}}\left(t-t_{\mathrm{off}}\right)\right)\right]\mathrm{dt}\\ =\frac{1}{6}{V}_{\mathrm{sw},i}{I^{\prime }}_i{t}_{\mathrm{off}}\end{array}& \left(22\right)\end{array}$ where I_i and I′_i are currents through i^th switch, N_on and N_off is number of turn on and off a switch during fundamental cycle k. As a result to calculate total switching loss per one cycle can be written as follows:

$\begin{array}{cc}{P}_{\mathrm{sw},i}=\frac{1}{6T}\sum _{i=1}^7\left(\sum _{k=1}^{N_{on}}{P}_{\mathrm{sw},\mathrm{on},\mathrm{ik}}+\sum _{k=1}^{N_{\mathrm{off}}}{P}_{\mathrm{sw},\mathrm{off},\mathrm{ik}}\right)& \left(23\right)\end{array}$

In order to calculate total conduction losses at steady state, a pure resistive load (R_L) is considered. Based on the overall circuit analysis shown in FIGS. 8A to 8D, all possible operations are considered to calculate the maximum conduction loss. FIGS. 8A to 8D represent the equivalent circuit diagram for the 9L-SCMLI inverter. Pure resistive loading condition is considered because there should not exist any auxiliary current path between load current and output voltage to facilitate the charging of capacitors. Therefore, resistive loading condition is considered as worst condition for calculation of losses in SCMLIs

Hereafter, R_onD, R_ESR, R_onu represent internal resistance of power diode, equivalent series resistance of each capacitor and internal resistance of each switch. While VRS, VC and VF showcases reverse biased voltage of power diode, stored voltage of capacitor and forward biased voltage of power diode. By applying Kirchhoffs voltage law and Kirchhoffs current law for connecting nodes, the following equations are summarised. Equation (24) represents the charging current of involved capacitors for states ±V_dc/2 during operating mode (I_{L, I}). Similarly, in equation (25) for V_dc, as it also involves charging of capacitors at second operating mode (I_{L, II}). Equations (27) and (28) show third and fourth operating modes with respect to FIGS. 7C and 7D, respectively. Instantaneous value of conduction losses during operating modes I, II, III and IV are given in equations (28) to (31) as follows:2(R_onD+R_ESR)I_charging+(3R_onu+R_onDR_L)I_L,I+R_onD(I_charging+I_L,I)=V_dc−V_RS−2(V_c+V_F)  (24)2(R_onD+R_ESR)I_charging+(3R_onu+R_onDR_L)I_L,II+(I_L,II+I_charging)R_onD=V_dc+V_F−2V_c−V_RS)  (25)(4R_onu+R_onD+R_L+R_ESI)I_L,III=V_dc−V_F+V_c  (26)(4R_onu+R_L+2_ESR)I_L,IV=V_dc+2V_c  (27)As an outcome, to calculate the average value during full cycle of output voltage waveform for first, second, third and fourth voltage levels, corresponding time should be taken into considerationP_con,I=2(I_charging)²(R_onD±R_ESR)+(I_L,1)²(3R_onu+R_onD)+R_onD(I_L,I+I_charging)²  (28)P_con,II=2(R_onD+2R_ESR)(I_charging)²+3R_onu(I_L,II)²+R_onD(I_L,II+I_charging)²  (29)P_con,III=(4R_onu+R_onD+R_ESR)(I_L,III)²  (30)P_con,IV=(4R_onu+2R_ESR)(I_L,IV)²  (31)From FIGS. 8A to 8D, (t₂−t₁), (t₃−t₂), (t₄−t₃) and (T/4−t₄), respectively, are given in equations (32) to (35). As a result, the total conduction losses (P_con,T) over a full cycle output voltage are shown in equation (36).

$\begin{array}{cc}{\overline{P}}_{\mathrm{con},I}=\frac{4}{T}\left(t_2-t_1\right)P_{\mathrm{con},I}& \left(32\right)\\ {\overline{P}}_{\mathrm{con},\mathrm{II}}=\frac{4}{T}\left(t_3-t_2\right)P_{\mathrm{con},\mathrm{II}}& \left(33\right)\\ {\overline{P}}_{\mathrm{con},\mathrm{III}}=\frac{4}{T}\left(t_4-t_3\right)P_{\mathrm{con},\mathrm{III}}& \left(34\right)\\ {\overline{P}}_{\mathrm{con},{\mathrm{IV}}^{=}}\frac{4}{T}\left(\frac{T}{4}-t_4\right)P_{\mathrm{con},\mathrm{IV}}& \left(35\right)\\ {\overline{P}}_{con,T}={\overline{P}}_{\mathrm{con},I}+{\overline{P}}_{\mathrm{con},\mathrm{II}}+{\overline{P}}_{\mathrm{con},\mathrm{III}}+{\overline{P}}_{\mathrm{con},\mathrm{IV}}& \left(36\right)\end{array}$

Simulation results for power losses are compared in this section under dynamic load, where, conduction and switching losses of the 9L-SCMLI inverter are calculated for each switch. FIGS. 9A to 9D demonstrate the outcomes from loss calculation as discussed above, where P_{con_sw}, P_{sw_sw} represent conduction and switching losses in IGBT and P_{con_d}, P_{sw_d} represent conduction and switching losses in diode.

Only switch S₈ experiences maximum loss as compared to other switches. While switches present in H-bridge, that is S₄, S₅, S₆ and S₇ share almost equal losses and switch S₃ having the least. Overall, power loss for proposed topology is quite low.

Ripple losses usually occur when capacitors are connected in parallel for charging operation due to the difference between input voltage and voltage of capacitors. Therefore, voltage ripple of capacitors is shown in the following equation:

$\begin{array}{cc}\Delta V_{Ci}=\frac{1}{Ci}{\int }_{t^{\prime }}^t{i}_{\mathrm{Ci}}\left(t\right)dt& \left(37\right)\end{array}$

where [t−t] represents time interval of discharging modes in capacitors. Total value of ripples losses for a fundamental cycle can be seen from

$\begin{array}{cc}{P}_{Rip}=\frac{1}{2T}\sum _{i=1}^2{C}_i\Delta V_{Ci}^2& \left(38\right)\end{array}$

Since P_Rip is inversely proportional to the capacitance Ci, larger value of capacitance leads to increase in overall efficiency. Equations (39) and (40) represent total losses using which the overall efficiency of the proposed 9L-SCMLI can be deduced as below, where P_out is output power of the SCMLI inverter.

$\begin{array}{cc}{P}_{\mathrm{Loss}}=P_{\mathrm{Rip}}+P_{\mathrm{Con},T}+P_{\mathrm{sw}}& \left(39\right)\\ \eta =\frac{P_{\mathrm{out}}}{P_{\mathrm{out}}+P_{Loss}}& \left(40\right)\end{array}$

The simulation and experimental results validate the performance of the SCMLI according to the invention. Firstly, the SCMLIs were simulated in MATLAB/SIMUINK for values V_in=100 V with each capacitor of 470 μF having R_ESR=0.1Ω under dynamic load condition for fundamental frequency (f=50 Hz) and f=400 Hz-1 kHz. In order to verify the performance of the SCMLI experimentally, a laboratory prototype was fabricated using Semikron insulated gate bipolar transistors (IGBT SKM75GB063D switches) having R_onu=14 mΩ and power diode 25 HMR 120 with R_onD=3 mΩ and each capacitor of 470 μF were used. The dSPACE 1104 is used for generating the gate pulses at fundamental frequency of 50 Hz, while SKYPER-32-PRO-R as gate driver were used during implementation of prototype.

Both simulation waveforms of the 9LSCMLI at f=50 Hz and 1 kHz are shown in FIGS. 10A to 10D under R−L (R=50Ω, L=1 mH) load condition. While, experimental waveforms are shown in FIGS. 11a-c at f?=?50 Hz, 400 Hz and 1 kHz under R−L (R=50Ω, L=1 mil) load condition at different frequency having output voltage equal to 200V and output current equal to 4 A, as both capacitors voltage equal to 50V. However, waveforms shown in FIGS. 11A to 11C represent the performance of the 9L-SCMLI when opted for higher frequency at a fixed load condition. Dynamic load variation is done at f=400 Hz as shown in FIGS. 12A to 12C. Waveforms shown in FIGS. 11A to 11C highlight the feasibility of the SCMLI for load variation adaptability at higher frequency. Change in modulation index (m) is shown in FIGS. 13A to 13C. At m equal to 0.2, 0.4, 0.6 and 1 at f equal to 1 kHz. FIG. 12A represents a change in m from 0.2 to 0.4 causing change in output voltage and current waveform while the voltage across both the capacitors remains constant (capacitors are neither charged nor discharged). Similarly, as in FIG. 13B, while in FIG. 13C voltage across capacitors changes with change in in from 0.6 to 1. In conclusion, during change in m change in output voltage levels is observed as shown in FIG. 13A from 3L to 5L, FIG. 13B from 5L to 7L, FIG. 13C from 7L to 9L. Change in step input voltage from 100V to 200V is shown in FIG. 14A, generally. From low to high causing change in output voltage, current and voltage across capacitors represents the stability of the SCMLI under sudden change in input voltage at f=1 kHz. Switch voltage and current across switches S₂ and S₆ is shown in FIG. 14B at f=50 Hz under R−L (R=50Ω, L=1 mH) load condition. Feasibility of the proposed SCMLI under R−L (80Ω-100 mH) load condition is shown in FIGS. 15A and 15B.

Results of a31L-SCMLI (HE) are presented. As shown in FIGS. 16A and 16B, simulation results representing output voltage, current and voltage across capacitors is shown at f=50 Hz under R−L (R=65Ω, L=1 mH) load condition. Similarly, under the same load condition at f=400 Hz simulation results are shown in FIGS. 16C and 16D. While, experimental results are shown in FIGS. 17A and 17B representing the feasibility of the SCMLI under dynamic load variation and output voltage across capacitors is shown in FIG. 17C under R−L (R=65Ω, L=1 mH) load at f=50 Hz. In conclusion, the above discussed waveforms represent the operability of the SCMLI under dynamic conditions. The experimental prototype used for testing is shown in FIG. 18. FIG. 19 represents the efficiency graph for the proposed 9L-SCMLI w.r.t. to load variation at f=50 Hz having efficiency up to 97.08% (R=225Ω, L=1 mH).

While the invention has been described in terms of a preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims

1. A switched capacitor multilevel inverter (SCMLI) comprising: a single DC power supply providing an input voltage Vdc;a capacitor;first, second and third switches, the DC power supply and the first switch connected in a first circuit branch, the second switch and the capacitor connected in a second circuit branch parallel to the first circuit branch, and the third switch connected between a first junction of the DC power supply and the first switch and a second junction of the second switch and the capacitor to form a boosting circuit in a first bridge circuit configuration;fourth and fifth switches each connected to a third junction of the first switch and the capacitor of the bridge circuit, the fourth and fifth switches forming a third circuit branch;sixth and seventh switches each connected to a fourth junction of the DC power supply and the second switch of the bridge circuit, the sixth and seventh switches forming a fourth circuit branch parallel to the third circuit branch and the boosting circuit connected between the third and fourth junctions in a second circuit configuration; anda load connected between a fifth junction of the fourth and sixth switches and a sixth junction of the fifth and seventh switches, wherebythe first to seventh switches are operated to generate a peak output voltage of magnitude twice the input voltage in five distinct voltage levels,wherein the SCMLI only has seven switches which are the first, second third, fourth, fifth, sixth, and seventh switches.

2. A switched capacitor multilevel inverter (SCMLI) comprising: a single DC power supply providing an input voltage Vdc;first and second capacitors connected in series;a first diode connected in series with the DC power supply in a first circuit branch;a first switch connected in series with the series connection of the first and second capacitors in a second circuit branch;a second switch connected between a first junction of the DC power supply and the first diode and a second junction of the first switch and the series connection of the first and second capacitors to form a first bridge circuit configuration;third and fourth switches connected in a third circuit branch, and fifth and sixth switches connected in a fourth circuit branch parallel to the third circuit branch;a load connected between a third junction of the third and fourth switches and a fourth junction of the fifth and sixth switches to form a second bridge circuit configuration;a seventh switch connected between a fifth junction of the first diode and the second capacitor and a sixth junction of the third and fifth switches of the second bridge circuit configuration; andan eighth switch and a second diode connected in series between a seventh junction between the first and second capacitors and the sixth junction, wherebythe first to eighth switches are operated to generate a peak output voltage of magnitude twice the input voltage in nine distinct voltage levels,wherein the SCMLI only has eight switches which are the first, second third, fourth, fifth, sixth, seventh, and eighth switches.

3. A switched capacitor multilevel inverter (SCMLI), comprising: a basic structure with a first cell comprising a single DC power supply providing an input voltage Vdc;first and second capacitors connected in series;a first diode connected in series with the DC power supply in a first circuit branch;a first switch connected in series with the series connection of the first and second capacitors in a second circuit branch;a second switch connected between a first junction of the DC power supply and the first diode and a second junction of the first switch and the series connection of the first and second capacitors to form a first bridge circuit configuration;third and fourth switches connected in a third circuit branch, and fifth and sixth switches connected in a fourth circuit branch parallel to the third circuit branch;a load connected between a third junction of the third and fourth switches and a fourth junction of the fifth and sixth switches to form a second bridge circuit configuration;a seventh switch connected between a fifth junction of the first diode and the second capacitor and a sixth junction of the third and fifth switches of the second bridge circuit configuration; andan eighth switch and a second diode connected in series between a seventh junction between the first and second capacitors and the sixth junction, wherebythe first to eighth switches are operated to generate a peak output voltage of magnitude twice the input voltage in nine distinct voltage levels,wherein the basic structure only has eight switches which are the first, second third, fourth, fifth, sixth, seventh, and eighth switches,wherein the first and second capacitors, the first diode, the first and second switches, the seventh switch, and the eighth switch and second diode form the first cell; andone or more cells which replicate the first cell of the basic structure to generate a higher number of higher voltage levels in multiple distinct voltage levels, the number of voltage levels being a function of the number of cells.

4. The switched capacitor multilevel inverter (SCMLI) of claim 3, wherein the one or more cells are replicated horizontally.

5. The switched capacitor multilevel inverter (SCMLI) of claim 3, wherein the one or more cells are replicated vertically.