This disclosure relates generally to soft-start ramp circuits and, more particularly, to switched-capacitor soft-start ramp circuits.
A circuit board may include many discrete and/or integrated circuits powered from a single voltage supply (e.g., 1.8V, 3.3V, and/or 5.0V). When a circuit first powers up, it may have a low input impedance and, consequently, may draw a large amount of current from a power supply for a very short period of time. Such a large initial current draw may cause the power supply, which may be powering other circuits, to suffer a significant voltage sag or drop that can cause undesirable effects on other circuits connected to the power supply. To prevent a power supply voltage drop caused by a large initial current draw, designers implement soft-start circuits to slowly increase the voltage to a circuit or device being powered up. Such circuits reduce the voltage provided to a device when that device is in a low input impedance mode due to startup and, thus, reduces current draw by the device and the attendant possible power supply voltage drop.
Certain examples are shown in the above-identified figures and described in detail below. In describing these examples, like or identical reference numbers may be used to identify common or similar elements. The figures are not necessarily to scale and certain features and certain views of the figures may be shown exaggerated in scale or in schematic for clarity and/or conciseness. Although the following discloses example methods and apparatus, it should be noted that such methods and apparatus are merely illustrative and should not be considered as limiting. The example circuits described herein may be implemented using discrete components, integrated circuits (ICs), or any combination thereof.
Additionally, it is contemplated that any form of logic may be used to implement portions of apparatus or methods herein. Logic may include, for example, circuit implementations that are made exclusively in dedicated hardware (e.g., circuits, transistors, logic gates, hard-coded processors, programmable array logic (PAL), application-specific integrated circuits (ASICs), etc.), exclusively in software, exclusively in firmware, or some combination of hardware, firmware, and/or software. Accordingly, while the following describes example methods and apparatus, persons of ordinary skill in the art will readily appreciate that the examples are not the only way to implement such apparatus.
As described in detail below, the examples described herein may be used to provide switched-capacitor soft-start ramp generator circuits that provide power to a circuit. Such example circuits increase supply voltage provided to a circuit or device being powered up to reduce the likelihood that the power supply voltages may sag during current drain of the circuit or device while the same is initially powered. According to a first example, a first capacitor is selectively coupled to a reference voltage or an output by switches. In one example, the switches are alternated between closed and open states based on a clock signal. The output provides feedback that affects a reference voltage via a feedback circuit utilizing a device, such as, for example, a p-type metal-oxide semiconductor (PMOS), which is forced to operate in the saturation region by a current source. The current source and PMOS may be adjusted so that the reference voltage is slightly higher than the output voltage. Thus, on a subsequent clock cycle the output voltage will be increased to the reference voltage and the reference voltage will again be increased. Thus, while the circuit being powered is coming on line, the supply voltage provided thereto steadily increases. The resulting example output to the circuit being powered is, therefore, a series of substantially equal increasing voltage steps, as described below.
As the soft-start ramp generator 100 begins increasing the voltage to Vout, each iteration of the CLK signal produces a small increase in the voltage at Vout. Due to the charging behavior of the capacitors 102 and 112, the voltage increase to Vout is largest during the first iteration and increases by a smaller amount at each successive iteration. This creates an RC-like charging behavior for the soft-start ramp generator 100 as shown by the trace 302 in
In the example of
Additionally, although the example circuit 200 is shown having one bucket capacitor and one output capacitor, the bucket capacitor 202 and/or the output capacitor 204 may be implemented using more than one capacitor. For example, to achieve a particular capacitance ratio it may be necessary to place capacitors in parallel or series. This may be a desirable technique to use if, for example, inexpensive, commercially available capacitors with only a limited number of choices for capacitance values are used.
In the example of
The switches 206 and 208 as described in the example of
In the example circuit 200 of
Although the feedback circuit is shown using MP1 and the current source 210, any suitable circuit may be used to provide feedback from Vout to Vref. The goal of said feedback circuit is to keep the voltage of Vref slightly above the voltage of Vout during supply ramping.
Prior to powering up the load circuit(s), Vref and Vout exist at a steady state. Feedback is provided from Vout to Vref via a feedback circuit, which, when activated, causes Vref to have a slightly higher voltage than Vout. In the example circuit 200 of
At initial startup of the load circuit(s) (i.e., the load circuit(s) is/are first coupled to the output of the circuit 200), the capacitor 202 may be coupled to one of Vref or Vout via switches 206 and 208. The feedback circuit (i.e., the current source 210 and PMOS MP1) is activated, causing a small rise in the voltage at Vref relative to Vout.
To start a first switching cycle and increase the voltage at Vout, the switch 206 is closed (if necessary) and switch 208 is opened (if necessary) to couple the capacitor 202 to Vref. While switch 206 is closed, Vref charges the capacitor 202 to the voltage at Vref. As described above, owing to the feedback circuit (MP1 and 210), Vref has a slightly higher voltage than Vout.
Next, switch 206 opens and switch 208 closes, allowing the capacitor 202 to discharge, which increases the voltage at Vout and charges a second capacitor 204 (e.g., an output capacitor). As Vout increases, it provides feedback to MP1. As mentioned above, the example current source 210 forces a small amount of current through the source-drain terminals of MP1, which causes MP1 to operate in the saturation region, resulting in a small source-gate voltage at MP1. Vref responds to the increase in Vout by increasing due to the source-gate voltage of MP1, which remains the same or substantially the same, that is added to the value of Vout. Thus, the next time the switch 206 closes and the switch 208 opens, the capacitor 202 is again charged with a voltage Vref slightly higher than Vout. As the voltage at Vref increases, the source-drain voltage of MP1 also increases, causing MP1 to operate in saturation. In this way, Vout is increased in equal or substantially equal voltage steps with each cycle of the CLK and
As the operation of the circuit 200 iterates (i.e., CLK and
As an alternative to powering the load circuit(s) by repeatedly cycling the switches 202 and 204 after Vout reaches Vcc, any or all of the circuit 200 may be bypassed, including the capacitors 202 and/or 204, the switches 206 and/or 208, the current source 210, and/or the field-effect transistor MP1 to couple Vcc directly to the load(s) via some other means (not shown). Another option to power the load(s) may be to close both switches 206 and 208 and deactivate or bypass the current source 210, allowing any required load current to flow directly from Vcc to Vout via the switches 206 and 208.
As shown in
Q=C*(Vout′+Vsg)+nC*Vout′ (1)
Equation (2) shows the charge equation while the
Q=(n+1)C*Vout (2)
wherein Q is the total charge, Vout′ is the output voltage for the previous (or current) cycle, Vout is the output voltage for the subsequent cycle, and Vsg is the source-gate voltage of MP1. Using equations (1) and (2), equations (3) and (4) can be derived:
Vout′+Vsg+n*Vout′=(n+1)Vout (3)
Vout−Vout′=Vsg/(n+1) (4)
Equation 4 shows that the voltage step size can be controlled by defining appropriate values for the source-gate voltage for MP1 and/or the capacitance ratio for the capacitors 202 and 204. Equation 4 also illustrates that the voltage step size is independent of the absolute value of Vout, assuming that the source-gate voltage of MP1 and the capacitance ratio of the capacitors 202 and 204 remain constant.
The output voltage feeds back to the field-effect transistor (e.g., to the gate of MP1), causing the reference voltage to increase accordingly (block 412). For example, in the circuit 200 of
After the output voltage has ramped up, as an alternative to repeating the cycles, the method 400 may bypass any or all of the components in the circuit 200 (e.g., the current source, the switches, the capacitors or the field-effect transistor) to couple the voltage source directly to the output via an additional circuit. A third option to power the load may be to close both switches and deactivate the current source, allowing any required load current to flow directly from the voltage source to the output.
Although certain methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods and apparatus fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.