The present disclosure relates in general to circuits for audio devices, including without limitation personal audio devices such as wireless telephones and media players, and more specifically, to a switched mode amplifier including a switched mode converter for driving an audio transducer of an audio device.
Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a speaker driver including a power amplifier for driving an audio output signal to headphones or speakers.
In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to driving an audio output signal to an audio transducer may be reduced or eliminated.
In accordance with embodiments of the present disclosure, a switching power stage for producing a load voltage at a load output of the switching power stage, the load output comprising a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, may include a power converter comprising a power inductor and a first plurality of switches, wherein the power converter is configured to drive a power converter output terminal coupled to the first load terminal in order to drive the first load terminal, a linear amplifier configured to drive a linear amplifier output terminal coupled to the second load terminal in order to drive the second load terminal, a controller configured to control the first plurality of switches of the power converter and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.
In accordance with these and other embodiments of the present disclosure, a method may be provided for producing a load voltage at a load output of the switching power stage, the load output comprising a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, the switching power stage further comprising a power converter comprising a power inductor and a first plurality of switches, wherein the power converter is configured to drive a power converter output terminal coupled to the first load terminal in order to drive the first load terminal, and the switching power stage further comprising a linear amplifier configured to drive a linear amplifier output terminal coupled to the second load terminal in order to drive the second load terminal. The method may include controlling the first plurality of switches of the power converter and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.
Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
Loop filter 22 may comprise any system, device, or apparatus configured to receive an input signal (e.g., audio input signal VIN or a derivative thereof) and a feedback signal (e.g., audio output signal VOUT, a derivative thereof, or other signal indicative of audio output signal VOUT) and based on such input signal and feedback signal, generate a controller input signal to be communicated to converter controller 24. In some embodiments, such controller input signal may comprise a signal indicative of an integrated error between the input signal and the feedback signal. In other embodiments, such controller input signal may comprise a signal indicative of a target current signal to be driven as an output current IOUT or a target voltage signal to be driven as an output voltage VOUT to a load coupled to the output terminals of output stage 28.
Controller 24 may comprise any system, device, or apparatus configured to, based on an input signal (e.g., input signal INPUT), output signal VOUT, and/or other characteristics of switched mode amplifier 20, control switching of switches integral to power converter 26, switches integral to output stage 28, and/or one or more linear amplifiers integral to output stage 28, in order to transfer electrical energy from a power supply VSUPPLY to the load of switched-mode amplifier 20 in accordance with the input signal.
Power converter 26 may receive at its input a voltage VSUPPLY (e.g., provided by power supply 10), and may generate at its output a voltage VPC. In some embodiments, voltage VSUPPLY may be received via input terminals including a positive input terminal and a negative input terminal which may be coupled to a ground voltage. As described in greater detail in this disclosure (including, without limitation, in reference to
Turning briefly to
Turning again to
In some embodiments, an offset voltage may be added to each of the output of power converter 26 and the output of linear amplifier 60, to ensure that the voltage VAMP>0 at all times.
Accordingly, presence of linear amplifier 60 and its ability to increase the common mode voltage of the output terminals in response to low magnitudes of the output signal VOUT may minimize non-linearities of output signal VOUT as a function of the input signal received by controller 24, and permit crossing a magnitude of zero by audio output signal VOUT.
In operation of output stage 28B, controller 24 may activate (e.g., enable, close, turn on) switch 64 and deactivate (e.g., disable, open, turn off) switch 66 for positive values of audio output signal VOUT. As in output stage 28A, in output stage 28B, controller 24 may, as power converter output voltage VPC approaches the lower saturation limit, cause linear amplifier 60 to drive a non-zero linear amplifier output voltage VAMP to the second output terminal in order to increase a common mode voltage between the first output terminal and the second output terminal, allowing audio output signal VOUT to approach and cross zero. Above the lower saturation limit, controller 24 may cause linear amplifier 60 to drive a zero linear amplifier output voltage VAMP to the second output terminal such that audio output signal VOUT is equal to power converter output voltage VPC.
In operation of output stage 28C, controller 24 may activate (e.g., enable, close, turn on) switch 64 and deactivate (e.g., disable, open, turn off) switch 66 for positive values of audio output signal VOUT and activate switch 66 and deactivate switch 64 for negative values of audio output signal VOUT. When audio output signal VOUT is positive and as power converter output voltage VPC approaches the lower saturation limit, controller 24 may cause linear amplifier 60 to drive a non-zero linear amplifier output voltage VAMP to the second output terminal in order to increase a common mode voltage between the first output terminal and the second output terminal, allowing audio output signal VOUT to approach and cross zero. Above the lower saturation limit power converter output voltage VPC for positive values of audio output signal VOUT, controller 24 may cause linear amplifier 60 to drive a zero or approximately zero linear amplifier output voltage VAMP to the second output terminal such that audio output signal VOUT is equal to power converter output voltage VPC. Similarly, when audio output signal VOUT is negative and as power converter output voltage VPC approaches the lower saturation limit, controller 24 may cause linear amplifier 61 to drive a non-zero linear amplifier output voltage VAMP′ to the first output terminal in order to increase a common mode voltage between the first output terminal and the second output terminal, allowing audio output signal VOUT to approach and cross zero. Above the lower saturation limit of power converter output voltage VPC for negative values of audio output signal VOUT, controller 24 may cause linear amplifier 61 to drive a zero or approximately zerolinear amplifier output voltage VAMP′ to the first output terminal such that audio output signal VOUT is equal to the inverse of power converter output voltage VPC. In addition, controller 24 may be configured such that for positive voltages of audio output signal VOUT, it causes linear amplifier 61 to enter a high-impedance mode in which linear amplifier 61 does not drive any output voltage VAMP′, and for negative voltages of audio output signal VOUT, it causes linear amplifier 60 to enter a high-impedance mode in which linear amplifier 60 does not drive any output voltage VAMP. In equation form:
In operation of output stage 28D, controller 24 may activate switches 64 and 70 and deactivate switches 66 and 68 for positive values of audio output signal VOUT and activate switches 66 and 68 and deactivate switches 64 and 70 for negative values of audio output signal VOUT. As in output stage 28B, in output stage 28D, controller 24 may, as power converter output voltage VPC approaches the lower saturation limit, cause linear amplifier 60 to drive a non-zero linear amplifier output voltage VAMP to the second output terminal in order to increase a common mode voltage between the first output terminal and the second output terminal, allowing audio output signal VOUT to approach and cross zero. Above the lower saturation limit of power converter output voltage VPC, controller 24 may cause linear amplifier 60 to drive a zero linear amplifier output voltage VAMP to the second output terminal such that audio output signal VOUT is equal to power converter output voltage VPC.
In the foregoing discussion, embodiments are disclosed in which a capacitor 27 is coupled between the power converter output terminal and one of a first supply terminal having a first voltage and a second supply terminal having a second voltage, and embodiments are disclosed in which a capacitor 62 is coupled between the first load terminal and the second load terminal of switched mode amplifier 20. However, in these and other embodiments, a capacitor may be coupled between the first load terminal of switched mode amplifier 20 and one of the first supply terminal and the second supply terminal. In addition, in these and other embodiments, a capacitor may be coupled between the second load terminal of switched mode amplifier 20 and one of the first supply terminal and the second supply terminal.
As used herein, a “switch” may comprise any suitable device, system, or apparatus for making a connection in an electric circuit when the switch is enabled (e.g., activated, closed, or on) and breaking the connection when the switch is disabled (e.g., deactivated, open, or off) in response to a control signal received by the switch. For purposes of clarity and exposition, control signals for switches described herein are not depicted although such control signals would be present to selectively enable and disable such switches. In some embodiments, a switch may comprise a metal-oxide-semiconductor field-effect transistor (e.g., an n-type metal-oxide-semiconductor field-effect transistor).
As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.
This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.
All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.
The present disclosure claims priority to U.S. Provisional Patent Application Ser. No. 62/279,956, filed Jan. 18, 2016, which is incorporated by reference herein in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
3851269 | Szorc | Nov 1974 | A |
6348781 | Midya | Feb 2002 | B1 |
6617908 | Thomsen et al. | Sep 2003 | B1 |
6727752 | Skinner | Apr 2004 | B2 |
7084799 | Butler | Aug 2006 | B1 |
7265524 | Jordan | Sep 2007 | B2 |
7466194 | Mazda | Dec 2008 | B2 |
8242847 | Leong et al. | Aug 2012 | B1 |
8638168 | Signoff et al. | Jan 2014 | B1 |
8773196 | Delano | Jul 2014 | B2 |
9088211 | Ivanov | Jul 2015 | B2 |
9628033 | King et al. | Apr 2017 | B2 |
9647611 | Embar et al. | May 2017 | B1 |
20030122615 | Zeff | Jul 2003 | A1 |
20030222713 | Skinner et al. | Dec 2003 | A1 |
20040169552 | Butler | Sep 2004 | A1 |
20050083115 | Risbo | Apr 2005 | A1 |
20070229332 | Tsividis | Oct 2007 | A1 |
20080111622 | Sperlich et al. | May 2008 | A1 |
20080310046 | Menegoli et al. | Dec 2008 | A1 |
20090027247 | Kumamoto et al. | Jan 2009 | A1 |
20090212859 | Lesso et al. | Aug 2009 | A1 |
20100214024 | Jones et al. | Aug 2010 | A1 |
20100237941 | Goldfarb et al. | Sep 2010 | A1 |
20120306575 | Shah et al. | Dec 2012 | A1 |
20140028395 | Chan et al. | Jan 2014 | A1 |
20150071464 | Du et al. | Mar 2015 | A1 |
20150222184 | Melanson | Aug 2015 | A1 |
20150323947 | Amadi et al. | Nov 2015 | A1 |
20160056707 | Wong et al. | Feb 2016 | A1 |
20170207755 | He et al. | Jul 2017 | A1 |
20170207759 | He et al. | Jul 2017 | A1 |
20170271996 | King et al. | Sep 2017 | A1 |
20170272043 | King et al. | Sep 2017 | A1 |
20170272044 | Melanson et al. | Sep 2017 | A1 |
Number | Date | Country |
---|---|---|
1367704 | Dec 2003 | EP |
2510395 | Dec 1984 | GB |
2546576 | Jul 2017 | GB |
2548443 | Sep 2017 | GB |
S59224905 | Dec 1984 | JP |
9857422 | Dec 1998 | WO |
2007136800 | Nov 2007 | WO |
2017127353 | Aug 2014 | WO |
2017127132 | Jul 2017 | WO |
2017160520 | Sep 2017 | WO |
2017160522 | Sep 2017 | WO |
2017160556 | Sep 2017 | WO |
Entry |
---|
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2016/040072, dated Sep. 16, 2016, 10 pages. |
Combined Search and Examination Report under Sections 17 and 18(3) of the UKIPO, Application No. GB1701269.1, dated Jul. 7, 2017. |
Eynde, Frank O. On the relationship between the CMRR or PSRR and the second harmonic distortion of differential input amplifiers, IEEE Journal of Solid-State Circuits, Volume: 24, Issue: 6, Dec. 1989, pp. 1740-1744. |
Combined Search Report and Written Opinion, GB Application No. 1617096.1, dated Apr. 7, 2017. |
Search Report, GB Application No. 1619679.2, dated Apr. 28, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/020927, dated May 26, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/021351, dated May 26, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/013756, dated May 30, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3) of the UKIPO, Application No. GB1703492.7, dated Aug. 31, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3) of the UKIPO, Application No. GB1703865.4, dated Aug. 31, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/US2017/020911, dated Nov. 7, 2017. |
Number | Date | Country | |
---|---|---|---|
20170207755 A1 | Jul 2017 | US |
Number | Date | Country | |
---|---|---|---|
62279956 | Jan 2016 | US |