A switched mode power supply (SMPS) uses semiconductor switching techniques to transfer power from an input power source to a load. The SMPS may include an energy storage element (such as an inductor, a capacitor, a transformer, etc.) and switches. Through the operation of the switches, the energy storage element can continuously switch between a charging state and a discharging state in each switching cycle. A controller of the SMPS can determine the on-time and off-time of the switches, which can reflect the time durations of the charging and discharging states in a switching cycle, so the SMPS can provide a desired power to the load.
An apparatus comprises an amplifier, a ramp generation circuit, and a comparator. The amplifier has a reference input, a power converter feedback input, and an amplifier output. The ramp generation circuit having a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal coupled to the amplifier output. The comparator has a current sense input, a ramp signal input, and a comparator output, in which the ramp signal input is coupled to the ramp signal terminal, and the comparator output is coupled to a power converter control terminal.
An apparatus comprises a power converter and a controller. The power converter has a power input, a power output, a current sense output, and a control input. The controller has a control output, a feedback voltage input, a reference voltage input, and a current sense input. The control output is coupled to the control input. The feedback voltage input is coupled to the power output. The current sense input is coupled to the current sense output. The controller includes an amplifier, a ramp generation circuit, and a comparator. The amplifier has an amplifier output and first and second amplifier inputs, the first amplifier input coupled to the reference voltage input, and the second amplifier input coupled to the feedback voltage input. The ramp generation circuit has a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal coupled to the amplifier output. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the current sense input, the second comparator input coupled to the ramp signal terminal, and the comparator output coupled to the control output.
In a method, a current sense signal representing a current through a switch of a power converter is received. An error signal indicating a load condition is generated. Responsive to the error signal indicating that a light load condition is satisfied: a ramp signal having a ramp rate based on the error signal is generated. A current target signal is generated based on subtracting the ramp signal from the error signal. The current target signal is compared with the current sense signal to generate a decision. And a switching signal is provided to the power converter responsive to the decision.
The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.
Inductor 104 can be in the charging state when power stage 102 is enabled, which includes switch 112a being turned on and switch 112b being turned off. When inductor 104 is in the charging state, inductor 104 can receive a current from power source 106, and the current increases from a non-negative minimum current Imin to a peak current Ipeak with respect to time as magnetic energy is stored in inductor 104. The rate of increase of the inductor current within the on-time can be based on a voltage across inductor 104, which can be based on the input voltage Vin.
Inductor 104 can be in a discharging state when power stage 102 is disabled, which includes switch 112a being turned off and switch 112b being turned on. When inductor 104 is in the discharging state, inductor 104 can release the stored magnetic energy and provides a current, which decreases from Ipeak back to Imin with respect to time. The rate of decrease of the inductor current within the off-time can be based on a voltage across inductor 104, which can be based on the output voltage Vout.
The duration of on-time within a switching cycle can affect the peak current and the amount of magnetic energy stored in inductor 104, which can also affect the energy provided by inductor 104 to load 110. For example, in
In some examples, SMPS 100 can be controlled by a controller that implements a feedback system to regulate the on-time and off-time of the switching cycles, such that the SMPS can provide a desired voltage and/or a desired current to the load. Specifically, the controller can receive measurements of the current conducted by inductor 104, and measurements of the voltage provided by SMPS 100. Based on comparing the current conducted by inductor 104 and a desired/target current value, the controller can adjust the on-time of the switching cycle, which can also adjust the duration of the charging state of inductor 104 within the switching cycle as well as the peak inductor current. Also, based on comparing the voltage provided by SMPS 100 and a reference voltage, the controller can adjust the on-time and/or the duty cycle of the switching cycle to regulate the output voltage of SMPS 100 at the reference voltage.
The controller can set the on-time and off-time of a switching cycle based on various techniques, including pulse width modulation (PWM) and pulse frequency modulation (PFM). With PWM, the switching cycle period as well as the switching frequency can be kept constant. Due to the constant switching frequency, PWM can provide a predictable operating frequency and low output ripple characteristics. SMPS 100 can also operate with high efficiency during heavy load conditions where the switching loss incurred by power stage 102 can be small compared with the amount of power transferred to load 110. The controller can adjust the on-time of the switching cycle to adjust the peak inductor current as well as the output voltage. The operation in
The controller can also set the on-time and off-time of a switching cycle based on PFM. With PFM, the controller can maintain the on-time at a constant, and adjust the switching frequency to adjust the power provided to the load. PFM can improve the efficiency of SMPS when operating in a low load condition or a standby condition. In such conditions, as the demand for current from the load is reduced to close to zero, the switching frequency can be reduced. The switching loss incurred by power stage 102 can be reduced compared with the power being transmitted by SMPS 100, which can improve the efficiency of the SMPS. Also, because the switching frequency is reduced, the average inductor current can be reduced to match the reduced current demand of the load.
Although operating SMPS 100 in the PFM mode can improve the efficiency of the power converter in light load condition, the variable switching frequency in the PFM mode can worsen the electromagnetic interference (EMI) between SMPS 100 and other electronic components. Specifically, because the switching frequency varies with the load current, to support a wide range of load current SMPS 100 may also have a wide switching frequency range in the PFM mode. Accordingly, SMPS 100 may have a fundamental switching frequency, or its harmonics, that is close to the operation frequency of other electronic components in supplying a particular load current, and may violate EMI requirements for those components. For example, various Automotive Electromagnetic Compatibility (EMC) Test Standards, such as Comité International Spécial des Perturbations Radioelectriques (CISPR), contains thresholds for radio disturbances across various frequency ranges. SMPS 100 operating in the PFM mode may emit an electromagnetic signal having a fundamental frequency (or harmonic frequencies) that falls within those frequency ranges, and having power that exceeds the threshold defined in the CISPR standards. Accordingly, SMPS 100 operating in the PFM mode under certain load conditions may fail the CISPR standards and may not be suitable for automotive applications.
In some examples, SMPS 100 may also operate in a forced PWM (FPWM) mode in light load condition. The switching frequency of SMPS 100 in the PWM mode can be selected to conform certain EMI requirements (e.g., CISPR).
In the FPWM operations of
Referring to
Within each ramp cycle period, the magnitude of the ramp signal can reduce with time. The magnitude of the ramp signal can define a peak inductor current target for a particular switching cycle. Both the initial value of the ramp signal at the beginning of a ramp cycle period, and the rate at which the ramp signal reduces with time (the ramp/slew rate), can depend on the load condition. For example, the initial peak inductor current target at the beginning of a ramp cycle period can be Ipeak_init0 in
Graphs 602, 702, and 802 of
The controller can adjust the slope (ramp rate) of the ramp signal to adjust the average output current supplied to load 110 and capacitor 108. The average output currents in
The slope of the ramp also sets the width of the ramp signal Tramp_width, which can represent the duration of time when the peak inductor current target is above Imin. The ramp signal width can set the number of switching cycles in a ramp period. Specifically, in some examples, the controller may disable the switching of power stage 102 if peak inductor current target is close to or below Imin, which can indicate that the output current to be supplied by SMPS 100 is below a minimum load condition. Therefore, with a ramp signal having a steeper slope and a narrower width, the number of switching cycles within a ramp cycle period may be reduced, which can further reduce the average current supplied by SMPS 100 to the load. For example, in
The example control techniques described in
Also, compared with the FPWM operations described in
Specifically, controller 902 can include amplifiers 912, 914, and 916, a ramp generation circuit 918, a comparator 920, and a switching signal generation circuit 922. Amplifier 912 has a first input (e.g., a negative input) coupled to voltage divider 904 to receive VFB 906. Amplifier 912 also has a second input (e.g., a positive input) to receive a reference voltage signal (VREF) 930, which can represent a target output voltage of SMPS 100. Amplifier 912 can generate an error signal 932 representing a voltage difference between VFB 906 and VREF 930. The magnitude (e.g., voltage) of error signal 932 can indicate the load condition. This is because if SMPS 100 is not providing sufficient current to load 110, capacitor 108 can discharge to supply additional current, which causes the output voltage (and VFB 906) to drop, and the voltage difference increases. Accordingly, an error signal 932 having a large magnitude (e.g., a large voltage) can indicate a larger target current to be supplied by SMPS 100, which can represent a heavy load condition. Also, an error signal 932 having a small magnitude (e.g., a small voltage) can indicate a smaller target current to be supplied by SMPS 100, which can represent a light load condition.
In some examples, controller 902 can include a clamp circuit 933 coupled to the output of amplifier 912 to set an upper limit and a lower limit of the magnitude of error signal 932. Clamp circuit 933 can include unity-gain voltage buffers. The upper limit of error signal 932 can represent a peak inductor current limit for SMPS 100 in a heavy load condition. Also, the lower limit of error signal 932 can represent a threshold for light load condition. Under the light load condition, the magnitude of error signal 932 can be at the lower limit, and controller 902 can modulate the peak inductor current by a combination of error signal 932 and ramp signal 908 as to be described below.
Amplifier 914 has a first input coupled to the output of amplifier 912 to receive error signal 932. Amplifier 914 also has a second input coupled to a ramp signal terminal of ramp generation circuit 918 to receive ramp signal 908. Amplifier 914, which can include a subtraction circuit, can generate a current target signal 934 by subtracting ramp signal 908 from error signal 932. As to be discussed below, during a non-light load condition, ramp generation circuit 918 can generate a flat/static ramp signal 908 (e.g., at 0 v or a ground voltage), and current target signal 934 can represent error signal 932. Also, during a light load condition, ramp generation circuit 918 can generate ramp signal 908 having a ramp rate/slew rate that reflects the load condition, and current target signal 934 can also include a ramp signal similar to those illustrated by graphs 600, 700, and 800 of
Comparator 920 can have a first input (e.g., a positive input) coupled to a current sense terminal of SMPS 100 and a second input (e.g., a negative input) coupled to the output of amplifier 914. Comparator 920 can receive a current sense signal 940 representing a measurement of the inductor current in SMPS 100 at the first input, and current target signal 934 at the second input, and generate a decision signal 942 representing a comparison between the inductor current and a peak inductor current target represented by current target signal 934. Comparator 920 can generate decision signal 942 having a first state (e.g., a logical zero) if the inductor current is below the peak inductor current target, and switch decision signal 942 to a second state (e.g., a logical one) if the inductor current equals the peak inductor current target. In some examples, if current target signal 934 is below a threshold (e.g., an input voltage range of comparator 920) representing a minimum load condition, comparator 920 can maintain decision signal 942 in the second state.
Switching signal generator 922, which can include a clocked sequential logic circuit such as a flip-flop, has a first signal input coupled to the output of comparator 920 to receive decision signal 942. Switching signal generator 922 also has a second signal input coupled to a voltage source 950, and a clock input to receive a first clock signal 952. Switching signal generator 922 also has a signal output coupled to a control terminal of power stage 102 (e.g., control terminals of switches 112a and 112b) to provide switching signal 114. In some examples, the first signal input can be coupled to the reset input (labelled R) of the flip flop, the second signal input can be coupled to the data input (labelled D) of the flip flop, and the signal output can be coupled to the data output (labelled Q) of the flip flop. Voltage source 950 can provide a voltage representing a logical one.
First clock signal 952 can define the switching frequency of switching signal 114. For example, in a case where the switching frequency is at 2.4 MHz, first clock signal 952 can have a frequency of 2.4 MHz. Each switching cycle starts with decision signal 942 (and the reset input) having a logical zero state. The on-time (Ton) of a switching cycle starts. Switching signal 114 can have a first state that enables power stage 102, and the inductor current increases with time as the inductor is in a charging state. As the inductor current increases and becomes equal to the peak current target, decision signal 942 (and the reset input) can switch to the logical one state. Responsive to the switching of decision signal 942, switching signal 114 can also switch to a second state that disables power stage 102, and the on-time of the switching cycle ends. The inductor current then reduces with time as the inductor discharges. Also, in a case where minimum load condition is reached, decision signal 942 (and the reset input) can stay in the logical one state, which keeps the flip-flop in the reset state and power stage 102 in the disabled state.
Also, in the light load condition, amplifier 916 and ramp generation circuit 918 can generate a ramp signal 908 having a ramp rate/slew rate that reflects the load condition. Specifically, amplifier 916 has a first input (e.g., a negative input) coupled to the output of amplifier 912 to receive error signal 932. Amplifier 916 has a second input (e.g., a positive input) to receive a current threshold (ITH) signal 960. Current threshold signal 960 can be a voltage signal representing the threshold for light load condition. Amplifier 916 can generate a slope signal 962 representing a difference between the error signal 932 and current threshold signal 960. In some examples, error signal 932 and current threshold signal 960 are voltage signals, and the difference is a voltage difference. If error signal 932 exceeds current threshold signal 960, amplifier 916 can generate slope signal 962 having a disabled/inactive state (e.g., having a voltage/current below a threshold). But if error signal 932 is below current threshold signal 960, which indicates that the load current to be supplied by SMPS 100 is below the threshold for the light load condition, amplifier 916 can generate slope signal 962 in an enabled/active state (e.g., having a voltage/current above the threshold), and the magnitude of slope signal 962 can represent a difference between error signal 932 and current threshold signal 960. The difference can represent the amount of current (e.g., average current) to be supplied by SMPS 100 to load 110 under the light load condition.
Ramp generation circuit 918 includes a slope control terminal, a ramp signal terminal, and a clock input. The slope control terminal of ramp generation circuit 918 is coupled to the output of amplifier 916, and the ramp signal terminal of ramp generation circuit 918 is coupled to the second input of amplifier 914. Ramp generation circuit 918 can receive slope signal 962 via the slope control terminal. Responsive to slope signal 962 having the disabled/inactive state, ramp generation circuit 918 can be disabled. Also, responsive to slope signal 962 having an enabled/active state, ramp generation circuit 918 can provide ramp signal 908 having the ramp/slew rate based on the magnitude of slope signal 962.
Ramp generation circuit 918 also has a clock input to receive a second clock signal 964 which defines the cycle period of ramp signal 908. For example, second clock signal 964 can have a frequency of at 400 kHz. In each ramp cycle period, ramp generation circuit 918 can provide ramp signal 908 having the ramp/slew rate based on slope signal 962.
In some examples, ramp generation circuit 918 can generate ramp signal 908 that increases with time in each ramp cycle period. Accordingly, current threshold signal 960, which is from the subtraction between error signal 932 and ramp signal 908, can ramp down and provide a reducing peak inductor current target similar to those represented by graphs 600, 700, and 800 of
Referring to graphs 1004 and 1006, within each ramp cycle period Tramp, ramp generation circuit 918 can provide ramp signal 908 that increases with time at a slew rate dV0/dt based on slope signal 962. With a rate of dV0/dt, ramp signal 908 can increase from an initial ramp voltage Vramp_init0 to a final ramp voltage Vramp final within a ramp cycle period. In some examples, the initial ramp voltage Vramp_init0 can be 0 v (or a ground voltage). The final ramp voltage Vramp final is lower than the voltage of error signal 932, which has a voltage Verror0 representing the same load condition represented by slope signal 962 (and slew rate dV0/dt).
Also, referring to graph 1002, amplifier 914 (or a subtraction circuit) can generate current target signal 934 by subtracting ramp signal 908 from error signal 932. Accordingly, the peak inductor current target represented current target signal 934 can be at the highest at the beginning of the ramp cycle period and has the value of Ipeak_init0. The peak inductor current target reduces with time within the ramp cycle period as ramp signal 908 increases. The peak inductor current target can have the value of Ipeak_final at the end of the ramp cycle period.
Referring to graphs 1104 and 1106, within each ramp cycle period Tramp, ramp generation circuit 918 can provide ramp signal 908 that increases with time at a slew rate dV1/dt based on slope signal 962. With a rate of dV1/dt, ramp signal 908 can increase from an initial ramp voltage Vramp_init (which can be 0 v) and reach the voltage of error signal 932, Verror1, before the ramp cycle period ends. The duration for ramp signal 908 to increase from Vramp_init to Verror1 can define the ramp width Tramp_width1 of current target signal 934. Ramp signal 908 can be at Verror1 for the remainder of the ramp cycle period, and then switch to Vramp_init at the beginning of the next ramp cycle. The voltage Verror1 represents the same load condition represented by slope signal 962 (and slew rate dV1/dt). As described above,
Also, referring to graph 1002, amplifier 914 (or a subtraction circuit) can generate current target signal 934 by subtracting ramp signal 908 from error signal 932. Accordingly, the peak inductor current target represented by current target signal 934 can be at the highest at the beginning of the ramp cycle period and has the value of Ipeak_init1. The peak inductor current target reduces with time within the ramp cycle period as ramp signal 908 increases. The peak inductor current target can reach the minimum current value Imin after a duration of Tramp_width1 has elapsed has elapsed from the start of the ramp cycle period, when ramp signal 908 has the same voltage as error signal 932 (Verror1). The peak inductor current target can remain at Imin for the remainder of the ramp cycle period.
Referring to graphs 1204 and 1206, within each ramp cycle period Tramp, ramp generation circuit 918 can provide ramp signal 908 that increases with time at a slew rate dV2/dt based on slope signal 962. With a rate of dV2/dt, ramp signal 908 can increase from an initial ramp voltage Vramp_init (which can be 0 v) and reach the voltage of error signal 932, Verror2, before the ramp cycle period ends. The duration for ramp signal 908 to increase from Vramp_init to Verror2 can define the ramp width Tramp_width2 of current target signal 934. Ramp signal 908 can stay at Verror2 for the remainder of the ramp cycle period, and then switch to Vramp_init at the beginning of the next ramp cycle. The voltage Verror2 represents the same load condition represented by slope signal 962 (and slew rate dV2/dt). As described above,
Also, referring to graph 1202, amplifier 914 (or a subtraction circuit) can generate current target signal 934 by subtracting ramp signal 908 from error signal 932. Accordingly, the peak inductor current target represented by current target signal 934 can be at the highest at the beginning of the ramp cycle period and has the value of Ipeak_init2. The peak inductor current target reduces with time within the ramp cycle period as ramp signal 908 increases with time. The peak inductor current target can reach the minimum current value Imin after a duration of Tramp_width2 has elapsed from the start of the ramp cycle period, when ramp signal 908 has the same voltage as error signal 932 (Verror2). The peak inductor current target can remain at Imin for the remainder of the ramp cycle period.
Specifically, at the beginning of each ramp cycle period, switch driver circuit 1306 can provide control signal 1310 having a first state for a short duration to turn on switch 1304, which shorts the top and bottom plates of capacitor 1302 to remove the stored charge, and the slope control terminal and the ramp signal terminal can have the Vramp_init voltage (e.g., 0 v) of the ground terminal. Switch driver circuit 1306 can then switch control signal 1310 to a second state for the remainder of the ramp cycle period to turn off switch 1304, and the slope control terminal and the ramp signal terminal can be disconnected from the ground terminal.
With switch 1304 turned off, amplifier 916 can provide slope signal 962 to charge the capacitor 1302. In some examples, amplifier 916 can include a transconductance amplifier and can provide slope signal 962 as a current signal, with the magnitude of the current signal representing a voltage difference between error signal 932 and current threshold signal 960. As described above, the voltage of error signal 932 increases with the amount of current to be supplied by SMPS 100. Accordingly, under a light load condition (e.g., as illustrated in
Also, under a very light load condition (e.g., as illustrated in
Specifically, ADC 1402 can sample slope signal 962 at the ramp signal frequency, and provide a digital signal 1412 of slope signal 962 to ramp controller 1404. Based on digital signal 1412, ramp controller 1404 can provide control signal 1414 to DAC 1406 to generate ramp signal 908. Ramp controller 1404 can determine whether the light load threshold is reached based on slope signal 962. If digital signal 1412 represents that light load threshold is not reached (e.g., digital signal 1412 representing a zero), ramp controller 1404 can provide control signal 1414 to DAC 1406 to provide a voltage signal at Vramp_init (which can be 0 v).
Also, if digital signal 1412 represents that light load threshold is reached (e.g., digital signal 1412 being non-zero), ramp controller 1404 can determine the voltage range and the slope of ramp signal 908 based on digital signal 1412. As described above, under a light load condition, the magnitude of slope signal 962 can be relatively large (due to increased difference between error signal 932 and current threshold signal 960), digital signal 1412 can represent a large digital value, and ramp controller 1404 can set a high slew rate for ramp signal 608. Also, under a very light load condition, the magnitude of slope signal 962 can be relatively small (due to reduced difference between error signal 932 and current threshold signal 960), digital signal 1412 can represent a small digital value, and ramp controller 1404 can set a low slew rate of ramp signal 608. Ramp controller 1404 can also determine an instantaneous voltage of ramp signal 908 at a switching cycle based on the slew rate and clamp the voltage to at error signal 932. Within each ramp signal cycle, ramp controller 1404 can provide control signal 1414 representing the instantaneous voltage, and update control signal 1414 at each switching cycle, so that DAC 1406 can provide ramp signal 608 that increases with time at a ramp/slew rate that represents the load condition, as illustrated in graphs 1006, 1106, and 1206 of
As shown in
In operation 1902, the controller can receive a current sense signal (e.g., current sense 940) representing an inductor current of a power converter. As described above, the inductor current increases during an on-time of a power stage of the power converter (e.g., power stage 102) when the inductor is in a charging state. The inductor current decreases during an off-time of the power stage when the inductor is in a discharging state.
In operation 1904, the controller can generate an error signal indicating a load condition. In some examples, the controller can receive a feedback voltage (e.g., VFB 906) from the power converter and a reference voltage signal (e.g., VREF 930), and generate an error signal (e.g., error signal 932) representing a difference between an output voltage of the power converter and a reference voltage. The error signal can also represent an amount of current to be supplied by the SMPS to the load, and can indicate the load condition. The reference voltage can represent a target output voltage of the power converter, and the magnitude of the error signal can indicate the load condition. As described above, if the SMPS is providing insufficient amount of current to the load, which indicates a heavy load condition, a capacitor at the load (e.g., capacitor 108) can discharge to supply additional current, which causes the output voltage to drop and increases the voltage difference. Accordingly, an error signal having a large magnitude (e.g., a large voltage) can indicate a larger target current to be supplied by the SMPS, which represents a heavy load condition. Also, an error signal having a small magnitude (e.g., a small voltage) can indicate a smaller target current to be supplied by SMPS, which represents a light load condition.
In operation 1906, the controller can determine whether a light load condition is satisfied based on the error signal. Specifically, the controller (e.g., amplifier 916) can generate slope signal 962 representing a difference between the error signal and a current threshold signal (e.g., current threshold signal 960). In some examples, both the error signal and the current threshold signal are voltage signals, and the difference can be a voltage difference. The current threshold signal represents a threshold for a light load condition. Referring to
If the light load condition is satisfied (e.g., error signal 932 is below current threshold signal 960), the controller can proceed to operation 1908 and generate a ramp signal (e.g., ramp signal 908) having a ramp rate based on the error signal. Specifically, the controller (e.g., ramp generation circuit 918) can also set the ramp rate of ramp signal 908 according to an inverse relationship with slope signal 962, which represents the load condition. For example, ramp generation circuit 918 can decrease the ramp rate of ramp signal 908 responsive to an increase in the magnitude of slope signal 962, which can reduce the rate of reduction of the peak inductor current across switching cycles within a ramp cycle period and increase the average output current. Also, ramp generation circuit 918 can increase the ramp rate of ramp signal 908 responsive to a decrease in the magnitude of slope signal 962, which can increase the rate of reduction of the peak inductor current across switching cycles within a ramp cycle period and decrease the average output current.
In some examples, the controller can include an amplifier (e.g., amplifier 916) having an output coupled to a capacitor (e.g., capacitor 1302), and the amplifier can charge the capacitor to generate the ramp signal that ramps up with time, such as shown in
In operation 1910, the controller can provide a current target signal based on the ramp signal and the error signal. For example, amplifier 914 can generate current target signal 934 by subtracting ramp signal 608 from error signal 932, so that current target signal 934 ramps down with time at the same ramp/slew rate as ramp signal 908.
In operation 1912, the controller can compare the current target signal with the current sense signal to generate a first decision. The first decision can indicate whether the inductor current is equal to (or above) a current target represented by current target signal 934/error signal 932.
In operation 1914, the controller can provide a first switching signal to the power converter responsive to the first decision. Specifically, the controller can set the first switching signal to a first state if the first decision indicates that the inductor current is below the current target. Also, the controller can set the first switching signal to a second state if the first decision indicates that the inductor current is equal to (or above) the current target. Power stage 102 can be turned on, and the inductor can be in the charging state, responsive to the first switching signal having the first state. Also, power stage 102 can be turned off, and the inductor can be in the discharging state, responsive to the first switching signal having the second state. Because of the target current reduces with time, the peak inductor current also reduces across the switching cycles and at a rate that reflects the load condition.
Referring back to operation 1906, if the light load condition is not satisfied (e.g., error signal 932 is above current threshold signal 960), the controller can proceed to operation 1918 and generate a flat/static current target signal based on the error signal, and compare the current sense signal with the flat current sense signal to generate a second decision, in operation 1920. Specifically, responsive to the slope signal being in the disabled state, ramp generation circuit 918 can generate a flat or zero ramp signal 908, and amplifier 914 can provide a flat current target signal 934 representing error signal 932. The second decision can indicate whether the inductor current is equal to (or above) a current target represented by current target signal 934/error signal 932.
In operation 1922, the controller can provide a second switching signal to the power converter responsive to the second decision. Specifically, the controller can set the second switching signal to a first state if the second decision indicates that the inductor current is below the current target. Also, the controller can set the second switching signal to a second state if the second decision indicates that the inductor current is equal to (or above) the current target. Power stage 102 can be turned on, and the inductor can be in the charging state, responsive to the second switching signal having the first state. Also, power stage 102 can be turned off, and the inductor can be in the discharging state, responsive to the second switching signal having the second state. Because of the flat current target, the peak inductor current can be constant across multiple switching cycles.
In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal provided by device A.
In this description, a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party.
While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or in parallel between identical two nodes as the single resistor or capacitor.
Uses of the phrase “ground voltage potential” in this description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.
Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.