Claims
- 1. A switching apparatus for sharing input/output endpoints, the switching apparatus comprising:
a first plurality of I/O ports, coupled to a plurality of operating system domains through a PCI Express fabric, each configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus; a second I/O port, coupled to a first shared input/output endpoint, wherein said first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of said plurality of operating system domains; and core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said PCI Express transactions between said first plurality of I/O ports and said second I/O port.
- 2. The switching apparatus as recited in claim 1, wherein said core logic maps said each of said plurality of operating system domains to a corresponding root complex.
- 3. The switching apparatus as recited in claim 1, wherein said first shared input/output endpoint is integrated into the switching apparatus.
- 4. The switching apparatus as recited in claim 1, wherein said first shared input/output endpoint is integrated into a root complex.
- 5. The switching apparatus as recited in claim 1, wherein said first shared input/output endpoint is integrated into a processing complex.
- 6. The switching apparatus as recited in claim 1, wherein said core logic isolates said PCI Express transactions over a plurality of PCI Express bus hierarchies according to said each of said plurality of operating system domains.
- 7. The switching apparatus as recited in claim 6, wherein a subset of said PCI Express transactions are routed in accordance with addressing mechanisms for a particular one of said plurality of PCI Express bus hierarchies, said particular one of said plurality of PCI Express bus hierarchies corresponding to a particular one of said plurality of operating system domains.
- 8. The switching apparatus as recited in claim 1, wherein said core logic is configured to associate each of said PCI Express transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.
- 9. The switching apparatus as recited in claim 8, wherein said core logic designates said corresponding one of said plurality of OSDs according to a variant of PCI Express protocol, wherein said PCI Express protocol provides for routing of said PCI Express transactions only for a single operating system domain.
- 10. The switching apparatus as recited in claim 9, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said PCI Express protocol.
- 11. The switching apparatus as recited in claim 10, wherein said transaction layer packet is routed between said second I/O port and said first shared input/output endpoint.
- 12. The switching apparatus as recited in claim 11, wherein said first shared I/O endpoint is configured to detect said OS domain header and to perform a specified operation according to said PCI Express protocol exclusively for said one of said plurality of OSDs.
- 13. The switching apparatus as recited in claim 1, wherein said first shared input/output endpoint designates one of said PCI Express transactions for a particular one of said plurality of operating system domains by encapsulating an OS domain header within a transaction layer packet, and wherein said transaction layer packet is routed to said core logic via said second I/O port.
- 14. The switching apparatus as recited in claim 13, wherein said core logic is configured to detect and decapsulate said OS domain header from said transaction layer packet, and is configured to route said one of said PCI Express transactions to said particular one of said plurality of operating system domains.
- 15. The switching apparatus as recited in claim 1, wherein said core logic is integrated within a shared I/O switch.
- 16. The switching apparatus as recited in claim 1, wherein said core logic is integrated within a root complex.
- 17. The switching apparatus as recited in claim 1, wherein said core logic is integrated within a processing complex.
- 18. A shared input/output (I/O) switching mechanism, comprising:
core logic, configured to enable operating system domains to share one or more I/O endpoints over a PCI Express fabric, said core logic comprising:
global routing logic, configured to route PCI Express transactions to/from said operating system domains, and for routing PCI Express+ transactions to/from said one or more I/O endpoints, wherein each of said PCI Express+ transactions designates an associated one of said operating system domains for which an operation specified by each of said PCI Express transactions be performed.
- 19. The shared I/O switching mechanism as recited in claim 18, wherein said core logic isolates said PCI Express transactions over a plurality of PCI Express bus hierarchies according to each of said operating system domains.
- 20. The shared I/O switching mechanism as recited in claim 19, wherein said PCI Express transactions are routed in accordance with addressing mechanisms for a particular one of said plurality of PCI Express bus hierarchies, said particular one of said plurality of PCI Express bus hierarchies corresponding to said associated one of said operating system domains.
- 21. The shared I/O switching mechanism as recited in claim 18, wherein said core logic associates each of said operating system domains with each of a corresponding root complex.
- 22. The shared I/O switching mechanism as recited in claim 18, wherein said PCI Express+ transactions comport with a variant of the PCI Express protocol, said PCI Express protocol providing exclusively for a single operating system domain within said PCI Express fabric.
- 23. The shared I/O switching mechanism as recited in claim 22, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet of said each of said PCI Express transactions, wherein said each of said PCI Express transactions otherwise comports with the PCI Express protocol.
- 24. The shared I/O switching mechanism as recited in claim 23, wherein said transaction layer packet is routed between said the shared I/O switching mechanism and one of said one or more I/O endpoints.
- 25. The shared I/O switching mechanism as recited in claim 24, wherein said one of said one or more I/O endpoints is configured to detect said OS domain header and to perform said operation according to the PCI Express protocol exclusively for said one of said operating system domains.
- 26. The shared I/O switching mechanism as recited in claim 18, wherein one of said one or more I/O endpoints designates one of said PCI Express+transactions for a particular one of said operating system domains by encapsulating an OS domain header within a transaction layer packet, and wherein said transaction layer packet is routed to the shared I/O switching mechanism.
- 27. The shared I/O switching mechanism as recited in claim 26, wherein VMAC logic within the shared I/O switching mechanism is configured to detect and decapsulate said OS domain header from said transaction layer packet, and wherein said core logic routes a corresponding one of said PCI Express transactions to said particular one of said plurality of operating system domains according to the PCI Express protocol, said PCI Express protocol providing exclusively for a single operating system domain within said PCI Express fabric.
- 28. A method for interconnecting independent operating system domains to a shared I/O endpoint within a PCI Express fabric, comprising:
via first ports, first communicating with each of the independent operating system domains according to the PCI Express protocol, which provides exclusively for a single operating system domain within the PCI Express fabric; via a second port, second communicating with the shared I/O endpoint according to a variant of the PCI Express protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains; and via core logic within a switching apparatus, mapping the independent operating system domains to the shared I/O endpoint.
- 29. The method as recited in claim 28, further comprising:
over the PCI Express fabric, first interconnecting the independent operating system domains to the switching apparatus via the first ports; and over the PCI Express fabric, second interconnecting the shared I/O endpoint to the switching apparatus via the second port.
- 30. The method as recited in claim 28, wherein said first communicating comprises:
associating each of the independent operating system domains with a corresponding root complex.
- 31. The method as recited in claim 28, wherein said mapping comprises:
isolating transactions over a plurality of PCI Express bus hierarchies according to each of the operating system domains.
- 32. The method as recited in claim 31, wherein said mapping further comprises:
routing the transactions in accordance with addressing mechanisms for a particular one of the plurality of PCI Express bus hierarchies, the particular one of said plurality of PCI Express bus hierarchies corresponding to the corresponding one of the operating system domains.
- 33. The method as recited in claim 28, wherein said second communicating comprises:
employing the variant of the PCI Express protocol to associate a unique root complex that with the corresponding one of the operating system domains.
- 34. The method as recited in claim 33, wherein said employing comprises:
encapsulating an OS domain header within a transaction layer packet that otherwise comports with the PCI Express protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains.
- 35. The method as recited in claim 34, wherein said second communicating further comprises:
routing the transaction layer packet between the second port and the shared I/O endpoint.
- 36. The method as recited in claim 35, wherein said second communicating further comprises:
within the I/O endpoint, detecting the OS domain header; and performing the prescribed operation according to the PCI Express protocol, wherein said performing is accomplished exclusively for the corresponding one of the operating system domains.
- 37. The method as recited in claim 28, wherein said second communicating comprises:
within the shared I/O endpoint, designating a transaction for a particular one of the operating system domains by embedding an OS domain header within a transaction layer packet; and first transmitting the transaction layer packet to the second port.
- 38. The method as recited in claim 37, wherein said second communicating comprises:
within the switching apparatus, detecting and removing the OS domain header from the transaction layer packet.
- 39. The method as recited in claim 38, wherein said first communicating comprises:
second transmitting the transaction layer packet to the particular one of the operating system domains according to the PCI Express protocol.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of the following U.S. Provisional Application, which is herein incorporated by reference for all intents and purposes.
1FILINGSERIAL NUMBERDATETITLE60/555127Mar. 22, 2004PCI EXPRESS SHARED IO(NEXTIO.0108)WIRELINE PROTOCOLSPECIFICATION
[0002] This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 10/802,532 STORE ARCHITECTURE, filed on Mar. 16, 2004, having a common assignee and common inventors, and which claims the benefit of the following U.S. Provisional Applications:
2SERIAL NUMBERFILING DATETITLE60/464382Apr. 18, 2003SHARED-IO PCI COMPLIANT(NEXTIO.0103)SWITCH60/491314Jul. 30, 2003SHARED NIC BLOCK(NEXTIO.0104)DIAGRAM60/515558Oct. 29, 2003NEXIS(NEXTIO.0105)60/523522Nov. 19, 2003SWITCH FOR SHARED I/O(NEXTIO.0106)FABRIC60/541673Feb. 4, 2004PCI SHARED I/O WIRE LINE(NEXTIO.0107)PROTOCOL
[0003] Co-pending U.S. patent application Ser. No. 10/802,532 (Docket: NEXTIO.0200), is a continuation-in-part of the following co-pending U.S. patent applications all of which have a common assignee and common inventors:
3SERIAL NUMBERFILING DATETITLE10/757713Jan. 14, 2004METHOD AND APPARATUS(NEXTIO.0301)FOR SHARED I/O IN ALOAD/STORE FABRIC10/757711Jan. 14, 2004METHOD AND APPARATUS(NEXTIO.0302)FOR SHARED I/O IN ALOAD/STORE FABRIC10/757714Jan. 14, 2004METHOD AND APPARATUS(NEXTIO.0300FOR SHARED I/O IN ALOAD/STORE FABRIC
[0004] The three aforementioned co-pending U.S. patent applications (i.e., Ser. Nos. 10/757,713, 10/757,711, and 10/757,714) claim the benefit of the following U.S. Provisional Applications:
4SERIAL NUMBERFILING DATETITLE60/440788Jan. 15, 2003SHARED IO ARCHITECTURE(NEXTIO.0101)60/440789Jan. 21, 20033GIO-XAUI COMBINED(NEXTIO.0102)SWITCH60/464382Apr. 18, 2003SHARED-IO PCI COMPLIANT(NEXTIO.0103)SWITCH60/491314Jul. 30, 2003SHARED NIC BLOCK(NEXTIO.0104)DIAGRAM60/515558Oct. 29, 2003NEXIS(NEXTIO.0105)60/523522Nov. 19, 2003SWITCH FOR SHARED I/O(NEXTIO.0106)FABRIC60/541673Feb. 4, 2004PCI SHARED I/O WIRE LINE(NEXTIO.0107)PROTOCOL
[0005] This application is related to the following co-pending U.S. patent applications, which have a common assignee and common inventors.
5SERIAL NUMBERFILING DATETITLE Apr. 19, 2004SWITCHING APPARATUS AND(NEXTIO.0400)METHOD FOR PROVIDINGSHARED IO WITHIN ALOAD-STORE FABRIC Apr. 19, 2004SWITCHING APPARATUS AND(NEXTIO.0402)METHOD FOR PROVIDINGSHARED IO WITHIN ALOAD-STORE FABRIC
Provisional Applications (16)
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Number |
Date |
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60464382 |
Apr 2003 |
US |
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60491314 |
Jul 2003 |
US |
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60515558 |
Oct 2003 |
US |
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60523522 |
Nov 2003 |
US |
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60541673 |
Feb 2004 |
US |
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60464382 |
Apr 2003 |
US |
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60491314 |
Jul 2003 |
US |
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60515558 |
Oct 2003 |
US |
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60523522 |
Nov 2003 |
US |
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60541673 |
Feb 2004 |
US |
|
60440788 |
Jan 2003 |
US |
|
60440789 |
Jan 2003 |
US |
|
60464382 |
Apr 2003 |
US |
|
60491314 |
Jul 2003 |
US |
|
60515558 |
Oct 2003 |
US |
|
60523522 |
Nov 2003 |
US |
Continuation in Parts (4)
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Number |
Date |
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Parent |
10802532 |
Mar 2004 |
US |
Child |
10827620 |
Apr 2004 |
US |
Parent |
10757713 |
Jan 2004 |
US |
Child |
10827620 |
Apr 2004 |
US |
Parent |
10757711 |
Jan 2004 |
US |
Child |
10827620 |
Apr 2004 |
US |
Parent |
10757714 |
Jan 2004 |
US |
Child |
10827620 |
Apr 2004 |
US |