1. Field of the Invention
The present invention relates to a switching circuit for use in an analog circuit, a sample and hold circuit having the switching circuit, and a solid-state imaging device.
2. Description of Related Art
As an example of a sample and hold circuit for sampling and holding an analog signal, a sample and hold circuit shown in
The sample and hold circuit shown in
A control signal ΦSH is input to the switching circuit 903. When the control signal ΦSH is in a High state (logical value “1”), the switching circuit 903 is in an ON state (conductive state) in which an electric current is applied to an input and an output. In addition, when the control signal ΦSH is in a Low state (logical value “0”), the switching circuit 903 is in an OFF state (non-conductive state) in which no electric current is applied to an input and an output (the input and output are disconnected).
Next, an operation of the sample and hold circuit shown in
The analog signal Vin input from the input terminal 901 is input to the switching circuit 903. When the sample and hold circuit samples the input analog signal Vin, the control signal ΦPSH is in the High state, so that the switching circuit 903 is in the ON state. At this time, the sample and hold circuit charges the capacitor Csh through the analog signal Vin (timing t1 of
Deviation (crosstalk) is likely to occur in the analog signal Vout held by the capacitor Csh resulting from a voltage of the analog signal Vout held by the capacitor Csh and a voltage of the analog signal Vin input to the switching circuit 903 while the capacitor Csh holds the analog signal Vout. This is because capacitance (parasitic capacitance) formed between the input and output of the switching circuit 903 has an influence even when the control signal ΦSH is in the Low state in the switching circuit 903 formed in the semiconductor substrate.
Hereinafter, the case in which the deviation occurs in the analog signal Vout held by the capacitor Csh will be described.
A P-type single crystal silicon substrate (P-type Si substrate 34 of
In the switching circuit 903 of the above-described configuration, parasitic capacitance Cp is formed between the drain wiring 31 and the source wiring 32 (between the input and output of the switching circuit 903).
In the sample and hold circuit shown in
The above-described voltage deviation ΔV may be problematic for output characteristics of an analog circuit. As one specific example, a solid-state imaging device mounted on a distal end of an endoscope is considered. It is necessary to reduce the size of the solid-state imaging device to mount the solid-state imaging device on the distal end of a narrow endoscope. Thus, it is difficult to sufficiently increase the value of the capacitor Csh due to constraints on a circuit area.
As an example of specific numeric values, assuming that C1=1 pF, C2=1 fF, Vo=2 V, and Vi=1 V in Formula (1), an error of ΔV≈−1 mV occurs. When the resolution of the AD conversion circuit provided in a subsequent stage of the sample and hold circuit is designated as 12 bits and the input voltage range of the AD conversion circuit is designated as 1 V, an error of 1 mV at the input voltage is likely to be an error of about 4 least significant bits (LSBs) in data after analog-to-digital (AD) conversion.
According to a first aspect of the present invention, a switching circuit includes: a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate electrode disposed to be opposite to the channel region; a source wiring formed of a first material having higher conductivity than the semiconductor layer and connected to the source region; a drain wiring formed of a second material having higher conductivity than the semiconductor layer and connected to the drain region; and a decoupling wiring formed of a third material having higher conductivity than the semiconductor layer and disposed between the source wiring and the drain wiring, wherein the source region and the drain region are in a conductive state in a first period according to a voltage of the gate electrode, and the source region and the drain region are in a non-conductive state in a second period different from the first period, and wherein a voltage of the decoupling wiring is constant in at least a partial period of the second period.
According to a second aspect of the present invention, in the switching circuit according to the first aspect, a voltage of the source wiring or the drain wiring may change in the second period.
According to a third aspect of the present invention, in the switching circuit according to the first aspect, the first material, the second material, and the third material may be the same material.
According to a fourth aspect of the present invention, in the switching circuit according to the second aspect, the decoupling wiring may be connected to the gate electrode and supply a gate voltage to the gate electrode.
According to a fifth aspect of the present invention, in the switching circuit according to the first aspect, the decoupling wiring may be disposed not to overlap the gate electrode when the semiconductor layer is viewed in a direction perpendicular to a main surface of a semiconductor substrate including the semiconductor layer.
According to a sixth aspect of the present invention, in the switching circuit according to the third aspect, the decoupling wiring may be disposed not to overlap the gate electrode when the semiconductor layer is viewed in a direction perpendicular to a main surface of a semiconductor substrate including the semiconductor layer.
According to a seventh aspect of the present invention, a sample and hold circuit includes: the switching circuit according to the first aspect; an input terminal; an output terminal; and a capacitor, wherein one of the source wiring and the drain wiring is connected to the input terminal, wherein the other of the source wiring and the drain wiring is connected to the output terminal, and wherein the capacitor is connected between the output terminal and a point having a predetermined constant voltage.
According to an eighth aspect of the present invention, in the sample and hold circuit according to the seventh aspect, second parasitic capacitance formed between the other of the source wiring and the drain wiring connected to the output terminal and the decoupling wiring may be less than first parasitic capacitance formed between the one of the source wiring and the drain wiring connected to the input terminal and the decoupling wiring.
According to a ninth aspect of the present invention, a solid-state imaging device includes: an imaging unit in which a plurality of pixels, each of which outputs a pixel signal according to an amount of incident light, are disposed in a matrix shape; and the sample and hold circuit according to the seventh aspect configured to sample and hold an analog signal resulting from the pixel signal.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment of the present invention will be described.
A P-type Si substrate 34 is used in a semiconductor substrate serving as a base of the switching circuit 100. The switching circuit 100 is formed in an NMOS transistor. The P-type Si substrate 34 is a semiconductor layer including a source region S, a drain region D, and a channel region CH disposed between the source region S and the drain region D. The source region S and the drain region D are regions having different impurity concentrations from the P-type Si substrate 34. The source region S is exposed on the surface of the P-type Si substrate 34 and connected to the source contact CAS. The drain region D is exposed on the surface of the P-type Si substrate 34 and connected to the drain contact CAD. The channel region CH is disposed in the vicinity of the surface of the P-type Si substrate 34. During the operation of the switching circuit 100, a channel serving as a path of an electric current is formed in the channel region CH.
The gate electrode GA constituted of polysilicon is formed on the P-type Si substrate 34. The gate electrode GA is disposed to be opposite to the channel region CH. In addition, the gate electrode GA is connected to the gate wiring 33 formed in a first metal layer via the gate contact CAG. The drain region D is connected to the drain wiring 31 formed in the first metal layer via the drain contact CAD. The source region S is connected to the source wiring 32 formed in the first metal layer via the source contact CAS.
The gate wiring 33 is disposed not to overlap the channel region CH when the switching circuit 100 is two-dimensionally viewed in a direction perpendicular to a main surface of the P-type Si substrate 34 (the main surface of the semiconductor substrate is viewed from above) in the example shown in
In an upper portion of the P-type Si substrate 34, a position at which the gate electrode GA, each contact, and each wiring are not formed is an insulation layer INS formed of an insulation material. That is, the insulation layer INS is disposed to internally include the source region S, the drain region D, and the gate electrode GA. The source wiring 32 is formed of a first material having higher conductivity than the P-type Si substrate 34 which is a semiconductor layer and connected to the source region S. The drain wiring 31 is formed of a second material having higher conductivity than the P-type Si substrate 34 which is the semiconductor layer and connected to the drain region D.
In
In addition, the switching circuit 100 has the decoupling wiring 101 in the first metal layer in which the drain wiring 31, the source wiring 32, and the gate wiring 33 are formed. That is, the drain wiring 31, the source wiring 32, the gate wiring 33, and the decoupling wiring 101 are formed in the same layer. The decoupling wiring 101 is formed of a third material having higher conductivity than the P-type Si substrate 34 which is the semiconductor layer and disposed between the source wiring 32 and the drain wiring 31. Therefore, the decoupling wiring 101 is opposite to the source wiring 32 and is opposite to the drain wiring 31.
The decoupling wiring 101 is disposed on the drain region D and connected to the ground GND. In addition, the decoupling wiring 101 is disposed not to overlap the gate electrode GA when the P-type Si substrate 34 which is the semiconductor layer is two-dimensionally viewed in a direction perpendicular to the main surface of the P-type Si substrate 34 (the main surface of the semiconductor substrate is viewed from above).
The first material constituting the source wiring 32, the second material constituting the drain wiring 31, and the third material constituting the decoupling wiring 101 are the same material (for example, a metal) in the example of this embodiment. One or more of these materials may be a different material. That is, the first material may be the same as only one of the second and third materials, may be the same as both the second and third materials, or may be different from both of the second and third materials. The same is also true for the second material and the third material.
In the switching circuit 100, first parasitic capacitance Cdg is formed between the drain wiring 31 and the ground GND through the drain wiring 31 and the decoupling wiring 101 connected to the ground GND. Likewise, in the switching circuit 100, second parasitic capacitance Csg is formed between the source wiring 32 and the ground GND through the source wiring 32 and the decoupling wiring 101 connected to the ground GND.
Next, an operation of this embodiment will be described.
First, the control signal ΦSH changes from the Low state (logical value “0”) to the High state (logical value “1”), so that the switching circuit 100 is in the ON state in which the electric current is applied to the drain region D (input) and the source region S (output) (timing t1 of
After the first period has elapsed, the control signal ΦSH changes from the High state (logical value “1”) to the Low state (logical value “0”), so that the switching circuit 100 is in the OFF state in which no electric current is applied to the drain region D (input) and the source region S (output) (the drain region D (input) and the source region S (output) are disconnected) (timing t2 of
When the switching circuit 100 is in the OFF state in the example shown in
After the second period has elapsed, the control signal ΦSH changes from the Low state (logical value “0”) to the High state (logical value “1”), so that the switching circuit 100 is in the ON state in which the electric current is applied to the drain region D (input) and the source region S (output) (timing t4 of
That is, in the example shown in
Because the decoupling wiring 101 is disposed between the drain wiring 31 and the source wiring 32 according to the configuration shown in
Although the voltage connected to the decoupling wiring 101 is the ground GND in this embodiment, the present invention is not limited thereto. For example, the voltage connected to the decoupling wiring 101 may be a power supply voltage or a predetermined constant voltage other than the ground GND or the power supply voltage. In addition, if a change time (frequency) of the voltage of the decoupling wiring 101 is sufficiently long (delayed) as compared with the second period, the voltage connected to the decoupling wiring 101 may not be a constant voltage.
In addition, although the decoupling wiring 101 is disposed on the drain region D in this embodiment, the present invention is not limited thereto. For example, the decoupling wiring 101 may be disposed on the source region S or the gate electrode GA.
In addition, although the switching circuit 100 is an NMOS transistor in this embodiment, the present invention is not limited thereto. For example, the switching circuit 100 may be constituted of a P-channel metal-oxide semiconductor (PMOS) transistor or a combination of the NMOS transistor and the PMOS transistor. When the switching circuit 100 is constituted of the PMOS transistor, the operation (state) of the switching circuit 100 for the control signal ΦSH is opposite to the operation (state) of the case in which the switching circuit 100 is constituted of the NMOS transistor, but the same effect is obtained. For example, according to the voltage of the gate voltage, the source region and the drain region are in the ON state (conductive state) in the first period and the source region and the drain region are in the OFF state (non-conductive state) in the second period different from the first period. In addition, the voltage of the source wiring changes in the second period and the voltage of the decoupling wiring 101 is constant in the second period.
In addition, although the switching circuit 100 is configured to have the drain region D as the input and the source region S as the output in this embodiment, the present invention is not limited thereto. For example, the switching circuit 100 may be configured to have the source region S as the input and the drain region D as the output.
In addition, although the metal layer constituting the wiring of the switching circuit 100 is only the first metal layer in this embodiment, the present invention is not limited thereto. In the semiconductor manufacturing process, a plurality of metal layers are generally provided. When the drain wiring and the source wiring are also formed in a second metal layer one layer above the first metal layer or a higher metal layer, it is only necessary to form the decoupling wiring in the same metal layer as the drain wiring and the source wiring.
Next, the second embodiment of the present invention will be described.
The configuration shown in
Next, the operation of this embodiment will be described. The operation of this embodiment is the same as the operation shown in
Because the gate wiring 33 also functions as the decoupling wiring according to the configuration shown in
In addition, although the switching circuit 200 is an NMOS transistor in this embodiment, the present invention is not limited thereto. For example, the switching circuit 200 may be constituted of a PMOS transistor or a combination of the NMOS transistor and the PMOS transistor. When the switching circuit 200 is constituted of the PMOS transistor, the operation (state) of the switching circuit 200 for the control signal ΦSH is opposite to the operation (state) of the case in which the switching circuit 200 is constituted of the NMOS transistor, but the same effect is obtained. For example, according to the voltage of the gate voltage, the source region and the drain region are in the ON state (conductive state) in the first period and the source region and the drain region are in the OFF state (non-conductive state) in the second period different from the first period. In addition, the voltage of the source wiring changes in the second period and the voltage of the decoupling wiring 101 is constant in the second period.
In addition, although the switching circuit 200 is configured to have a drain region D as an input and a source region S as an output in this embodiment, the present invention is not limited thereto. For example, the switching circuit 200 may be configured to have the source region S as the input and the drain region D as the output.
In addition, although a metal layer constituting the wiring of the switching circuit 200 is only a first metal layer in this embodiment, the present invention is not limited thereto. In a semiconductor manufacturing process, a plurality of metal layers are generally provided. When the drain wiring and the source wiring are also formed in a second metal layer one layer above the first metal layer or a higher metal layer, it is only necessary to form the decoupling wiring in the same metal layer as the drain wiring and the source wiring.
Next, the third embodiment of the present invention will be described.
In the configuration shown in
Because an operation of this embodiment is the same as those of the above-described first and second embodiments, a description thereof will be omitted.
Because a transistor characteristic (threshold voltage) is different from the case in which no wiring is disposed on a channel in a semiconductor manufacturing process when the wiring is disposed on the channel, a characteristic at the time of design may not be secured. However, because no wiring is disposed on the channel according to the configuration shown in
Although the gate wiring 33 is disposed on the drain region D in this embodiment, the present invention is not limited thereto. For example, the gate wiring 33 may be disposed on the source region S.
In addition, although the switching circuit 300 is an NMOS transistor in this embodiment, the present invention is not limited thereto. For example, the switching circuit 300) may be constituted of a PMOS transistor or a combination of the NMOS transistor and the PMOS transistor. When the switching circuit 300 is constituted of the PMOS transistor, the operation (state) of the switching circuit 300 for the control signal φSH is opposite to the operation (state) of the case in which the switching circuit 300 is constituted of the NMOS transistor, but the same effect is obtained. For example, according to the voltage of the gate voltage, the source region and the drain region is in the ON state (conductive state) in the first period and the source region and the drain region are in the OFF state (non-conductive state) in the second period different from the first period. In addition, the voltage of the source wiring changes in the second period and the voltage of the decoupling wiring 101 is constant in the second period.
In addition, although the switching circuit 300 is configured to have the drain region D as an input and a source region S as an output in this embodiment, the present invention is not limited thereto. For example, the switching circuit 200 may be configured to have the source region S as the input and the drain region D as the output.
In addition, although a metal layer constituting the wiring of the switching circuit 300 is only a first metal layer, the present invention is not limited thereto. In the semiconductor manufacturing process, a plurality of metal layers are generally provided. When the drain wiring and the source wiring are also formed in a second metal layer one layer above the first metal layer or a higher metal layer, it is only necessary to form the decoupling wiring in the same metal layer as the drain wiring and the source wiring.
Next, the fourth embodiment of the present invention will be described.
The sample and hold circuit 400 shown in
The switching circuit 403 is constituted of the switching circuit according to any one of the above-described first to third embodiments. Accordingly, the sample and hold circuit 400 of this embodiment has the switching circuit 403, the input terminal 401, the output terminal 402, and the capacitor Csh. One of the source wiring and the drain wiring (the drain wiring in the example shown in
Because the decoupling wiring is disposed between the drain wiring and the source wiring in the switching circuit 403, parasitic capacitance is unlikely to be formed between the drain wiring and the source wiring. A control signal ΦSH is input to the switching circuit 403. When the control signal ΦSH is in a High state (logical value “I”), the switching circuit 403 is in an ON state (conductive state) in which an electric current is applied to an input and an output. In addition, when the control signal QSl is in a Low state (logical value “0”), the switching circuit 403 is in an OFF state (non-conductive state) in which no electric current is applied to an input and an output (the input and output are disconnected).
In the example shown in
Because the drain wiring is opposite to the decoupling wiring connected to the gate electrode in the switching circuit 403 when the switching circuit 403 is constituted of the switching circuit 200 according to the second embodiment or the switching circuit 300 according to the third embodiment, the first parasitic capacitance Cdg is formed between the drain wiring and the gate voltage. Likewise, because the source wiring is opposite to the decoupling wiring connected to the gate voltage in the switching circuit 403, second parasitic capacitance Csg is formed between the source wiring and the gate voltage.
Because an operation of this embodiment is the same as those of the above-described first to third embodiments, a description thereof will be omitted.
As described above, according to the configuration shown in
When the gate wiring (decoupling wiring) of the switching circuit 403 is not disposed on the gate electrode (the case of the third embodiment) in this embodiment, the gate wiring (decoupling wiring) is disposed on an input side (on the drain region D in
The gate wiring (decoupling wiring) is disposed on the input side as described above, so that the second parasitic capacitance Csg formed between the other wiring of the source wiring and the drain wiring connected to the output terminal 402 and the decoupling wiring is less than the first parasitic capacitance Cdg formed between one of the source wiring and the drain wiring connected to the input terminal 401 and the decoupling wiring.
Disposing the gale wiring (decoupling wiring) on the input side is an example of a method of setting the second parasitic capacitance Csg less than the first parasitic capacitance Cdg. For example, it is possible to set the second parasitic capacitance Csg less than the first parasitic capacitance Cdg by setting the distance between mutually opposite sides of the gate wiring (decoupling wiring) and the wiring (drain wiring) of the input side less than the distance between mutually opposite sides of the gate wiring (decoupling wiring) and the wiring (source wiring) of the output side. Alternatively, when the distance between the gate wiring (decoupling wiring) and the wiring (drain wiring) of the input side is substantially the same as the distance between the gate wiring (decoupling wiring) and the wiring (source wiring) of the output side, a length of a side of the wiring (drain wiring) of the input side opposite to the gate wiring (decoupling wiring) is configured to be longer than a length of a side of the wiring (source wiring) of the output side opposite to the gate wiring (decoupling wiring), the second parasitic capacitance Csg can be configured to be less than the first parasitic capacitance Cdg.
In addition, although the capacitor Csh is connected to the output terminal 402 and the ground GND in this embodiment, the present invention is not limited thereto. For example, the capacitor Csh may be connected between the output terminal 402 and the power supply voltage or the capacitor Csh may be connected between the output terminal 402 and a point having a predetermined constant voltage other than the ground GND or the power supply voltage.
In addition, although the switching circuit 403 is configured to have the drain region D as an input and the source region S as an output in this embodiment, the present invention is not limited thereto. For example, the switching circuit 403 may be configured to have the source region S as the input and the drain region D as the output.
Next, the fifth embodiment of the present invention will be described.
In the imaging unit 501, a plurality of pixels (unit pixels 502), each of which generates and outputs a pixel signal according to an amount of incident light, are disposed. The vertical selection unit 509 selects each row of the imaging unit 501. The read current source unit 504 reads the pixel signal from the imaging unit 501 as a voltage signal. The analog unit 505 processes the pixel signal read from the imaging unit 501 and outputs the processed pixel signal. In addition, the analog unit 505 has an auto gain control (AGC) circuit having a signal amplification function and so on, if necessary. The horizontal selection unit 510 transfers the output signal of the analog unit 505 to the sample and hold unit 506 connected to a horizontal signal line 512. The sample and hold unit 506 holds an input signal and outputs the held signal to the output unit 507. The control unit 511 controls each part.
Although the imaging unit 501 including unit pixels 502 of 4 rows×6 columns has been described with reference to
Hereinafter, each part will be described in further detail. The imaging unit 501 includes the unit pixels 502 two-dimensionally disposed in only 4 rows×6 columns. In addition, each row control line 508 is wired for every row in the pixel array of 4 rows×6 columns. One end of each row control line 508 is connected to an output terminal of a corresponding row of the vertical selection unit 509. The vertical selection unit 509 includes a shift register, a decoder, or the like, and controls row addressing and row scanning of the imaging unit 501 through the row control lines 508 when each unit pixel 502 of the imaging unit 501 is driven. In addition, a vertical signal line 503 is wired to each column in the pixel array of the imaging unit 501.
The read current source unit 504 is constituted of a current source for reading the pixel signal from the imaging unit 501 as a voltage signal. The analog unit 505 is constituted of a correlated double sample (CDS) circuit or the like, and processes the read pixel signal from the imaging unit 501 to output the processed pixel signal.
The horizontal selection unit 510 includes a shift register, a decoder, or the like, and controls the column scanning of the analog unit 505. According to the control of the horizontal selection unit 510, the pixel signal processed by the analog unit 505 is sequentially read to the horizontal signal line 512 and transferred to the sample and hold unit 506.
The sample and hold unit 506 is constituted of a sample and hold circuit according to the above-described fourth embodiment, periodically samples and holds an analog signal according to the pixel signal input from the horizontal signal line 512, and outputs the sampled and held analog signal to the output unit 507.
The output unit 507 has a buffering function of outputting the input signal, and outputs a signal to an AD conversion circuit provided in a subsequent stage, although this is not shown. In addition, the output unit 507, for example, may incorporate a signal processing function such as AD conversion circuit or black level adjustment, column variation correction, and color processing in addition to the buffering function.
The control unit 511 includes a functional block of a timing generator (TG), which supplies a clock or a pulse signal of a predetermined timing necessary for an operation of each part such as the vertical selection unit 509, the horizontal selection unit 510, or the sample and hold unit 506, and a functional block for communicating with the TG.
Next, an operation of this embodiment will be described. Although a description of a specific operation of the unit pixel 502 is omitted, a reset level and a signal level are output in the unit pixel 502 as is well known. A reset level including noise of a pixel signal is read in a first read operation as an analog pixel signal from each unit pixel 502 of a selected row of the imaging unit 501, and then a signal level is read in a second read operation. The reset level and the signal level are input to the analog unit 505 through the vertical signal line 503 in time series. The signal level may be read in the first read operation and then the reset level may be read in the second read operation.
The analog unit 505 performs CDS processing on the reset level and the signal level, so that a pixel signal obtained by removing noise from the signal level is generated. Thereafter, the generated pixel signal is output via the sample and hold unit 506 and the output unit 507 sequentially.
As described above, according to the configuration shown in
“Front”. “back”, “up”, “down”, “right”, “left”, “vertical”, “horizontal”, “below”, “lateral”, “row”, and “column” and other terms expressing directions used in the present description are assumed to represent the orientation of the device of the present invention. Accordingly, the terms in the present description should be relatively interpreted in the device of the present invention.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.
Number | Date | Country | Kind |
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2013-178198 | Aug 2013 | JP | national |
This application is a continuation application based on a PCT International Application No. PCT/JP2014/070870, filed on Aug. 7, 2014, whose priority is claimed on Japanese Patent Application No. 2013-178198, filed on Aug. 29, 2013. Both the contents of the PCT International Application and the Japanese Patent Application are incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/JP2014/070870 | Aug 2014 | US |
Child | 14960899 | US |