Switching device with non-negative biasing

Abstract

Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

Description

FIELD

Embodiments of the present disclosure relate generally to the field of circuits, and more particularly to switching devices with non-negative biasing.

BACKGROUND

Radio frequency (RF) switching devices are used in many applications, such as in wireless communication systems, to selectively pass an RF signal. For switching devices that include field-effect transistors (FETs), a negative bias voltage is required to bias the FETs in an off state. The negative bias voltage is typically generated by a negative voltage generator that includes an oscillator and a charge pump. The oscillator may inject spurs into the RF core of the switching device, thereby causing spurious emissions.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 illustrates a circuit diagram of a switching device in accordance with various embodiments.

FIG. 2 illustrates a flow chart of a method for biasing a switching device in accordance with various embodiments.

FIG. 3 illustrates a circuit diagram of a single-pole, single-throw switch in accordance with various embodiments.

FIG. 4 illustrates a circuit diagram of a single-pole, single-throw switch with a plurality of series field-effect transistors (FETs) and a plurality of shunt FETs in accordance with various embodiments.

FIG. 5 is a block diagram of an exemplary wireless communication device in accordance with various embodiments.

DETAILED DESCRIPTION

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific devices and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The phrase “in one embodiment” is used repeatedly. The phrase generally does not refer to the same embodiment; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise.

In providing some clarifying context to language that may be used in connection with various embodiments, the phrases “NB” and “A and/or B” mean (A), (B), or (A and B); and the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

The term “coupled with,” along with its derivatives, may be used herein.

“Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.

FIG. 1 illustrates a switching circuit 100 in accordance with various embodiments. Switching circuit 100 (also referred to as circuit 100) may include a field-effect transistor (FET) 104 coupled with biasing circuitry 108. The FET 104 may include a drain terminal 112, a source terminal 116, a gate terminal 120, and a body 124. In some embodiments, the FET 104 may be an enhancement mode FET. Additionally, or alternatively, the FET 104 may be a silicon on insulator (SOI) device and/or a bulk complementary metal-oxide-semiconductor (CMOS) device.

In various embodiments, the FET 104 may selectively transition between an off state and an on state to facilitate switching of a transmission signal (e.g., a radio frequency (RF) signal). For example, the FET 104 may receive the transmission signal at the drain terminal 112 and pass the transmission signal to the source terminal 116 if the FET 104 is in the on state. The FET 104 may prevent the passage of the transmission signal between the drain terminal 112 and the source terminal 116 if the FET 104 is in the off state. The FET 104 may receive a control signal at the gate terminal 120 to transition the FET 104 between the off state and the on state.

In some embodiments, the FET 104 may be coupled in series with an interconnect to selectively pass the transmission signal to an output terminal (e.g., for transmission by an antenna and/or other structure). In other embodiments, the FET 104 may be coupled in shunt with the interconnect to selectively pass the transmission signal to a ground terminal (e.g., to divert the transmission signal and prevent it from being passed to the output terminal). As discussed below and shown in FIG. 3, some embodiments may include a switching module that includes a series transistor coupled in series with the interconnect and a shunt transistor coupled in shunt to the ground. In a first state of the switching module, the series transistor may be on and the shunt transistor may be off to pass the transmission signal to the output terminal. In a second state of the switching module, the series transistor may be off and the shunt transistor may be on to pass the transmission signal to the ground terminal and prevent the transmission signal from passing to the output terminal.

Various embodiments provide a biasing scheme to be used by the biasing circuitry 108 for the FET 104. The biasing scheme is discussed herein with reference to an n-type enhancement mode FET, however, in other embodiments, the biasing scheme may be used and/or modified for use with another type of FET, such as a p-type FET.

In various embodiments, the biasing circuitry 108 may produce direct current (DC) bias voltages to bias the drain terminal 112, the source terminal 116, the gate terminal 120, and/or the body 124 of the FET 104. The biasing circuitry 108 may bias the drain terminal 112 and the source terminal 116 to a first DC voltage in the on state and a second DC voltage in the off state. The second DC voltage may be different from the first DC voltage. In some embodiments, the biasing circuitry 108 may bias the gate terminal 120 to the second DC voltage in the on state and the first DC voltage in the off state. In some embodiments, the body 124 may be biased to the first voltage in the on state and the off state.

In various embodiments, the first and second DC voltages may be non-negative. For example, the first DC voltage may be a zero voltage (e.g. ground voltage), and the second DC voltage may be a positive voltage. In one non-limiting example, the second DC voltage may be about 1V to about 5V, such as about 2.5 Volts.

Accordingly, the biasing scheme described herein may use only non-negative bias voltages, thereby eliminating the need for an oscillator or a charge pump to generate a negative voltage. Thus, the potential for spurious emissions due to spurs from the oscillator is eliminated. Additionally, only two bias voltages may need to be generated to control the FET 104 during the on and off states. Furthermore, as discussed further below, only two control lines may be required to control a pair of transistors in a series-shunt configuration (e.g., a series transistor and a shunt transistor). Accordingly, the circuit 100 may occupy a smaller size (e.g., on a die) compared with a circuit that includes an oscillator, charge pump, and/or additional control lines.

Additionally, the biasing scheme may maintain a maximum voltage difference among the nodes of FET 104 (e.g., drain terminal 112, source terminal 116, gate terminal 120, and body 124), during the on and off states, equal to the difference between the first DC voltage and the second DC voltage.

FIG. 2 shows a flow chart of a method 200 of biasing a FET (e.g., FET 104) in accordance with various embodiments. In some embodiments, the method 200 may be performed by biasing circuitry, such as biasing circuitry 108.

At 204, the biasing circuitry may bias a drain terminal and a source terminal of the FET with a first non-negative DC voltage and a gate terminal of the FET with a second non-negative DC voltage. In some embodiments, the first non-negative DC voltage may be a ground voltage (e.g., zero Volts) and the second non-negative DC voltage may be a positive DC voltage (e.g., 2.5 Volts). The FET, given the biasing at 204, may be in an on state to selectively pass an RF signal at the drain terminal to the source terminal.

At 208, the biasing circuitry may bias the drain terminal and the source terminal with the second non-negative DC voltage and may bias the gate terminal with the first non-negative DC voltage. This may transition the FET to an off state in which the FET prevents the RF signal from passing from the drain terminal to the source terminal.

In some embodiments, a body of the FET may be biased to the first voltage in the on state and the off state.

FIG. 3 illustrates a switching circuit 300 (also referred to as a switching module or circuit 300) including a first FET (FET1) 304 (also referred to as series FET 304) and a second (FET2) FET 308 (also referred to as shunt FET 308) in accordance with various embodiments. The circuit 300 may be switchable between a first state and a second state. The circuit 300 may include an input terminal 312 that receives an RF signal (e.g., from a transmitter). The circuit 300 may pass the RF signal to an output terminal 316 if the circuit 300 is in the first state and may pass the RF signal to a ground terminal 320 if the circuit 300 is in the second state. In some embodiments, the output terminal 316 may be coupled with an antenna (not shown) for transmitting the RF signal.

The first FET 304 may be coupled in series between the input terminal 312 and the output terminal 316. The first FET 304 may also be described as being connected in series with an interconnect 318 running from the input terminal 312 to the output terminal 316. The first FET 304 may selectively pass the RF signal to the output terminal if the circuit 300 is in the first state. The first FET 304 may have a drain terminal 324, a source terminal 328, a gate terminal 332, and a body 336.

The second FET 308 may be coupled between the input terminal 312 and the ground terminal 320. The second FET 308 may also be described as being in shunt with the input terminal 312. The second FET 308 may selectively pass the RF signal to the ground terminal 320 if the circuit 300 is in the second state (thereby preventing the RF signal from passing to the output terminal 316). The second FET 308 may include a drain terminal 340, a source terminal 344, a gate terminal 348, and a body 352.

The circuit 300 may further include a first control terminal 356 and a second control terminal 360. The first control terminal 356 may receive a first control signal to bias the gate terminal 332 of the first FET 304, the drain terminal 340 and source terminal 344 of the second FET 308. The second control terminal 360 may receive a second control signal to bias the gate terminal 348 of the second FET 308, and the drain terminal 324 and source terminal 328 of the first FET 304. The circuit 300 may include bias circuitry 364 that provides the first control signal and the second control signal.

The first and second control terminals 356 and 360 may be coupled with the first FET 304 and/or second FET 308 in any suitable arrangement to bias the first FET 304 and/or second FET 308. For example, as shown in FIG. 3, the first control terminal 356 may be coupled with the gate terminal 332 of the first FET 304 (e.g., via a resistor R3 382) and coupled with the drain terminal 340 of the second FET 308 (e.g., via a resistor R1 368). The second control terminal 360 may be coupled with the gate terminal 348 of the second FET 308 (e.g., via a resistor R5 386) and the drain terminal 324 of the first FET 304 (e.g., via a resistor R2 372). The first FET 304 and second FET 308 may include a bias resistor (not shown) coupled between the respective drain terminals and source terminals to bias the source terminals at the same voltage as the respective drain terminals.

The circuit 300 may further include DC blocking capacitors 376a-d to facilitate the different bias voltages at the drain terminal 324 and source terminal 328 of the first FET 304 compared with the drain terminal 340 and source terminal 344 of the second FET 308 at a given time (e.g., in the first state or the second state). A first DC blocking capacitor C1 376a may be coupled between the input terminal 312 and the drain terminal 324 of first FET 304, and a second DC blocking capacitor C2 376b may be coupled between the input terminal 312 and the drain terminal 340 of the second FET 308. Capacitors C1 376a and C2 376b may isolate the DC voltage at the drain terminal 324 from the DC voltage at the drain terminal 340 to facilitate different bias voltages. A third DC blocking capacitor C3 376c may be coupled between the source terminal 328 of the first FET 304 and the output terminal 316 to isolate the DC voltage at the source terminal from the DC voltage at the output terminal 316. A fourth DC blocking capacitor C4 376d may be coupled between the source terminal 344 of the second FET 308 and the ground terminal 320 to isolate the DC voltage at the source terminal 344 from the DC voltage at the ground terminal 320.

In various embodiments, the first control signal may provide a first DC voltage during the second state of the circuit 300 and a second DC voltage during the first state of the circuit 300. The second control signal may provide the first DC voltage during the first state and the second DC voltage during the second state. The second DC voltage may be different from the first DC voltage, and the first and second DC voltages may both be non-negative. For example, the first DC voltage may be a ground voltage (e.g., zero Volts) and the second DC voltage may be a positive DC voltage (e.g., 2.5 Volts).

In various embodiments, the body 336 of the first FET 304 and the body 352 of the second FET 308 may be biased to the ground voltage (e.g., zero Volts) via resistors R4 384 and R6 388, respectively, during the first state and the second state of the circuit 300.

In various embodiments, in the first state of circuit 300, the first FET 304 may be on and the second FET 308 may be off. Accordingly, the first FET 304 may pass the RF signal from the input terminal 312 to the output terminal 316. In the second state of circuit 300, the first FET 304 may be off and the second FET 308 may be on. Accordingly, the first FET 304 may prevent the RF signal from passing to the output terminal 316, and the second FET 308 may pass the RF signal to the ground terminal 320.

Accordingly, the circuit 300 may require only two control lines (e.g., control terminals 356 and 360) to control both the series FET 304 and the shunt FET 308. Additionally, the circuit 300 may not require generation of a negative bias voltage. The additional DC blocking capacitors 376a-d may provide some insertion loss and/or reduced isolation, but the impact may be relatively minor (e.g., insertion loss of less than 0.04 dB). Thus, the circuit 300 may have a smaller size (e.g., die area) compared with prior switching circuits without substantial performance degradation.

It will be apparent that in some embodiments the first FET 304 may be included in a stack of a plurality of FETs coupled between the input terminal 312 and the output terminal 316 (e.g., a plurality of series FETs). Additionally, or alternatively, the second FET 308 may be included in a stack of a plurality of FETs coupled between the input terminal 312 and the ground terminal 320 (e.g., a plurality of shunt FETs).

For example, FIG. 4 illustrates a switching circuit 400 (also referred to as circuit 400) that is similar to circuit 300 except that circuit 400 includes a first stack of FETs 404 (e.g., including a plurality of FETs 404a-c) coupled in series between the an input terminal 412 and an output terminal 416, and a second stack of FETs 408 (e.g., a including a plurality of FETs 408a-c) coupled in shunt between the input terminal 412 and a ground terminal 420. The first stack of FETs 404 and/or second stack of FETs 408 may include any suitable number of FETs.

The circuit 400 further include a body resistor 422a-c coupled between a body terminal of the respective FET 404a-c and a common body node 426. Additionally, a gate resistor 430a-c may be coupled between a gate terminal of the respective FET 404a-c and a common gate node 434. In some embodiments, the circuit 400 may include a common resistor 438 coupled between the common body node 426 and ground, and a common resistor 442 coupled between the common gate node 434 and biasing circuitry 464. Other embodiments may not include the common resistor 438 and/or common resistor 442.

The circuit 400 may further include a body resistor 446a-c coupled between a body terminal of the respective FET 408a-c and a common body node 450. Additionally, a gate resistor 454a-c may be coupled between a gate terminal of the respective FET 408a-c and a common gate node 458. In some embodiments, the circuit 400 may include a common resistor 462 coupled between the common body node 450 and ground, and a common resistor 466 coupled between the common gate node 458 and biasing circuitry 464. Other embodiments may not include the common resistor 462 and/or common resistor 466.

A block diagram of an exemplary wireless communication device 500 is illustrated in FIG. 5 in accordance with some embodiments. Wireless communication device 500 may have an RF power amplifier (PA) module 504 including one or more RF PAs 508. RF PA module 504 may further include one or more RF switches 512 coupled with one or more of the RF PAs 508. The RF switches 512 may be similar to and/or include switching circuits 100, 300, and/or 400. Additionally, or alternatively, the RF switches 512 may be configured to carry out method 200.

In addition to the RF PA module 504, the wireless communication device 500 may have an antenna structure 514, a Tx/Rx switch 518, a transceiver 522, a main processor 526, and a memory 530 coupled with each other at least as shown. While the wireless communication device 500 is shown with transmitting and receiving capabilities, other embodiments may include devices with only transmitting or only receiving capabilities. While RF switches 512 are shown as included in RF PA module 504, in other embodiments, RF switches 512 may be included in other components of the wireless communication device 500, such as Tx/Rx switch 518 and/or transceiver 522, in addition to or instead of RF PA module 504.

In various embodiments, the wireless communication device 500 may be, but is not limited to, a mobile telephone, a paging device, a personal digital assistant, a text-messaging device, a portable computer, a desktop computer, a base station, a subscriber station, an access point, a radar, a satellite communication device, or any other device capable of wirelessly transmitting/receiving RF signals.

The main processor 526 may execute a basic operating system program, stored in the memory 530, in order to control the overall operation of the wireless communication device 500. For example, the main processor 526 may control the reception of signals and the transmission of signals by transceiver 522. The main processor 526 may be capable of executing other processes and programs resident in the memory 530 and may move data into or out of memory 530, as desired by an executing process.

The transceiver 522 may receive outgoing data (e.g., voice data, web data, e-mail, signaling data, etc.) from the main processor 526, may generate the RF_in signal(s) to represent the outgoing data, and provide the RF_in signal(s) to the RF PA module 504. The transceiver 522 may also control the RF PA module 504 to operate in selected bands and in either full-power or backoff-power modes. In some embodiments, the transceiver 522 may generate the RF_in signal(s) using OFDM modulation.

The RF PA module 504 may amplify the RF_in signal(s) to provide RF_out signal(s) as described herein. The RF_out signal(s) may be forwarded to the Tx/Rx switch 518 and then to the antenna structure 514 for an over-the-air (OTA) transmission. In some embodiments, Tx/Rx switch 518 may include a duplexer. In a similar manner, the transceiver 522 may receive an incoming OTA signal from the antenna structure 514 through the Tx/Rx switch 518. The transceiver 522 may process and send the incoming signal to the main processor 526 for further processing.

The one or more RF switches 512 may be used to selectively pass RF signal(s) (e.g., RF_in signal(s) and/or RF_out signal(s)) to, from, and/or within components of wireless communication device 500.

In various embodiments, the antenna structure 514 may include one or more directional and/or omnidirectional antennas, including, e.g., a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna or any other type of antenna suitable for OTA transmission/reception of RF signals.

Those skilled in the art will recognize that the wireless communication device 500 is given by way of example and that, for simplicity and clarity, only so much of the construction and operation of the wireless communication device 500 as is necessary for an understanding of the embodiments is shown and described. Various embodiments contemplate any suitable component or combination of components performing any suitable tasks in association with wireless communication device 500, according to particular needs. Moreover, it is understood that the wireless communication device 500 should not be construed to limit the types of devices in which embodiments may be implemented.

Although the present disclosure has been described in terms of the above-illustrated embodiments, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. Those with skill in the art will readily appreciate that the teachings of the present disclosure may be implemented in a wide variety of embodiments. This description is intended to be regarded as illustrative instead of restrictive.

Claims

1. An apparatus comprising: a field-effect transistor (FET) configured to transition between an off state and an on state to facilitate switching of a transmission signal, the FET having a gate terminal, a drain terminal, and a source terminal; andbiasing circuitry coupled with the FET and configured to: bias the drain terminal and the source terminal to a first direct current (DC) voltage in the on state and a second DC voltage in the off state, the second DC voltage being different from the first DC voltage; andbias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

2. The apparatus of claim 1, wherein the gate terminal of the FET is to receive a control signal to switch the FET between the off state and the on state.

3. The apparatus of claim 2, wherein the FET further includes a body, and wherein the biasing circuitry is configured to bias the body to the first voltage in the on state and the off state.

4. The apparatus of claim 2, wherein the first and second DC voltages are non-negative.

5. The apparatus of claim 4, wherein the first DC voltage is a zero voltage and the second DC voltage is a positive voltage.

6. The apparatus of claim 2, wherein the FET is an enhancement mode FET.

7. The apparatus of claim 6, wherein the FET is a silicon on insulator or bulk complementary metal-oxide-semiconductor device.

8. A switching apparatus comprising: an input terminal configured to receive a radio frequency (RF) signal, the switching apparatus configured to pass the RF signal to an output terminal if the switching apparatus is in a first state and to pass the RF signal to a ground terminal if the switching apparatus is in a second state;a first field-effect transistor (FET) coupled in series between the input terminal and the output terminal to selectively pass the RF signal to the output terminal if the switching apparatus is in the first state, the first FET having a first gate terminal and a first drain terminal;a second FET coupled between the input terminal and the ground terminal and having a second gate terminal and a second drain terminal;a first control terminal configured to receive a first control signal to bias the first gate terminal and the second drain terminal; anda second control terminal configured to receive a second control signal to bias the second gate terminal and the first drain terminal.

9. The switching apparatus of claim 8, wherein the first control signal provides a first direct current (DC) voltage during the second state and a second DC voltage during the first state, the second DC voltage being different from the first DC voltage, and the first and second DC voltages being non-negative.

10. The switching apparatus of claim 9, wherein the second control signal provides the second DC voltage during the second state and the first DC voltage during the first state.

11. The switching apparatus of claim 10, wherein the first DC voltage is a ground voltage and the second DC voltage is a positive DC voltage.

12. The switching apparatus of claim 8, wherein the first FET further includes a first body and the second FET further includes a second body, wherein the first and second bodies are configured to be biased to a ground voltage during the first state and the second state.

13. The switching apparatus of claim 8, further comprising: a first DC-blocking capacitor coupled between the input terminal and the first drain terminal; anda second DC-blocking capacitor coupled between the input terminal and the second drain terminal.

14. The switching apparatus of claim 13, wherein the first FET further includes a first source terminal and the second FET further includes a second source terminal, and wherein the switching apparatus further comprises: a third DC-blocking capacitor coupled between the first source terminal and the first output terminal; anda fourth DC-blocking capacitor coupled between the second source terminal and the ground terminal.

15. The switching apparatus of claim 14, wherein the input terminal is configured to receive the RF signal from a transmitter and to pass the RF signal to an antenna for transmission over a wireless communication network if the switching apparatus is in the first state.

16. The switching apparatus of claim 8, further comprising: a plurality of series FETs, including the first FET, coupled in series between the input terminal and the output terminal; anda plurality of shunt FETs, including the second FET, coupled in shunt between the input terminal and the ground terminal.

17. A system comprising: a transmitter configured to produce a radio frequency (RF) signal;an antenna configured to send the RF signal over a wireless communication network; anda field-effect transistor (FET) coupled between the transmitter and the antenna, the FET configured to pass the RF signal to the antenna if the FET is in an on state and to prevent passage of the RF signal to the antenna if the FET is in an off state, the FET including: a drain terminal configured to receive the RF signal;a source terminal configured to pass the RF signal to the antenna if the FET is in the on state; anda gate terminal; andbiasing circuitry coupled with the FET and configured to bias the gate terminal to a zero direct current (DC) voltage if the FET is in the off state and a positive DC voltage if the FET is in the on state, wherein the biasing circuitry is further configured to bias the drain terminal and source terminal to the positive DC voltage in the off state and the zero DC voltage in the on state.

18. The system of claim 17, wherein the FET further includes a body terminal, and wherein the biasing circuitry is further configured to bias the body terminal to a zero voltage in the on state and the off state.

19. The system of claim 17, wherein the FET is a first FET, the drain terminal is a first drain terminal, the source terminal is a first source terminal, and the gate terminal is a first gate terminal, and the system further comprising a second FET coupled between the transmitter and a ground terminal, the second FET having an off state and an on state and configured to pass the RF signal from the transmitter to the ground terminal if the second FET is in the on state, the second FET including: a second drain terminal configured to receive the RF signal;a second source terminal; anda second gate terminal;wherein the biasing circuitry is further configured to:bias the second source terminal and the second drain terminal to the positive DC voltage if the second FET is in the off state and the zero DC voltage if the second FET is in the on state; andbias the second gate terminal to the zero DC voltage if the second FET is in the off state and the positive DC voltage if the second FET is in the on state.

20. The system of claim 19, wherein the biasing circuitry includes: a first control terminal configured to bias the first gate terminal, the second drain terminal, and the second source terminal;a second control terminal configured to bias the second gate terminal, the first drain terminal, and the first source terminal.