The present disclosure is related to U.S. patent application Ser. No. 15/277,465, filed Sep. 27, 2016, and entitled “Amplifier with Configurable Final Output Stage,” which is incorporated herein by reference.
The present disclosure relates in general to circuits for audio devices, including without limitation personal audio devices, such as wireless telephones and media players, and more specifically, to systems and methods relating to switching between configurations of an audio system with multiple playback paths.
Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers. Generally speaking, a power amplifier amplifies an audio signal by taking energy from a power supply and controlling an audio output signal to match an input signal shape but with a larger amplitude.
One example of an audio amplifier is a class-D amplifier. A class-D amplifier (also known as a “switching amplifier”) may comprise an electronic amplifier in which the amplifying devices (e.g., transistors, typically metal-oxide-semiconductor field effect transistors) operate as electronic switches, and not as linear gain devices as in other amplifiers (e.g., class-A, class-B, and class-AB amplifiers). In a class-D amplifier, an analog signal to be amplified may be converted to a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that the analog signal is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of the analog signal. After amplification with a class-D amplifier, the output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in the class-D amplifier or a load driven by the class-D amplifier. Class-D amplifiers are often used due to the fact that they may be more power efficient than linear analog amplifiers, in that class-D amplifiers may dissipate less power as heat in active devices as compared to linear analog amplifiers. However, class-D amplifiers may have high quiescent power when amplifying low-magnitude signals and may require a large amount of area in order to meet stringent dynamic range requirements in audio devices.
Accordingly, it may be desired to have an amplifier that has a configurable final output stage, wherein the final output stage is configurable between a Class-AB output stage and a Class-D output stage. However, having an amplifier with a configurable output stage may be susceptible to audio artifacts caused by switching between the modes of the final output stage.
In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to signal amplification in an audio system may be reduced or eliminated.
In accordance with embodiments of the present disclosure, a system may include a playback path and a control circuit. The playback path may have a playback input for receiving an input signal and configured to generate at a playback path output an output signal based on the input signal, wherein the playback path is configured to operate in a plurality of operational modes. The control circuit may be configured to receive a first signal from within the playback path and indicative of the input signal, receive a second signal generated from the input signal externally to the playback path, and select a selected operational mode from the plurality of operational modes based on the first signal and the second signal.
In accordance with these and other embodiments of the present disclosure, a method may include receiving a first signal from within a playback path and indicative of an input signal, wherein the playback path comprises a playback input for receiving the input signal and configured to generate at a playback path output an output signal based on the input signal, and wherein the playback path is configured to operate in a plurality of operational modes. The method may also include receiving a second signal generated from the input signal externally to the playback path and selecting a selected operational mode from the plurality of operational modes based on the first signal and the second signal.
Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
First stage 22 may include any suitable analog front end circuit for conditioning analog input signal VIN for use by final output stage 24. For example, first stage 22 may include one or more analog integrators 32 cascaded in series, as shown in
Final output stage 24 may include any suitable driving circuit for driving audio output signal VOUT as a function of intermediate signal VINT (thus, also making audio output signal VOUT a function of analog input signal VIN) wherein final output stage 24 is switchable among a plurality of modes including at least a first mode in which final output stage 24 generates audio output signal VOUT as a modulated output signal which is a function of intermediate signal VINT and a second mode in which final output stage 24 generates audio output signal VOUT as an unmodulated output signal which is a function of intermediate signal VINT. To carry out this functionality, final output stage 24 may include a class-D audio output stage 42 which may be enabled in the first mode (and disabled in the second mode) to generate audio output signal VOUT as a modulated output signal which is a function of intermediate signal VINT and a class-AB audio output stage 44 which may be enabled in the second mode (and disabled in the first mode) to generate audio output signal VOUT as an unmodulated output signal which is a function of intermediate signal VINT.
Class-D audio output stage 42 may comprise any suitable system, device, or apparatus configured to amplify intermediate signal VINT and convert intermediate signal VINT into a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that intermediate signal VINT is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of intermediate signal VINT. After amplification by class-D audio output stage 42, its output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in output circuitry of class-D audio output stage 42 or a load driven by final output stage 24. As shown in
Class-AB audio output stage 44 may comprise any suitable system, device, or apparatus configured to amplify intermediate signal VINT with a linear gain and convert intermediate signal VINT into an unmodulated audio output signal VOUT. For example, in some embodiments, unmodulated audio output signal VOUT may include a continuous-time baseband signal (e.g., an audio baseband signal). As shown in
As shown in
In some embodiments, a signal gain (e.g., VOUT/VINT) of final output stage 24 in the first mode may be approximately equal to the signal gain of final output stage 24 in the second mode. In these and other embodiments, an offset (e.g., direct current offset) of final output stage 24 in the first mode may be approximately equal to the offset of final output stage 24 in the second mode.
As shown in
Signal feedback network 26 may include any suitable feedback network for feeding back a signal indicative of audio output signal VOUT to the amplifier input of amplifier 16. For example, as shown in
Thus, final output stage 24 may operate as an open-loop switched-mode driver in the first mode and may operate as a continuous-time closed-loop amplifier in the second mode. In addition, when the final output stage is operating in the second mode, amplifier 16 may comprise a first feedback loop including signal feedback network 26 and a second feedback loop coupled between the amplifier output and the intermediate output implemented by signal feedback network 50.
Control circuit 28 may include any suitable system, device, or apparatus configured to receive information indicative of digital audio input signal DIG_IN, audio output voltage VOUT, intermediate signal VINT, and/or another operational characteristic of amplifier 16, and based at least thereon, control operation of one or more components of amplifier 16. For example, control circuit 28 may be configured to, based on a characteristic of digital audio input signal DIG_IN and/or analog input signal VIN (e.g., which may be determined from receiving and analyzing digital audio input signal DIG_IN, analog input signal VIN, intermediate signal VINT and/or audio output signal VOUT), switch between the first mode and the second mode of final output stage 24. Such characteristic may include one or more of a frequency of analog input signal VIN, an amplitude of analog input signal VIN, a signal-to-noise ratio of analog input signal VIN, a noise floor of analog input signal VIN, or another noise characteristic of analog input signal VIN. For example, in some embodiments, control circuit 28 may be configured to switch final output stage 24 from the first mode to the second mode when an amplitude of analog input signal VIN decreases below a threshold amplitude, and may be configured to switch final output stage 24 from the second mode to the first mode when an amplitude of analog input signal VIN increases above the same threshold amplitude or another threshold amplitude. In some embodiments, to reduce audio artifacts associated with switching between modes, control circuit 28 may also be configured to switch between modes only when the amplitude of audio output signal VOUT is approximately zero (e.g., when a modulated signal generated by class-D audio output stage 42 is at its minimum voltage in its generated pulse train).
In these and other embodiments, control circuit 28 may further be configured to, in order to reduce audio artifacts induced by switching between the two modes, cause final output stage 24 to switch between the first mode and the second mode at an approximate completion of a modulation period of the modulated output signal output by Class-D audio output stage 42, and cause final output stage 24 to switch between the second mode and the first mode at an approximate beginning of another modulation period of the modulated output signal output by Class-D audio output stage 42.
In these and other embodiments, control circuit 28 may further be configured to, in order to reduce audio artifacts induced by switching between the two modes, control preconditioning circuit 49 and components thereof as described elsewhere in this disclosure.
In addition, control circuit 28 may also be configured to perform calibration of final output stage 24. For example, control circuit 28 may receive and analyze intermediate signal VINT and audio output signal VOUT to determine a gain of class-D audio output stage 42 (e.g., the signal gain of final output stage 24 in the first mode) and a gain of class-AB audio output stage 44 (e.g., the signal gain of final output stage 24 in the second mode), and based thereon, modify the gain of class-D audio output stage 42 and/or the gain of class-AB audio output stage 44 in order to calibrate the signal gain of final output stage 24 in the second mode to match the signal gain of final output stage 24 in the first mode. As another example, control circuit 28 may receive and analyze intermediate signal VINT and/or audio output signal VOUT to determine an offset (e.g., direct current offset) of class-D audio output stage 42 (e.g., the offset of final output stage 24 in the first mode) and an offset of class-AB audio output stage 44 (e.g., the offset of final output stage 24 in the second mode), and based thereon, modify the offset of class-D audio output stage 42 and/or the offset of class-AB audio output stage 44 in order to calibrate the offset of final output stage 24 in the second mode to match the offset of final output stage 24 in the first mode.
In these and other embodiments, control circuit 28 may also be configured to control characteristics of first stage 22 (e.g., integrator 32) and/or signal feedback network 26. Control circuit 28 may maintain such characteristics and structure of first stage 22 and signal feedback network 26 as static when switching between the first mode and the second mode of final output stage 24 and when switching between the second mode and the first mode. Maintaining the characteristics and structure of first stage 22 and signal feedback network 26 as static when switching between modes allows the modes to share the same analog front end and feedback network, thus reducing or minimizing the likelihood of mismatched signal gain and offset between the modes, and thus reducing or minimizing audio artifacts caused by switching between modes. However, after control circuit 28 has switched final output stage 24 to the second mode (e.g., amplifier output driven by class-AB audio output stage 44), control circuit 28 may modify characteristics of first stage 22 and/or signal feedback network 26 in order to decrease a noise floor of amplifier 16. For example, in some embodiments, control circuit 28 may modify characteristics of integrator 32 (e.g., resistances and/or capacitances of filters internal to integrator 32) and/or other components of first stage 22 in order to decrease a noise floor of amplifier 16 when final output stage 24 operates in the second mode. As another example, in these and other embodiments, control circuit 28 may modify characteristics of signal feedback network 26 (e.g., resistances of variable feedback resistors 48) in order to decrease a noise floor of amplifier 16 when final output stage 24 operates in the second mode. When making such modification, control circuit 28 may, before switching final output stage 24 from the second mode to the first mode, return such characteristics to their unmodified states.
Thus, in operation, when switching between modes of final output stage 24 from its class-D mode of operation to class-AB mode of operation, switches 92 may be activated and switches 94 deactivated under the control of control signals communicated from control circuit 28 to allow operation of class-AB audio output stage 44B to settle into a normal steady-state operation before coupling the output of class-AB driver stage 90 to the output of final output stage 24. After class-AB output stage 44B has settled (and other conditions for switching between modes of final output stage 24 have been satisfied, as described elsewhere in this disclosure), switches 94 may be activated and switches 92 deactivated under the control of control signals communicated from control circuit 28 in order to couple the output of class-AB driver stage 90 to the output of final output stage 24. Accordingly, during the process of switching between modes of final output stage 24 from its class-D mode of operation to class-AB mode of operation, the replica of class-AB driver stage 90 formed by p-MOSFET 96 and N-MOSFET 98 may precondition at least one of the voltage (e.g., voltage VOUT) and the current of the output of final output stage 28 by charging the output to a common mode voltage of class-AB driver stage 90 using a replica of class-AB driver stage 90 to provide the common mode voltage.
Although
Clamp 46 of preconditioning circuit 49B may be similar to that of clamp 46 of preconditioning circuit 49A. When preconditioning circuit 49B is enabled under the control of control signals communicated from control circuit 28, clamp 46 may be enabled to short the output terminals of final output stage 24 together, switch 43 may be activated, and switch 41 deactivated to allow charge present on capacitor 39 to charge each of the output terminals of final output stage 24 to a common mode voltage Vcm. When preconditioning circuit 49B is disabled under the control of control signals communicated from control circuit 28, clamp 46 may be disabled, switch 41 may be activated, and switch 43 deactivated to allow capacitor 39 to charge to common mode voltage Vcm. Those of skill in the art may recognize that a dual equivalent current source and inductor may be substituted in place of voltage Vcm and capacitor 39 such that the inductor may precondition a current of the output terminals of final output stage 24 when preconditioning circuit 49B is enabled.
At step 52, control circuit 28 may monitor intermediate signal VINT, audio output signal VOUT, or another signal indicative of analog input signal VIN, to determine if analog input signal VIN has decreased from above to below a threshold amplitude. If analog input signal VIN has decreased from above to below the threshold amplitude, method 51 may proceed to step 53. Otherwise, method 51 may remain at step 52 until such threshold amplitude crossing occurs.
At step 53, control circuit 28 may monitor audio output signal VOUT to determine when the amplitude of audio output signal VOUT is approximately zero (e.g., when a modulated signal generated by class-D audio output stage 42 is at its minimum voltage in its generated pulse train). If audio output signal VOUT has reached approximately zero, method 51 may proceed to step 54. Otherwise, method 51 may remain at step 53 until audio output signal VOUT reaches approximately zero.
At step 54, control circuit 28 may cause class-AB amplifier 44 to power on from a powered-off or powered-down state, which state class-AB amplifier 44 may operate in order to save power when final output stage 24 is operating in the class-D mode.
At step 55, control circuit 28 may monitor audio output signal VOUT to determine when class-AB amplifier 44 has settled into a steady-state operation from being powered on. Once class-AB amplifier 44 has settled, method 51 may proceed to step 56.
At step 56, control circuit 28 may enable clamp 46, thus shorting the output terminals at the amplifier output of amplifier 16 together, forcing audio output signal VOUT to zero. At step 57, control circuit 28 may disable class-D amplifier 42. For example, class-D amplifier 42 may be disabled by deactivating switches integral to class-D amplifier 42 such that the output terminals of class-D amplifier 42 are in a high-impedance state.
At step 58, class-AB audio output stage 44 and/or preconditioning circuit 49 may ramp a common mode voltage of audio output signal VOUT to a predetermined value (e.g., a common-mode voltage equal to one-half of a supply voltage for class-AB audio output stage 44). At step 60, control circuit 28 may fully enable class-AB audio output stage 44 such that audio output signal VOUT is an unmodulated signal which is a function of intermediate signal VINT. For example, class-AB amplifier 44 may be enabled by activating switches integral to class-AB amplifier 44 (e.g., switches 94 depicted in
At step 62, control circuit 28 may disable clamp 46, thus allowing audio output signal VOUT to take on a non-zero value driven by class-AB audio output stage 44. After completion of step 62, method 51 may end.
Although
Method 51 may be implemented using personal audio device 1 or any other system operable to implement method 51. In certain embodiments, method 51 may be implemented partially or fully in software and/or firmware embodied in computer-readable media and executable by a controller.
At step 72, control circuit 28 may monitor intermediate signal VINT, audio output signal VOUT, or another signal indicative of analog input signal VIN, to determine if analog input signal VIN has increased from below to above a threshold amplitude (which may be the same threshold as that of step 52, or a different threshold). If analog input signal VIN has increased from below to above the threshold amplitude, method 70 may proceed to step 73. Otherwise, method 70 may remain at step 72 until such threshold amplitude crossing occurs.
At step 73, control circuit 28 may monitor audio output signal VOUT to determine when the amplitude of audio output signal VOUT is approximately zero (e.g., when audio output signal VOUT experiences a zero crossing). If audio output signal VOUT is approximately zero, method 70 may proceed to step 74. Otherwise, method 70 may remain at step 73 until audio output signal VOUT is approximately zero.
At step 74, control circuit 28 may cause class-D amplifier 42 to power on from a powered-off or powered-down state, which state class-D amplifier 42 may operate in order to save power when final output stage 24 is operating in the class-AB mode.
At step 75, control circuit 28 may monitor audio output signal VOUT to determine when class-D amplifier 42 has settled into a steady-state operation from being powered on. Once class-D amplifier 42 has settled, method 70 may proceed to step 76.
At step 76, control circuit 28 may enable clamp 46, thus shorting the output terminals at the amplifier output of amplifier 16 together, forcing audio output signal VOUT to zero. At step 77, control circuit 28 may disable class-AB amplifier 44. For example, class-AB amplifier 44 may be disabled by activating switches integral to class-AB amplifier 44 (e.g., switches 94 depicted in
At step 78, preconditioning circuit 49 (or another auxiliary amplifier, not shown in
At step 82, control circuit 28 may disable clamp 46, thus allowing audio output signal VOUT to take on a non-zero value driven by class-D audio output stage 42. After completion of step 82, method 70 may end.
Although
Method 70 may be implemented using personal audio device 1 or any other system operable to implement method 70. In certain embodiments, method 70 may be implemented partially or fully in software and/or firmware embodied in computer-readable media and executable by a controller.
A particular challenge in determining whether to switch between modes of final output stage 24 is that detection of in-band signal levels for such switching requires low-pass filtering. However, such a low-pass filter adds latency to the determination of whether to switch nodes. Thus, for a rising magnitude of an input signal, the latency in such determination of whether to switch modes (e.g., from the second mode with Class AB output stage 44 enabled to the first mode with Class D output stage 42 enabled) may cause switching to occur too slowly, such that signal clipping of the output signal occurs.
As shown in
Ones density detector 122 may include any system, device, or apparatus configured to determine (particularly in embodiments in which digital audio input signal DIG_IN is a pulse-density modulated signal) a density of logical ones of digital audio input signal DIG_IN and generate an output signal indicative of such density. Such output signal may be received by comparator 128 and compared by comparator 128 against a threshold density THRA in order to generate an intermediate switching signal SWA.
Inline filter 124 may include any suitable filter configured to receive digital audio input signal DIG_IN and low-pass filter digital audio input signal DIG_IN to generate a low-pass filtered version of digital audio input signal DIG_IN. Such filtered signal may be received by comparator 130 and compared by comparator 130 against a threshold density THRB in order to generate an intermediate switching signal SWB. As its name indicates, inline filter 124 may be integral to the signal path between digital audio input signal DIG_IN and audio output signal VOUT, and thus may generate an output signal FILT that may represent an intermediate voltage internal to DAC 14, first stage 22, or any other suitable portion of amplifier 16 comprising the signal path between digital audio input signal DIG_IN and audio output signal VOUT.
Offline filter 126 may include any suitable filter configured to receive digital audio input signal DIG_IN and low-pass filter digital audio input signal DIG_IN to generate a low-pass filtered version of digital audio input signal DIG_IN. Such filtered signal may be received by comparator 132 and compared by comparator 132 against a threshold density THRC in order to generate an intermediate switching signal SWC. As its name indicates, offline filter 126 may be external to the signal path between digital audio input signal DIG_IN and audio output signal VOUT. Because it is external to the signal path, offline filter 126 may be of a higher latency (and thus greater accuracy) than inline filter 124.
Logical OR gate 134 may perform a logical OR operation on the intermediate switching signals SWA, SWB, and SWC and generate a switching signal SWITCH that indicates that final output stage 24 of amplifier 16 should switch from the second mode (e.g., Class-AB output stage 44 enabled) to the first mode (e.g., Class-D output stage 42 enabled) in response to digital audio input signal DIG_IN increasing in magnitude. Accordingly, an assertion of any of switching signals SWA, SWB, and SWC may trigger a switch between the second mode to the first mode of final output stage 24. Due to their individual characteristics, the combination of ones density detector 122 and comparator 128 may be best suited for detecting threshold crossings of fast-rising signal magnitudes of digital audio input signal DIG_IN, the combination of inline filter 124 and comparator 130 may be best suited for detecting threshold crossings of medium-rising signal magnitudes of digital audio input signal DIG_IN, and the combination of offline filter 126 and comparator 132 may be best suited for detecting threshold crossings of slow-rising signal magnitudes of digital audio input signal DIG_IN. Accordingly, control circuit 28 may efficiently switch from the second mode (e.g., Class-AB output stage 44 enabled) to the first mode (e.g., Class-D output stage 42 enabled) of final output stage 24 while reducing or eliminating audio artifacts of switching.
The various thresholds THRA, THRB, and THRC may be equal/equivalent, or may be different. For example, in some embodiments, threshold THRB may be larger than threshold THRC to account for noise present in inline filter 124 and/or noise present in all or a portion of the signal path between digital audio input signal DIG_IN and audio output signal VOUT. Thus, control circuit 28 may set threshold THRB relative to threshold THRC by measuring a difference between the filtered signal output by inline filter 124 and the filtered signal output by offline filter 126 when digital audio input signal DIG_IN is zero, such that the difference is indicative of noise present in inline filter 124, and setting threshold THRB based on the difference.
Although the foregoing contemplates use of the components of control circuit 28 depicted in
As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.
This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.
All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.
Number | Name | Date | Kind |
---|---|---|---|
3683164 | Minami | Aug 1972 | A |
4346349 | Yokoyama | Aug 1982 | A |
4441081 | Jenkins | Apr 1984 | A |
4446440 | Bell | May 1984 | A |
4493091 | Gundry | Jan 1985 | A |
4628526 | Germer | Dec 1986 | A |
4890107 | Pearce | Dec 1989 | A |
4972436 | Halim et al. | Nov 1990 | A |
4999628 | Kakaubo et al. | Mar 1991 | A |
4999830 | Agazzi | Mar 1991 | A |
5077539 | Howatt | Dec 1991 | A |
5148167 | Ribner | Sep 1992 | A |
5198814 | Ogawara et al. | Mar 1993 | A |
5212551 | Conanan | May 1993 | A |
5272449 | Izawa | Dec 1993 | A |
5321758 | Charpentier et al. | Jun 1994 | A |
5323159 | Imamura et al. | Jun 1994 | A |
5343161 | Tokumo et al. | Aug 1994 | A |
5434560 | King et al. | Jul 1995 | A |
5495505 | Kundmann | Feb 1996 | A |
5550923 | Hotvet et al. | Jul 1996 | A |
5600317 | Knoth et al. | Feb 1997 | A |
5714956 | Jahne et al. | Feb 1998 | A |
5719641 | Mizoguchi | Feb 1998 | A |
5771301 | Fuller et al. | Jun 1998 | A |
5796303 | Vinn et al. | Aug 1998 | A |
5808575 | Himeno et al. | Sep 1998 | A |
5810477 | Abraham et al. | Sep 1998 | A |
6088461 | Lin | Jul 2000 | A |
6160455 | French et al. | Dec 2000 | A |
6201490 | Kawano et al. | Mar 2001 | B1 |
6260176 | Chen | Jul 2001 | B1 |
6271780 | Gong et al. | Aug 2001 | B1 |
6333707 | Oberhammer et al. | Dec 2001 | B1 |
6353404 | Kuroiwa | Mar 2002 | B1 |
6542612 | Needham | Apr 2003 | B1 |
6614297 | Score | Sep 2003 | B2 |
6683494 | Stanley | Jan 2004 | B2 |
6745355 | Tamura | Jun 2004 | B1 |
6768443 | Willis | Jul 2004 | B2 |
6810266 | Ecklund et al. | Oct 2004 | B1 |
6822595 | Robinson | Nov 2004 | B1 |
6853242 | Melanson et al. | Feb 2005 | B2 |
6888888 | Tu et al. | May 2005 | B1 |
6897794 | Kuyel et al. | May 2005 | B2 |
6989955 | Ziemer et al. | Jan 2006 | B2 |
7020892 | Levesque et al. | Mar 2006 | B2 |
7023268 | Taylor et al. | Apr 2006 | B1 |
7061312 | Andersen et al. | Jun 2006 | B2 |
7167112 | Andersen et al. | Jan 2007 | B2 |
7216249 | Fujiwara et al. | May 2007 | B2 |
7279964 | Bolz et al. | Oct 2007 | B2 |
7302354 | Zhuge | Nov 2007 | B2 |
7312734 | McNeill et al. | Dec 2007 | B2 |
7315204 | Seven | Jan 2008 | B2 |
7365664 | Caduff et al. | Apr 2008 | B2 |
7378902 | Sorrells et al. | May 2008 | B2 |
7385443 | Denison | Jun 2008 | B1 |
7403010 | Hertz | Jul 2008 | B1 |
7440891 | Shozakai et al. | Oct 2008 | B1 |
7522677 | Liang | Apr 2009 | B2 |
7583215 | Yamamoto et al. | Sep 2009 | B2 |
7671768 | De Ceuninck | Mar 2010 | B2 |
7679538 | Tsang | Mar 2010 | B2 |
7733592 | Hutchins et al. | Jun 2010 | B2 |
7737776 | Cyrusian | Jun 2010 | B1 |
7893856 | Ek et al. | Feb 2011 | B2 |
7924189 | Sayers | Apr 2011 | B2 |
7937106 | Sorrells et al. | May 2011 | B2 |
7952502 | Kolze et al. | May 2011 | B2 |
8060663 | Murray et al. | Nov 2011 | B2 |
8130126 | Breitschaedel et al. | Mar 2012 | B2 |
8194889 | Seefeldt | Jun 2012 | B2 |
8298425 | Kanbe | Oct 2012 | B2 |
8330631 | Kumar et al. | Dec 2012 | B2 |
8362936 | Ledzius et al. | Jan 2013 | B2 |
8462035 | Schimper et al. | Jun 2013 | B2 |
8483753 | Behzad et al. | Jul 2013 | B2 |
8508397 | Hisch | Aug 2013 | B2 |
8717211 | Miao et al. | May 2014 | B2 |
8786477 | Albinet | Jul 2014 | B1 |
8836551 | Nozaki | Sep 2014 | B2 |
8873182 | Liao et al. | Oct 2014 | B2 |
8878708 | Sanders et al. | Nov 2014 | B1 |
8952837 | Kim et al. | Feb 2015 | B2 |
9071201 | Jones et al. | Jun 2015 | B2 |
9071267 | Schneider et al. | Jun 2015 | B1 |
9071268 | Schneider et al. | Jun 2015 | B1 |
9118401 | Nieto et al. | Aug 2015 | B1 |
9148164 | Schneider et al. | Sep 2015 | B1 |
9171552 | Yang | Oct 2015 | B1 |
9178462 | Kurosawa et al. | Nov 2015 | B2 |
9210506 | Nawfal et al. | Dec 2015 | B1 |
9306588 | Das et al. | Apr 2016 | B2 |
9337795 | Das et al. | May 2016 | B2 |
9391576 | Satoskar et al. | Jul 2016 | B1 |
9444504 | Robinson et al. | Sep 2016 | B1 |
9503027 | Zanbaghi | Nov 2016 | B2 |
9525940 | Schneider et al. | Dec 2016 | B1 |
9543975 | Melanson et al. | Jan 2017 | B1 |
9584911 | Das et al. | Feb 2017 | B2 |
9596537 | He et al. | Mar 2017 | B2 |
9635310 | Chang et al. | Apr 2017 | B2 |
9680488 | Das et al. | Jun 2017 | B2 |
9762255 | Satoskar et al. | Sep 2017 | B1 |
9774342 | Schneider et al. | Sep 2017 | B1 |
9780800 | Satoskar et al. | Oct 2017 | B1 |
9807504 | Melanson et al. | Oct 2017 | B2 |
9813814 | Satoskar | Nov 2017 | B1 |
9831843 | Das et al. | Nov 2017 | B1 |
9917557 | Zhu et al. | Mar 2018 | B1 |
9929703 | Zhao | Mar 2018 | B1 |
20010001547 | Delano et al. | May 2001 | A1 |
20010009565 | Singvall | Jul 2001 | A1 |
20040078200 | Alves | Apr 2004 | A1 |
20040184621 | Andersen et al. | Sep 2004 | A1 |
20050068097 | Kirn et al. | Mar 2005 | A1 |
20050084037 | Liang | Apr 2005 | A1 |
20050258989 | Li et al. | Nov 2005 | A1 |
20050276359 | Xiong | Dec 2005 | A1 |
20060056491 | Lim et al. | Mar 2006 | A1 |
20060064037 | Shalon et al. | Mar 2006 | A1 |
20060098827 | Paddock et al. | May 2006 | A1 |
20060261886 | Hansen et al. | Nov 2006 | A1 |
20060284675 | Krochmal et al. | Dec 2006 | A1 |
20070018719 | Seven | Jan 2007 | A1 |
20070026837 | Bagchi | Feb 2007 | A1 |
20070057720 | Hand et al. | Mar 2007 | A1 |
20070092089 | Seefeldt et al. | Apr 2007 | A1 |
20070103355 | Yamada | May 2007 | A1 |
20070120721 | Caduff et al. | May 2007 | A1 |
20070123184 | Nesimoglu et al. | May 2007 | A1 |
20070142943 | Torrini et al. | Jun 2007 | A1 |
20070146069 | Wu | Jun 2007 | A1 |
20080012639 | Mels | Jan 2008 | A1 |
20080030577 | Cleary et al. | Feb 2008 | A1 |
20080114239 | Randall et al. | May 2008 | A1 |
20080143436 | Xu | Jun 2008 | A1 |
20080159444 | Terada | Jul 2008 | A1 |
20080198048 | Klein et al. | Aug 2008 | A1 |
20080278632 | Morimoto | Nov 2008 | A1 |
20080292107 | Bizjak | Nov 2008 | A1 |
20090015327 | Wu | Jan 2009 | A1 |
20090021643 | Hsueh et al. | Jan 2009 | A1 |
20090051423 | Miaille | Feb 2009 | A1 |
20090058531 | Hwang et al. | Mar 2009 | A1 |
20090084586 | Nielsen | Apr 2009 | A1 |
20090220110 | Bazarjani et al. | Sep 2009 | A1 |
20100168882 | Zhang et al. | Jul 2010 | A1 |
20100176980 | Breitschadel et al. | Jul 2010 | A1 |
20100183163 | Matsui et al. | Jul 2010 | A1 |
20100195771 | Takahashi | Aug 2010 | A1 |
20110013733 | Martens et al. | Jan 2011 | A1 |
20110025540 | Katsis | Feb 2011 | A1 |
20110029109 | Thomsen et al. | Feb 2011 | A1 |
20110044414 | Li | Feb 2011 | A1 |
20110063148 | Kolze et al. | Mar 2011 | A1 |
20110096370 | Okamoto | Apr 2011 | A1 |
20110136455 | Sundstrom et al. | Jun 2011 | A1 |
20110150240 | Akiyama et al. | Jun 2011 | A1 |
20110170709 | Guthrie et al. | Jul 2011 | A1 |
20110188671 | Anderson et al. | Aug 2011 | A1 |
20110228952 | Lin | Sep 2011 | A1 |
20110242614 | Okada | Oct 2011 | A1 |
20110268301 | Nielsen et al. | Nov 2011 | A1 |
20110285463 | Walker et al. | Nov 2011 | A1 |
20120001786 | Hisch | Jan 2012 | A1 |
20120007757 | Choe et al. | Jan 2012 | A1 |
20120047535 | Bennett et al. | Feb 2012 | A1 |
20120133411 | Miao et al. | May 2012 | A1 |
20120177201 | Ayling et al. | Jul 2012 | A1 |
20120177226 | Silverstein et al. | Jul 2012 | A1 |
20120188111 | Ledzius et al. | Jul 2012 | A1 |
20120207315 | Kimura et al. | Aug 2012 | A1 |
20120242521 | Kinyua | Sep 2012 | A1 |
20120250893 | Carroll et al. | Oct 2012 | A1 |
20120263090 | Porat et al. | Oct 2012 | A1 |
20120274490 | Kidambi et al. | Nov 2012 | A1 |
20120280726 | Colombo et al. | Nov 2012 | A1 |
20120293348 | Snelgrove | Nov 2012 | A1 |
20120314750 | Mehrabani | Dec 2012 | A1 |
20130095870 | Phillips et al. | Apr 2013 | A1 |
20130106635 | Doi | May 2013 | A1 |
20130129117 | Thomsen et al. | May 2013 | A1 |
20130188808 | Pereira et al. | Jul 2013 | A1 |
20130235484 | Liao et al. | Sep 2013 | A1 |
20130241753 | Nozaki | Sep 2013 | A1 |
20130241755 | Chen et al. | Sep 2013 | A1 |
20140044280 | Jiang | Feb 2014 | A1 |
20140105256 | Hanevich et al. | Apr 2014 | A1 |
20140105273 | Chen et al. | Apr 2014 | A1 |
20140126747 | Huang | May 2014 | A1 |
20140135077 | Leviant et al. | May 2014 | A1 |
20140184332 | Shi et al. | Jul 2014 | A1 |
20140269118 | Taylor et al. | Sep 2014 | A1 |
20140363023 | Li et al. | Dec 2014 | A1 |
20140368364 | Hsu | Dec 2014 | A1 |
20150009079 | Bojer | Jan 2015 | A1 |
20150170663 | Disch et al. | Jun 2015 | A1 |
20150214974 | Currivan | Jul 2015 | A1 |
20150214975 | Gomez et al. | Jul 2015 | A1 |
20150249466 | Elyada | Sep 2015 | A1 |
20150295584 | Das et al. | Oct 2015 | A1 |
20150327174 | Rajagopal et al. | Nov 2015 | A1 |
20150381130 | Das et al. | Dec 2015 | A1 |
20160072465 | Das et al. | Mar 2016 | A1 |
20160080862 | He et al. | Mar 2016 | A1 |
20160080865 | He et al. | Mar 2016 | A1 |
20160139230 | Petrie et al. | May 2016 | A1 |
20160173112 | Das et al. | Jun 2016 | A1 |
20160181988 | Du et al. | Jun 2016 | A1 |
20160286310 | Das et al. | Sep 2016 | A1 |
20160365081 | Satoskar et al. | Dec 2016 | A1 |
20170047895 | Zanbaghi | Feb 2017 | A1 |
20170150257 | Das et al. | May 2017 | A1 |
20170212721 | Satoskar et al. | Jul 2017 | A1 |
20170374459 | Satoskar | Dec 2017 | A1 |
20180046239 | Schneider | Feb 2018 | A1 |
20180048325 | Schneider | Feb 2018 | A1 |
20180098149 | Das | Apr 2018 | A1 |
Number | Date | Country |
---|---|---|
3351788 | Jul 1989 | EP |
0966105 | Dec 1999 | EP |
1244218 | Sep 2002 | EP |
1575164 | Sep 2005 | EP |
1689075 | Aug 2006 | EP |
1753130 | Feb 2007 | EP |
1798852 | Jun 2009 | EP |
2207264 | Jul 2010 | EP |
1599401 | Sep 1981 | GB |
2119189 | Nov 1983 | GB |
2307121 | Jun 1997 | GB |
2507096 | Apr 2014 | GB |
2527637 | Dec 2015 | GB |
2527677 | Oct 2016 | GB |
2537694 | Oct 2016 | GB |
2537697 | Oct 2016 | GB |
2539517 | Dec 2016 | GB |
2552860 | Feb 2018 | GB |
2552867 | Feb 2018 | GB |
2008294803 | Dec 2008 | JP |
WO0054403 | Sep 2000 | WO |
0237686 | May 2002 | WO |
2006018750 | Feb 2006 | WO |
2007005380 | Jan 2007 | WO |
2007136800 | Nov 2007 | WO |
2008067260 | Jun 2008 | WO |
2014113471 | Jul 2014 | WO |
2015160655 | Oct 2015 | WO |
2016040165 | Mar 2016 | WO |
2016040171 | Mar 2016 | WO |
2016040177 | Mar 2016 | WO |
2016160336 | Oct 2016 | WO |
2016202636 | Dec 2016 | WO |
2017116629 | Jul 2017 | WO |
2018031525 | Feb 2018 | WO |
2018031646 | Feb 2018 | WO |
Entry |
---|
Combined Search and Examination Report under Sections 17 and 18(3) of the UKIPO, Application No. GB1620427.3, dated Jun. 1, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3) of the UKIPO, Application No. GB1620428.1, dated Jul. 21, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1700371.6, dated Aug. 1, 2017. |
Thaden, Rainer et al., A Loudspeaker Management System with FIR/IRR Filtering; AES 32nd International Conference, Hillerod, Denmark, Sep. 21-23, 2007; pp. 1-12. |
Thaden, Rainer et al., A Loudspeaker Management System with FIR/IRR Filtering; Slides from a presentation given at the 32nd AES conference “DSP for Loudspeakers” in Hillerod, Denmark in Sep. 2007; http://www.four-audio.com/data/AES32/AES32FourAudio.pdf; 23 pages. |
GB Patent Application No. 1419651.3, Improved Analogue-to-Digital Convertor, filed Nov. 4, 2014, 65 pages. |
Combined Search and Examination Report, GB Application No. GB1506258.1, dated Oct. 21, 2015, 6 pages. |
International Search Report and Written Opinion, International Patent Application No. PCT/US2015/025329, dated Aug. 11, 2015, 9 pages. |
International Search Report and Written Opinion, International Patent Application No. PCT/US2015/048633, dated Dec. 10, 2015, 11 pages. |
International Search Report and Written Opinion, International Patent Application No. PCT/US2015/048591, dated Dec. 10, 2015, 11 pages. |
Combined Search and Examination Report, GB Application No. GB1510578.6, dated Aug. 3, 2015, 3 pages. |
International Search Report and Written Opinion, International Application No. PCT/US2015/056357, dated Jan. 29, 2015, 13 pages. |
Combined Search and Examination Report, GB Application No. GB1514512.1, dated Feb. 11, 2016, 7 pages. |
International Search Report and Written Opinion, International Application No. PCT/US2015/048609, dated Mar. 23, 2016, 23 pages. |
International Search Report and Written Opinion, International Application No. PCT/US2016/022578, dated Jun. 22, 2016, 12 pages. |
Combined Search and Examination Report, GB Application No. GB1600528.2, dated Jul. 7, 2016, 8 pages. |
Combined Search and Examination Report, GB Application No. GB1603628.7, dated Aug. 24, 2016, 6 pages. |
International Search Report and Written Opinion, International Application No. PCT/EP2016/062862, dated Aug. 26, 2016, 14 pages. |
Combined Search and Examination Report, GB Application No. GB1602288.1, dated Aug. 9, 2016, 6 pages. |
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/US2016/065134, dated Mar. 15, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/US2016/040096, dated Mar. 24, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/US2017/014240, dated Apr. 24, 2017. |
Groeneweg, B.P., et al., A Class-AB/D Audio Power Amplifier for Mobile Applications Integrated Into a 2.5G/3G Baseband Processo1016r, IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 57, No. 5, May 2010, pp. 1003-1016. |
Chen, K., et al., A High-PSRR Reconfigurable Class-AB/D Audio. Amplifier Driving a Hands-Free/Receiver. 2-in-1 Loudspeaker, IEEE Journal of Solid-State Circuits, vol. 47, No. 11, Nov. 2012, pp. 2586-2603. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1702540.4, dated Oct. 2, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1702655.0, dated Oct. 24, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1706693.7, dated Oct. 26, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1706690.3, dated Oct. 30, 2017. |
Search Report under Section 17, United Kingdom Intellectual Property Office, Application No. GB1702656.8, dated Oct. 31, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/045861, dated Nov. 14, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/046083, dated Nov. 14, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1708546.5, dated Nov. 22, 2017. |
Combined Search and Examination Report under Sections 17 and 18(3), United Kingdom Intellectual Property Office, Application No. GB1708544.0, dated Nov. 28, 2017. |
International Search Report and Written Opinion of the International Searching Authority, International Patent Application No. PCT/US2017/052439, dated Dec. 14, 2017. |
Chen, Kuo-Hsin, et al., A 106dB PSRR Direct Battery Connected Reconfigurable Class-AB/D Speaker Amplifier for Hands-Free/Receiver 2-in-1 Loudspeaker, Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian, Nov. 14, 2011, pp. 221-224. |
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/US2018/026410, dated Jul. 6, 2018. |
Number | Date | Country | |
---|---|---|---|
20180295442 A1 | Oct 2018 | US |