Berekovic, M. et al.: “An Algorithm-Hardware-System Approach to VLIW Multimedia Processors”, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Kluwer Academic Publishers, Dordrecht, NL, vol. 20, No. 1/02, Oct. 1, 1998, pp. 163-179, XP000786735, ISSN: 0022-5773. |
Byrd, G. T. et al.: “Multithreaded Processor Architectures”, IEEE Spectrum, IEEE, Inc., New York, vol. 32, No. 8, Aug. 1, 1995, pp. 38-46, XP000524855, ISSN: 0018-9235. |
Fillo, M. et al.: “The M-Machine Multicomputer”, Ann Arbor, Nov. 29-Dec. 1, 1995, Los Alamitos, IEEE Comp. Soc. Press, vol. SYMP. 28, Nov. 29, 1995, pp. 146-156, XP000585356, ISBN: 0-8186-7349-4. |
Gulati, M. et al.: “Performance Study of a Multithreaded Superscalar Microprocessor”, Proceedings International Symposium on High-Performance Computer Architecture, 1996, XP000572068. |
Klass, F. et al.: “A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors”, 1998 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, Jun. 11-13, 1998, vol. 34, No. 5, pp. 712-716, XP002156316, IEEE Journal of Solid-State Circuits, May 1999, IEEE, ISSN: 0018-9200. |
Tullsen, D. M. et al.: “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor”, Computer Architecture News, Association for Computing Machinery, New York, vol. 24, No. 2, May 1, 1996, pp. 191-202, XP000592185, ISSN: 0163-5964. |
Tremblay et al., “A Three Dimensional Register File for Superscalar Processors”, Proceedings of the 28th Annual Hawaii International Conference on Systems Sciences, Jan. 1995, pp. 191-201. |
Gruenewald et al.: “Towards Extremely Fast Context Switching in a Block-Multithreaded Processor”, IEEE, Proceedings of the 22nd Euromicro Conference Beyond 2000: Hardware and Software Design Strategies, Prague 1996. S. 592-599. Universität Karlsruhe; Institut für Rechnerentwurf und Fehlertoleranz. 1996. |
Hirata et al.: “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads”, Proceedings of the 19th Annual International Symposium on Computer Architecture, ACM & IEEE-CS, pp. 136-145, May 1992. |
Kavi et al.: “A Decoupled Scheduled Dataflow Multithreaded Architecture”, IEEE 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99) Jun. 23-25, 1999, Fremantle, Australia. |