Patent Application
20250007408
This application claims priority to and the benefit of Chinese Patent Application No. 202310788603.1, filed Jun. 29, 2023, which is incorporated herein by reference in its entirety.
Switching mode power supplies are widely used in power conversion applications because of small volume and high conversion efficiency. In the switching mode power supply, the peak current mode (e.g., constant peak current control mode) is a well-known control scheme. The so-called constant peak current control mode is that: when a current flowing through a power stage of the switching mode power supply reaches a constant reference value, the power switches in the power stage are controlled to change the switching state (e.g., from an ON state to an OFF state or from an OFF state to an ON state), to have the current flowing through the power stage start to decrease.
However, the actual peak value of the current is influenced by the switching frequency and the inductor, which leads to an inaccuracy of the control.
In accordance with an embodiment of the present invention, a switching mode power supply is discussed. The switching mode power supply comprises a power stage, a sample and hold circuit, an amplifying circuit, a comparing circuit, and a logical circuit. The power stage includes a high side power switch and a low side power switch, configured to be periodically turned on and off, to convert an input voltage to an output voltage. The sample and hold circuit is configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal, to generate a sample and hold signal. The amplifying circuit is configured to amplify a difference between the sample and hold signal and a reference voltage, to generate an adjust reference signal. The comparing circuit is configured to compare the adjust reference signal with the sense signal, to generate a comparison signal. The logical circuit is configured to generate a control signal in response to the comparison signal.
In addition, in accordance with an embodiment of the present invention, a controller of a switching mode power supply with a power stage is discussed. The controller comprises: a sample and hold circuit, an amplifying circuit, a comparing circuit, and a logical circuit. The sample and hold circuit is configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal, to generate a sample and hold signal. The amplifying circuit is configured to generate an adjust reference signal in response to a reference voltage and the sample and hold signal. The comparing circuit is configured to compare the adjust reference signal with the sense signal, to generate a comparison signal. The logical circuit is configured to generate a control signal in response to the comparison signal.
Furthermore, in accordance with an embodiment of the present invention, a switching mode power supply is discussed. The switching mode power supply comprises a power stage, a sample and hold circuit, an amplifying circuit, a comparing circuit, and a logical circuit. The power stage includes at least one power switch, configured to be periodically turned on and off, to convert an input voltage to an output voltage. The sample and hold circuit is configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal, to generate a sample and hold signal. The amplifying circuit is configured to amplify a difference between the sample and hold signal and a reference voltage, to generate an adjust reference signal. The comparing circuit is configured to compare the adjust reference signal with the sense signal, to generate a comparison signal. The logical circuit is configured to generate a control signal in response to the comparison signal.
Embodiments of circuits for switching mode power supply are described in detail herein. In the following description, some specific details, such as example circuits for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc.
The following embodiments and aspects are illustrated in conjunction with circuits and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements.
In one embodiment of the present invention, the logical circuit 105 comprises a RS flip flop, having a set terminal S, a reset terminal R and an output terminal Q. The set terminal is configured to receive a clock signal clk. The reset terminal is configured to receive the comparison signal CMP. The logical circuit is configured to generate the control signal ctrl at the output terminal Q in response to the clock signal clk and the comparison signal CMP, to change a switching state of the power switch, e.g., to turn on the power switch or to turn off the power switch. Specifically, the logical circuit 105 is configured to have the current flowing through the power stage increase in response to the clock signal clk and have the current flowing through the power stage decrease in response to the comparison signal CMP. In other embodiments of the present invention, the logical circuit 105 may be set by other signals. For example, when the output voltage VO reaches a certain voltage value, the logical circuit 105 is set, and the current flowing through the power stage 101 starts to increase.
In one embodiment of the present invention, the sample and hold circuit 102 comprises: a sample switch 21 and a sample capacitor 22. The sample switch 21 is configured to be turned on under the control of the control signal ctrl when the current flowing through the power stage 101 is going to decrease from its peak value, so that the peak value of the sense signal CS is delivered to the sample capacitor 22. Then the sample switch 21 is turned off, and the peak current information of the current flowing through the power stage 101 is held at the sample capacitor 22. As shown in
In one embodiment of the present invention, the power stage 101 may comprise a boost circuit, as shown in
During the operation of the switching mode power supply 200, when the low side power switch LS is ON, the input voltage VIN, the inductor L, and the low side power switch LS form a current loop. The inductor current increases, i.e. the current flowing through the power stage 101 increases. When the low side power switch LS is going to be turned off, the current flowing through the power stage 101 reaches its maximum value (i.e., peak current). The short pulse generator 107 detects the falling edge of low side drive signal GLS and turns on the sample switch 21 accordingly. Then the peak current information is delivered to the sample capacitor 22. Due to an influence of the parasitic parameters in actual circuits, there is a time delay at the delivery of the low side drive signal GLS from the drive circuit 106 to the low side power switch LS. During this delay time period, the low side power switch LS is going to be turned off but has not been turned off yet, and the sample switch 21 is turned on to sample and hold the peak current, which is then delivered to the amplifying circuit 103.
In one embodiment of the present invention, the power stage 101 may comprise a buck circuit, as shown in
During the operation of the switching mode power supply 300, when the high side power switch HS is ON, the input voltage VIN is converted to the output voltage VO by way of the inductor L and the high side power switch HS. The inductor current increases, i.e. the current flowing through the power stage 101 increases. When the high side power switch HS is going to be turned off, and the low side power switch LS is going to be turned on, the current flowing through the power stage 101 reaches its maximum value (i.e., peak current). At the sample and hold circuit 102, the sample switch 21 is turned on in response to the rising edge of the low side drive signal GLS, to deliver the peak current information of the current flowing through the power stage 101 to the sample capacitor 22. Due to an influence of the parasitic parameters in actual circuits, there is a time delay at the delivery of the low side drive signal GLS from the drive circuit 106 to the low side power switch LS. During this delay time period, the low side power switch LS is going to be turned on but has not been turned on yet, and the sample switch 21 is turned on to sample and hold the peak current, which is delivered to the amplifying circuit 103.
In the examples of
The embodiments in the
During the operation of the switching mode power supply 400, when the high side power switch HS is ON, the input voltage VIN, the high side power switch HS, and the inductor L form a current loop. The inductor current increases, so does the current flowing through the power stage 101 increases. When the high side power switch HS is going to be turned off, and the low side power switch LS is going to be turned on, the current flowing through the power stage 101 reaches its maximum value (i.e., peak current). At the sample and hold circuit 102, the sample switch 21 is turned on in response to the rising edge of the low side drive signal GLS, to deliver the peak current information of the current flowing through the power stage 101 to the sample capacitor 22. Due to an influence of the parasitic parameters in actual circuits, there is a time delay at the delivery of the low side drive signal GLS from the drive circuit 106 to the low side power switch LS. During this delay time period, the low side power switch LS is going to be turned on but has not been turned on yet, and the sample switch 21 is turned on to sample and hold the peak current, which is delivered to the amplifying circuit 103.
In one embodiment of the present invention, the amplifying circuit 102 comprises: an error amplifier and a compensation loop, to amplify the difference between the sample and hold signal PCS and the reference voltage Vref, to generate the adjust reference signal ADJ. In one embodiment of the present invention, the compensation loop comprises a resistor and a capacitor.
Step 601, periodically turning on and turning off the high side power switch and the low side power switch, to convert an input voltage to an output voltage.
Step 602, sampling and holding a peak value of a sense signal indicative of a current flowing through the power stage, to generate a sample and hold signal.
Step 603, amplifying and integrating a difference between the sample and hold signal and a reference voltage, to generate an adjust reference signal.
Step 604, comparing the adjust reference signal with the sense signal, to generate a comparison signal.
Step 605, generating a control signal in response to the comparison signal.
And
Step 606, generating a high side drive signal and a low side drive signal in response to the control signal, to respectively control the high side power switch and the low side power switch.
In one embodiment of the present invention, the method further comprises: generating a short pulse signal in response to the high side drive signal (e.g., an edge jump of the high side drive signal) or in response to the low side drive signal (e.g., an edge jump of the low side drive signal), to sample and hold the peak value of the sense signal.
In one embodiment of the present invention, the method further comprises: providing a clock signal, wherein the control signal is generated in response to the clock signal and the comparison signal.
Several embodiments of the foregoing switching mode power supply amplify (or amplify and integrate) the difference between the peak current and the reference voltage, to adjust the actual reference voltage. Thus, the accuracy of the control is improved.
It is to be understood in these letters patent that the meaning of “A” is coupled to “B” is that either A and B are connected to each other as described below, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B.
This written description uses examples to disclose the invention, including the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310788603.1 | Jun 2023 | CN | national |
