Patent Application
20130176004
The present disclosure relates generally to electrical circuits, and more particularly but not exclusively to switching mode power supplies.
Peak current mode control is widely used in switching mode power supplies due to fast transient response, over current protection, and etc.
It is an object of the present disclosure to provide a switching mode power supply, which solves the above problems.
In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present disclosure, a switching mode power supply, comprising: an input port configured to receive an input signal; an output port configured to provide an output signal; a power stage having a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to the input port to receive the input signal, the second input terminal being coupled to a driver to receive a driving signal, and based on the input signal and the driving signal, the power stage generates a switching signal at the output terminal; an inductor having a first terminal and a second terminal, the first terminal being coupled to the output terminal of the power stage to receive the switching signal, and the second terminal being coupled to the output port; an output capacitor coupled between the output port and a reference ground; a feedback unit coupled to the output port to generate a feedback signal indicative of the output signal; a voltage comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the feedback unit to receive the feedback signal, the second input terminal is coupled to a voltage reference signal, and wherein based on the feedback signal and the voltage reference signal, the voltage comparator generates a voltage comparison signal at the output terminal; a current comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive a current sense signal indicative of a current flowing through the power stage, the second input terminal is configured to receive a current reference signal, and wherein based on the current sense signal and the current reference signal, the current comparator generates a current comparison signal at the output terminal; a logic unit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the voltage comparator to receive the voltage comparison signal, the second input terminal is coupled to the output terminal of the current comparator to receive the current comparison signal, and wherein based on the voltage comparison signal and the current comparison signal, the logic unit generates a logic signal at the output terminal; and the driver coupled to the logic unit to receive the logic signal, and wherein based on the logic signal, the driver generates the driving signal to control the power stage.
In addition, there has been provided, in accordance with an embodiment of the present disclosure, a switching mode power supply, comprising: an input port configured to receive an input signal; an output port configured to provide an output signal; a power stage having a first input terminal, a second input terminal, and an output terminal, the first input terminal being coupled to the input port to receive the input signal, the second input terminal being coupled to a driver to receive a driving signal, and based on the input signal and the driving signal, the power stage generates a switching signal at the output terminal; an inductor having a first terminal and a second terminal, the first terminal being coupled to the output terminal of the power stage to receive the switching signal, and the second terminal being coupled to the output port; an output capacitor coupled between the output port and a reference ground; a feedback unit coupled to the output port to generate a feedback signal indicative of the output signal; a voltage comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the feedback unit to receive the feedback signal, the second input terminal is coupled to a voltage reference signal, and wherein based on the feedback signal and the voltage reference signal, the voltage comparator generates a voltage comparison signal at the output terminal; an off timer coupled to a logic unit to receive a logic signal, and wherein based on the logic signal, the off timer generates a minimum off time signal; a logic AND circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the voltage comparator to receive the voltage comparison signal, the second input terminal is coupled to the off timer to receive the minimum off time signal, and wherein based on the voltage comparison signal and the minimum off time signal, the logic AND circuit generates a logic AND signal; a current comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive a current sense signal indicative of a current flowing through the power stage, the second input terminal is coupled to a current reference signal, and wherein based on the current sense signal and the current reference signal, the current comparator generates a current comparison signal at the output terminal; the logic unit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the logic AND circuit to receive the logic AND signal, the second input terminal is coupled to the output terminal of the current comparator to receive the current comparison signal, and wherein based on the logic AND signal and the current comparison signal, the logic unit generates the logic signal at the output terminal; and the driver coupled to the logic unit to receive the logic signal, and wherein based on the logic signal, the driver generates the driving signal to control the power stage
Furthermore, there has been provided, in accordance with an embodiment of the present disclosure, a method used in a switching mode power supply, comprising: comparing a feedback signal indicative of an output signal of the switching mode power supply with a voltage reference signal to generate a voltage comparison signal; comparing a current sense signal indicative of a current flowing through a high-side switch of the switching mode power supply with a current reference signal to generate a current comparison signal, the high-side switch being configured to couple a power supply supplying an input signal to a load of the switching mode power supply; using the voltage comparison signal to control the turning on of the high-side switch; and using the current comparison signal to control the turning off of the high-side switch.
The use of the similar reference label in different drawings indicates the same of like components.
In the present disclosure, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the disclosure. Persons of ordinary skill in the art will recognize, however, that the disclosure can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.
In one embodiment, the power stage 101 comprises a high-side switch and a low-side switch coupled in series.
In one embodiment, the logic unit 108 comprises a RS flip-flop.
In one embodiment, the feedback unit 104 comprises a first resistor and a second resistor coupled in series between the output port and the reference ground; and the feedback signal VFB is provided at the conjunction of the first resistor and the second resistor.
When the switching mode power supply 100 is in operation, in one hand, the output signal VO is monitored by the feedback unit 104 to provide the feedback signal VFB indicative of the output signal VO. The feedback signal VFB is then compared to the voltage reference signal Vref by the voltage comparator 105. When the feedback signal VFB goes lower than the voltage reference signal Vref, the voltage comparison signal provided by the voltage comparator 105 turns to be logical high. Accordingly, the output of the logic unit 107 is set, which causes the high-side switch to be turned on, and the low-side switch to be turned off via the driver 108. As a result, both the output signal VO and the current flowing through the high-side switch increase. In the other hand, the current flowing through the high-side switch is sensed to provide the current sense signal Isense indicative of the current flowing through the high-side switch. When the current sense signal Isense goes higher than the current reference signal Iref, the current comparison signal provided by the current comparator 106 turns to be logical high. Accordingly, the output of the logic unit 107 is reset, which causes the high-side switch to be turned off, and the low-side switch to be turned on via the driver 108. As a result, both the output signal and the current flowing through the high-side switch decrease. When the output signal decreases to a certain value, which means the feedback signal VFB becomes lower than the voltage reference signal Vref, the logic unit 107 is set by the voltage comparison signal again, and the high-side switch is turned on, and the low-side switch is turned off via the driver 108. So the switching mode power supply 100 enters a new switching cycle, and operates as discussed above.
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In one embodiment, the current reference signal Iref is adjustable. It may be adjusted to be a lower value to reduce the output voltage ripple when the switching mode power supply 100 enters light load condition. In one embodiment, when the current flowing through the low-side switch goes to zero, a zero-crossing signal is generated, which reduces the current reference signal Iref to a lower value.
In one embodiment, the power stage 201 comprises a high-side switch and a low-side switch coupled in series.
In one embodiment, the logic unit 208 comprises a RS flip-flop.
In one embodiment, the feedback unit 204 comprises a first resistor and a second resistor coupled in series between the output port and the reference ground; and the feedback signal VFB is provided at the conjunction of the first resistor and the second resistor.
In one embodiment, the current reference signal Iref is adjustable. It may be adjusted to be a lower value to reduce the output voltage ripple when the switching mode power supply 200 enters light load condition.
In one embodiment, the second logic unit 92 comprises a RS flip-flop.
In one embodiment, the minimum time preset unit 93 comprises: a comparator 34 having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the time reference signal VR; a reset switch 31, a current source 32, and a capacitor 33 coupled in parallel between the second input terminal of the comparator 34 and the reference ground to provide a voltage across the capacitor to the second input terminal of the comparator, wherein the comparator generates the minimum time preset signal at its output terminal based on the voltage across the capacitor and the time reference signal VR; and wherein the reset switch 31 further having a control terminal coupled to the output of the second logic unit 92 to receive the second logic signal.
When the switching mode power supply 200 is in operation, the current flowing through the high-side switch is sensed to provide the current sense signal Isense indicative of the current flowing through the high-side switch. When the current sense signal Isense is higher than the current reference signal Iref, the current comparison signal provided by the current comparator 206 turns to be logical high. Accordingly, the logic signal Slog provided by the logic unit 207 is reset to be low. In one hand, the short pulse generator 91 generates a short pulse signal in response to the falling edge of the logic signal Slog. Thus, the second logic signal provided by the second logic unit 92, i.e., the minimum off signal Smin is low, which turns off the reset switch 31. Then the capacitor 33 is charged by the current source 32; and the voltage across the capacitor 33 increases. When the voltage across the capacitor 33 increases to be higher than the time reference signal VR, the minimum time preset signal provided by the comparator 34 is high. Accordingly, the second logic signal, i.e., the minimum off time signal Smin is high, which turns on the reset switch 31, and causes the voltage across the capacitor 33 to be reset to zero. Thus, the minimum off time signal Smin is logical low for a preset time period which is determined by the current provided by the current source 31, the capacitance of the capacitor 33, and the time reference signal VR. In the other hand, the low logic signal causes the high-side switch to be turned off, and the low-side switch to be turned on via the driver 208. As a result, both the output signal VO and the current flowing through the high-side switch decrease. The output signal VO is monitored by the feedback unit 204 to provide the feedback signal VFB indicative of the output signal VO. The feedback signal VFB is then compared with the voltage reference signal Vref by the voltage comparator 205. When the output signal VO decreases to a certain value, i.e., the feedback signal VFB is lower than the voltage reference signal Vref, the voltage comparison signal provided by the voltage comparator 205 turns to be logical high. If the minimum off time signal Smin is low at this time point, the logic AND signal provided by the logic AND circuit 210 is low as well. Until the minimum off time signal goes high after it pass the preset time period, the logic AND signal provided by the logic AND circuit 210 turns high. Accordingly, the logic signal Slog provided by the logic unit 207 is high, which causes the high-side switch to be turned on, and the low-side switch to be turned off via the driver 208. As a result, both the output signal VO and the current flowing through the high-side switch increase. When the current flowing through the high-side switch increases to a certain value, that is, the current sense signal becomes higher than the current reference signal, the current comparison signal provided by the current comparator 206 is high. Accordingly, the logic signal Slog provided by the logic unit 207 is reset to be low, which turns off the high-side switch and turns on the low-side switch. And the switching mode power supply enters a new switching cycle, and operates as discussed above.
Several embodiment of the foregoing switching mode power supply provide constant peak current mode control with simple function circuitries compared to conventional technique discussed above. Unlike the conventional technique, several embodiments of the foregoing switching mode power supply adopt a current reference signal to control the ON/OFF status of the high-side switch and the low-side switch, so when the load is light, the switching frequency is reduced, which increases the system efficiency. In addition, several embodiments of the foregoing switching mode power supply adjust the current reference signal to a lower value when the switching mode power supply 100 enters light load condition, which reduces the output voltage ripple.
In one embodiment, the method further comprises generating a minimum off time signal; generating a logic AND signal by making logic AND with the voltage comparison signal and the minimum off time signal; and using the logic AND signal instead of the voltage comparison signal to control turning on of the high-side switch.
In one embodiment, the method further comprises adjusting the current reference signal to a lower value when the switching mode power supply enters light load condition.
While specific embodiments of the present disclosure have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure.
