SWITCHING POWER SUPPLY, CONTROLLER THEREFOR AND IMPROVEMENTS THEREOF

Abstract

A switching power supply comprising: a first power supply stage configured to receive an AC input voltage and to generate a DC output voltage, wherein the DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise, the output voltage is set to a second target level, the second target level being higher than the first target level. A level of power provided to a second power supply stage by the first power supply stage may be monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition. A level of the regulated DC output voltage May be adjusted according to a level of power drawn by the switching power converter in order to maintain a switching frequency of the resonant switching converter at or near its resonant frequency.

Description

BACKGROUND OF THE INVENTION

The present invention relates to the field of switching power supplies.

An off-line power supply receives power from an alternating-current (AC) source and provides a voltage-regulated, direct-current (DC) output that can be used to power a load. An exemplary off-line power supply includes a power factor correction (PFC) stage and a DC-to-DC converter stage. The PFC stage receives the AC input signal, performs rectification and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supply appears as a resistive load to the AC source. The DC-to-DC converter stage receives the rectified output of the PFC stage and generates the voltage-regulated, DC output which can be used to power the load. The rectified output of the PFC stage is typically at higher voltage and is more loosely regulated than the output of the DC-to-DC stage.

It is desired to provide an improved switching power supply.

SUMMARY OF THE INVENTION

The present invention is directed toward a switching power supply and improvements thereof. In accordance with an embodiment, a switching power supply comprises a first power supply stage configured to receive an AC input voltage and to generate a DC output voltage. The DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise, the output voltage is set to a second target level, the second target level being higher than the first target level. A level of power provided to a second power supply stage by the first power supply stage may be monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition. Adjusting the output voltage of the first power supply stage tends to maintain a switching frequency of the second power supply stage at or near a resonant frequency of the second power supply stage.

In accordance with another embodiment, a controller for switching power supply is provided, The controller comprises a power factor correction controller configured to control a power factor correction circuit arrangement to generate a regulated DC output voltage for provision to a resonant switching converter. The resonant switching converter has a resonant switching frequency. A level of the regulated DC output voltage is adjusted according to a level of power provided to the switching power converter in order to maintain a switching frequency of the resonant switching converter at or near the resonant frequency. A detector circuit arrangement is coupled to the power factor correction controller and configured to detect a level of power drawn by the switching power converter in order to adjust the level of the regulated DC output.

These and other embodiments are described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which:

FIG. 1 illustrates a block schematic diagram of a two-stage, off-line power supply in accordance with an embodiment of the present invention;

FIG. 2 illustrates a schematic circuit diagram of a power factor correction stage in accordance with an embodiment of the present invention;

FIG. 3 illustrates a block schematic diagram of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention;

FIG. 4 illustrates a schematic circuit diagram of a DC-to-DC converter stage in accordance with an embodiment of the present invention;

FIG. 5 illustrates a graph showing a relationship between switching frequency and gain for a resonant DC-to-DC converter stage in accordance with an embodiment of the present invention;

FIG. 6 illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention; and

FIG. 7 illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

The present invention is directed towards an improved switching power supply. In accordance with an embodiment, a switching power supply includes at least a first power supply stage, for example, a power factor correction (PFC) stage. The switching power supply may include a second power supply stage, for example, a DC-to-DC converter stage. The first power supply stage is configured to receive an AC voltage as input and to generate a DC output voltage. The second power supply stage receives the DC output voltage of the first power supply stage and generates a further DC output voltage. The DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise the output voltage is set to a second target level. The second target level is higher than the first target level.

The first and second target levels for the DC output voltage of the first power supply stage are dependent upon a level of power drawn by the switching power supply. For example, an error signal is representative of a difference between a current target level for the output voltage of first power supply stage and a monitored level of the output voltage of the first power supply stage. This error signal can be monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition.

The second power supply stage comprises a resonant circuit having a resonant frequency. The first target level causes switching in the second power supply stage to occur at or near the resonant frequency when the level of power reaches a first expected level during the first load condition. The second target level causes switching in the second power supply stage to occur at or near the resonant frequency when the level of power reaches a second expected level during the second load condition. For example, a load coupled to the switching power supply may draw approximately 1000 watts under certain operating conditions (e.g., the first load condition) and may also draw approximately 2000 watts under other operating conditions (e.g., the second load condition). When the load is drawing approximately 1000 watts, the DC output voltage of the first power supply stage is set to a first target level, e.g., 380 volts. To maximize efficiency, the second power supply stage can be configured such that its resonant frequency corresponds to the switching frequency required to regulate its output voltage when the DC output voltage of the first power supply stage is set to 380 volts and the load is drawing 1000 watts. For example, the output voltage of the second power supply stage may be regulated at 12.0 volts DC. However, if the load changes such that it begins drawing 2000 watts, the switching frequency of the second power supply stage will need to change in order to increase the power provided to load while maintaining its output voltage at its regulated level (e.g., at 12.0 volts DC). As a result of this change in switching frequency, efficiency will be reduced. To avoid this, the DC output voltage of the first power supply stage is adjusted (e.g., from 380 volts to 400 volts) when the load changes from 1000 watts to 2000 watts. As a result, the switching frequency can be maintained at or near the resonant frequency which tends to result in improved efficiency.

As described above, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). In this case, the load power is compared to a threshold to determine which of the two levels should be selected. This two level solution is most effective when the load power also tends to mostly have two levels (e.g., 1000 watts and 2000 watts). In accordance with a further embodiment, the DC output voltage of the first power supply stage may have more than two levels. In this case, the load power may be compared to multiple thresholds in order to determine which target level for the DC output voltage should be selected. In another embodiment, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power. In this case, rather than employ one or more thresholds, the target level for the DC output voltage may be continuously adjusted based on monitored changes in the load power thereby increasing efficiency when load power consumption is variable.

FIG. 1 illustrates a block schematic diagram of a two-stage, off-line power supply 100 in accordance with an embodiment of the present invention. As shown in FIG. 1, a first power supply stage 102 has an input coupled to alternating-current (AC) source V_AC. The first power supply stage 102 can be a power factor correction (PFC) stage. The PFC stage 102 performs rectification on the AC input signal and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supply 100 appears as a resistive load to the AC source. The PFC stage 102 generates a loosely regulated output voltage, V_DC.

The output voltage V_DC of the PFC stage 102 can be provided as input to a second power supply stage 104. The second power supply stage 104 can be a DC-to-DC converter stage. Using the input V_DC, the DC-to-DC converter stage 104 generates a voltage-regulated, DC output, V_O, which can be used to power a load. The level of V_DC is preferably at a higher voltage and can be more loosely regulated than the output V_O of the DC-to-DC converter stage 104. A target level of the output, V_DC, of the PFC stage 102 may be, for example, approximately 380 volts DC, while the voltage-regulated output V_O of the DC-to-DC converter stage 104 may be, for example, approximately 12.0 volts DC.

FIG. 2 illustrates a schematic circuit diagram of a power factor correction (PFC) stage 102 in accordance with an embodiment of the present invention. An alternating-current (AC) input source V_AC is coupled across input terminals of a bridge rectifier 110. A rectified input voltage signal Vrect is formed at a first output terminal of the rectifier 110 and is coupled to a first terminal of a main PFC inductor Li and to a first terminal of a resistor R_AC. A second terminal of the inductor Li is coupled to a first terminal of a transistor switch M₁ and to a first terminal of a transistor switch M₂. A second terminal of the switch M₂ is coupled to a first terminal of an output capacitor C_O. A second terminal of the switch M₁ and a second terminal of the capacitor C_O are coupled to a ground node.

A second terminal of the resistor R_AC is coupled to a voltage sensing input of a PFC controller 112. An input voltage sensing signal IAC, which is representative of the instantaneous rectified input voltage Vrect, flows through the resistor R_AC and is received by the controller 112. A second output terminal of the bridge rectifier 110 is coupled to a current sensing input of the controller 112 and to a first terminal of a resistor Rsense. A second terminal of the resistor Rsense is coupled to the ground node. A current sensing signal Isense, which is representative of the instantaneous current input to the power factor correction stage 102, is formed across the resistor Rsense and is received by the controller 112.

A resistor R_A has a first terminal coupled to the output voltage V_DC and a second terminal coupled to a first terminal of resistor R_B. A second terminal of the resistor R_B may be coupled a ground node. The resistors R_A and R_B form a voltage divider. An output voltage sensing signal V_FB is formed at the node between the resistors R_A and R_B. The signal V_FB is representative of the output voltage V_DC.

The PFC controller 112 generates a signal PFC OUT which controls the opening and closing of the switches M₁ and M₂ so as to regulate the intermediate output voltage V_DC while maintaining the input current in phase with the input voltage V_AC. To accomplish this, the controller 112 uses the signal V_FB, as well as the input voltage sensing signal IAC and the input current sensing signal Isense. The switches M₁ and M₂ are generally operated such that when one is opened, the other is closed.

FIG. 3 illustrates a block schematic diagram of the PFC controller 112 in more detail in accordance with an embodiment of the present invention. Within the controller 112, the signal V_FB is coupled to a first input terminal of a transconductance error amplifier GM₁. A second input of the error amplifier GM₂ is coupled to a reference voltage that is representative of a desired level for the output voltage V_DC. This reference voltage may be a fixed value V_REF1 Or V_REF2, depending upon the output level of a comparator CMP₁. An output of the error amplifier GM₁ forms a signal V_EAO, which is an error signal that is representative of a difference between the actual level of the output voltage V_DC and a desired level for the output voltage. As shown in FIG. 3, the error signal V_EAO is formed across a compensation circuit 114.

In an embodiment, the level of the reference voltage V_REF1 corresponds to a target level of approximately 380 volts DC for the PFC output V_DC, while the level of the reference voltage V_REF2 corresponds to a target level of approximately 400 volts DC for the PFC output V_DC. It will be apparent that different levels for the PFC output V_DC can be selected, for example, by changing the values of the reference voltage levels V_REF1 and V_REF2 applied to the error amplifier GM₁.

In an embodiment, the comparator CMP₁ determines whether the PFC circuit 102 is operating under a first load condition or a second load conditions (i.e. loading conditions other than the first load condition) according to the level of the error signal V_EAO. For example, when the level of the error signal V_EAO is less than a voltage reference VREF₃, this indicates the first load condition; in this case, the output of the comparator CMP₁ may be a logic low voltage. If the level of the error signal V_EAO exceeds VREF₃, this indicates the second load condition; in this case, the output of the comparator CMP₁ may be a logic high voltage. In an embodiment, the voltage reference VREF₃ may be set to 1.0 volts.

The output of the comparator CMP₁ determines whether the reference voltage V_REF1 or the reference voltage V_REF2 is applied to the error amplifier GM₁. Thus, the level at which V_DC is regulated by the PFC stage 102 can be different depending upon the loading.

Changing from a first target level for the output V_DC to a second target level, and vice versa, can result in a sudden change in the target level for the output V_DC. In an embodiment, once the output of the comparator CMP₁ is changed, the reference voltage applied to the error amplifier GM₁ is preferably not changed again (i.e. from V_REF1 to V_REF2 and vice versa) at least until the actual output voltage approaches the new target level. This can be accomplished, for example, by avoiding changing the target level again for a predetermined time period after a change or by avoiding changing the target level again until the error signal falls below a threshold after a change. Such a delay can help to prevent unstable operation. Such a delay can be implemented, for example, by a timer circuit within the comparator CMP₁ which prevents its output from changing for a predetermined time after each change or by requiring V_EAO to fall below or rise above VREF₃ by a hysteresis margin after each change in output of the comparator CMP₁.

As described above, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the reference voltage applied to the second input of the error amplifier GM₁ can have multiple levels or can be a variable value dependent upon, for example, the level of the error signal V_EAO. Employing multiple levels can be accomplished, for example, by replacing the comparator CMP₁ with an analog-to-digital converter that is configured to convert the level of V_EAO to a digital value where the digital value is used to select the reference voltage level from among a plurality of reference voltage levels for coupling to the second input of the error amplifier GM₁.

A gain modulation block 116 receives the error signal V_EAO as well as the signal IAC for generating a modulated error signal Imul. The gain modulation block 116 can, optionally, also receive the signal V_RMS. The signal V_RMS is representative of the level of the AC line voltage and can be used to inhibit switching in the PFC stage 102, by gradually pulling down the level of the signal Imul, for example, if the AC line voltage is too low for an extended period (i.e. under “brown out” conditions). The signal V_RMS can be generated, for example, by applying the signal IAC, which represents an instantaneous value of the input voltage V_AC, to a filter that generates signal V_RMS by averaging value of IAC over at least one cycle of the AC input voltage V_AC.

The output of the gain modulation block 116 is coupled to a first input terminal of a transconductance amplifier GM₂ and to a first terminal of a resistor Rmul₁. A second terminal of the resistor Rmul₁ is coupled to receive the signal Isense. A first terminal of a resistor Rmul₂ is coupled to a second input terminal of the amplifier GM₂. A second terminal of a resistor Rmul₂ is coupled to a ground node.

An output of the amplifier GM₂ is coupled to a compensation circuit 118. A signal I_EAO is formed at the output of the amplifier GM₂. The signal I_EAO is representative of the error signal V_EAO as well as the input voltage and input current to the PFC stage. The signal I_EAO is coupled to a first input of a comparator CMP₂. An output of a ramp generator 120 forms a ramp signal PFC RAMP which is coupled to a second terminal of the comparator CMP₂. An RTCT node of the ramp generator 120 is coupled to an RTCT timing network 122 which sets the frequency of the ramp signal.

The signal I_EAO functions to implement a first feedback loop which equalizes the signals IAC and ISENSE in order to maintain the input voltage Vrect in phase with the input current IAC. This first feedback loop includes the signals IAC and ISENSE, as well as the gain modulation block 116, resistors Rmul₁ and Rmul₂, and transconductance amplifier GM₂. As a result, the PFC converter appears to the AC input source as a resistive (i.e. non-reactive) load. The signal I_EAO also functions to implement a second feedback loop which regulates the output voltage V_DC at its desired level. This second feedback loop includes the signals V_FB and V_REF1 (or V_REF2) as well as the gain modulation block 116 and transconductance amplifiers GM₁ and GM₂

An output of the comparator CMP₂ is coupled to driver/logic block 124 which includes driver and logic circuit elements for forming the PFC switching signal PFC OUT. The signal PFC OUT controls the transistor switches M₁ and M₂ of the PFC stage 102 (FIGS. 1-2) of the switching power supply 100 (FIG. 1). It will be apparent that the PFC function and control of switching in the PFC stage 102 as shown in FIG. 3 can be accomplished in other ways and by employing different circuit arrangements.

FIG. 4 illustrates a schematic diagram of a resonant switching converter 106 in accordance with an embodiment of the present invention. The resonant switching converter 106 may be, for example, included in the DC-to-DC converter 104 of FIG. 1. Referring to FIG. 4, the converter 106 includes a half-bridge switching inverter that includes a pair of series-connected transistor switches M₃ and M₄. A power source, such as the output V_DC generated by the PFC stage 102 (FIG. 1), is coupled to a first terminal of the transistor switch M₃. A second terminal of the transistor switch M₃ is coupled to a first terminal of a transistor switch M₄ to form an intermediate node. The second terminal of the transistor switch M₄ is coupled to a ground node. Control terminals of each of the transistor switches M₃ and M₄ are coupled to a controller 108. The controller 108 controls opening and closing of the pair of transistor switches M₃ and M₄. The switches M₃ and M₄ are generally operated such that when one is opened, the other is closed. When the switch M₃ is closed and the switch M₄ is open, the intermediate node is coupled to V_DC. This raises a voltage, VIN, at the intermediate node. When the switch M₃ is open and the switch M₄ is closed, the intermediate node is coupled to ground. This lowers the voltage, VIN, at the intermediate node.

Energy storage elements are coupled to the intermediate node. Particularly, as shown in FIG. 4, a first terminal of an inductor L_r is coupled to the intermediate node. A second terminal of the inductor L_r is coupled to a first terminal of a capacitor C_r. The energy storage elements, L_r and C_r, form a series resonant tank. The resonant tank is charged with energy by raising and lowering the voltage VIN at the intermediate node. A second terminal of the capacitor C_r is coupled to a first terminal of a primary winding of a transformer T₁. A second terminal of the primary winding of the transformer T₁ is coupled to a ground node. A first terminal of a secondary winding of the transformer T₁ is coupled to a first terminal of a transistor switch M₅. A second terminal of the secondary winding of the transformer T₁ is coupled to a first terminal of a transistor switch M₆. A second terminal of the transistor switch M₅ and a second terminal of the transistor switch M₆ are coupled to a ground node. Control terminals of each of the transistor switches M₅ and M₆ are coupled to the controller 108. The controller 108 controls opening and closing of the transistor switches M₅ and M₆ synchronously with transistor switches M₃ and M₄.

A center tap of the secondary winding of the transformer T₁ is coupled to a first terminal of a capacitor C₁. A second terminal of the capacitor C₁ is coupled to a ground node. An output voltage, V_O, is formed across the capacitor C₁. A load 110 may be coupled across the capacitor C₁ to receive the output voltage V_O. The output voltage V_O, or a voltage that is representative of the output voltage, is fed back to the controller 128 via a feedback path 130.

Adjusting the switching frequency of the transistor switches M₃, M₄, M₅ and M₆ adjusts impedance of the resonant tank and, therefore, adjusts the amount of power delivered to the load 128. More particularly, decreasing the switching frequency tends to increase the power delivered to the load 128. Increasing the switching frequency tends to reduce the power delivered to the load 128. By monitoring the level of the output voltage V_O via a feedback path 130, the controller 108 can adjust the switching frequency to maintain the output voltage V_O constant despite changes in the power requirements of the load 128 and despite changes in the level of the input V_DC. This is referred to as frequency modulation or FM modulation. In an embodiment, the output voltage V_O is regulated at a level of 12.0 volts DC, however, it will be apparent that some other output voltage level can be selected. While FIG. 4 shows a half-bridge switching inverter, it can be replaced with a full-bridge switching inverter or with some other DC-to-DC converter topology.

FIG. 5 illustrates a graph showing a relationship between switching frequency and gain for a resonant DC-to-DC converter stage in accordance with an embodiment of the present invention. The resonant frequency for the DC-to-DC converter is shown in FIG. 5 as Fr. The value of Fr is dependent upon the values of the main resonant components of the resonant DC-to-DC converter which include the values of the inductor L_r, the capacitor C_r and the inductance of the primary winding of the transformer T₁ (FIG. 4). The gain of the converter is related to a ratio of the converter input voltage (i.e. the PFC output V_DC) and the converter output voltage. The maximum gain as shown in FIG. 5 is 1.0. FIG. 5 also shows a series of gain vs. frequency curves, each of which depicts a particular load level. Maximum efficiency for the resonant DC-to-DC converter occurs when the switching frequency is at or near the resonant frequency and, more particularly, when the switching frequency is in the range of Fr to 1.2 times Fr and when the switching duty cycle is approximately 50%. It is therefore desired to maintain the operating point within the range of Fr to 1.2 times Fr and duty cycle is approximately 50%. As load power increases, current levels within the resonant converter increase as do parasitic losses due to increased current. Accordingly, the gain vs. frequency curves show that gain falls off with increasing switch frequency more dramatically as the load increases. It is therefore desirable to increase converter input voltage at higher load power levels in order to maintain maximum efficiency.

FIG. 6 illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention. FIG. 6 shares many of the same components and functions as are depicted in FIG. 3 discussed above. Therefore, only differences between FIGS. 3 and 6 are discussed here. Specifically, in FIG. 6, the reference voltage V_REF2 is omitted while the reference voltage V_REF1 remains coupled to the second input of the transconductance amplifier GM₁. Rather than select between the reference voltages V_REF1 and V_REF2 as in FIG. 3, the output of the comparator CMP₁ selectively activates a current source I_ADD. The current source I_ADD may have a value of approximately 3 uA (microamps). Activating the current source I_ADD has the effect of increasing the target level for the PFC output V_DC. In an embodiment, the level of the reference voltage V_REF1 corresponds to a first target level (e.g., 380 volts DC) for the PFC output V_DC, while activating the current source I_ADD corresponds to a second target level (e.g. 400 volts DC) for the PFC output V_DC. As described above in connection with FIG. 6, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the current source I_ADD can be a variable value dependent upon, for example, the level of the error signal V_EAO. In this case, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power.

FIG. 7 illustrates a block schematic diagram of an alternative embodiment of a controller for a power factor correction stage and detector in accordance with an embodiment of the present invention. FIG. 7 shares many of the same components and functions as are depicted in FIG. 3 discussed above. Therefore, only differences between FIGS. 3 and 7 are discussed here. Specifically, in FIG. 7, the reference voltage V_REF2 is omitted while the reference voltage V_REF1 remains coupled to the second input of the transconductance amplifier GM₁. Rather than select between the reference voltages V_REF1 and V_REF2 as in FIG. 3, the output of the comparator CMP₁ selectively adds a resistance R_ADD in series with the resistor Rmul₁ by activating a switch SW₁. Activating the switch SW₁ has the effect of increasing the target level for the PFC output V_DC. In an embodiment, the level of the reference voltage V_REF1 corresponds to a first target level (e.g., 380 volts DC) for the PFC output V_DC, while activating the switch SW₁ corresponds to a second target level (e.g. 400 volts DC) for the PFC output V_DC. As described above in connection with FIG. 7, the DC output voltage of the first power supply stage has two levels, the first target level (e.g., 380 volts) and the second target level (e.g., 400 volts). Alternatively, the resistance R_ADD can have a variable value dependent upon, for example, the level of the error signal V_EAO. In this case, the target level for the DC output voltage may be adjusted over a continuous range of target levels based on the detected load power.

The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the embodiments disclosed. Accordingly, the scope of the present invention is defined by the appended claims and any amendments thereto.

Claims

1. A switching power supply comprising: a first power supply stage configured to receive an AC input voltage and to generate a DC output voltage, wherein the DC output voltage of the first power supply stage is set to a first target level during a first load condition and, otherwise, the output voltage is set to a second target level, the second target level being higher than the first target level.

2. The switching power supply according to claim 1, wherein the first power supply stage performs power factor correction and further comprising a second power supply stage configured to receive the DC output voltage from the first power supply stage and the second power supply stage being configured to generate a DC output voltage for the second power supply stage.

3. The switching power supply according to claim 2, wherein a level of power provided to the second power supply stage by the first power supply stage is monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition.

4. The switching power supply according to claim 3, wherein when the level of power provided to the second power supply stage by the first power supply stage is below a threshold, the switching power supply operates in accordance with the first load condition.

5. The switching power supply according to claim 4, wherein when the level of power provided to the second power supply stage by the first power supply stage exceeds the threshold, the switching power supply operates in accordance with the second load condition.

6. The switching power supply according to claim 5, wherein the threshold is adjusted in accordance with hysteresis.

7. The switching power supply according to claim 3, wherein the second power supply stage comprises a resonant circuit having a resonant frequency and wherein the first target level causes switching in the second power supply stage to occur at the resonant frequency when the level of power reaches a first expected level during the first load condition.

8. The switching power supply according to claim 7, wherein the second target level causes switching in the second power supply stage to occur at the resonant frequency when the level of power reaches a second expected level during the second load condition.

9. The switching power supply according to claim 8, wherein the second expected level is approximately twice the first expected level.

10. The switching power supply according to claim 1, wherein the first target level is approximately 380 volts DC.

11. The switching power supply according to claim 1, wherein the second target level is approximately 400 volts DC.

12. The switching power supply according to claim 1, wherein the DC output voltage of the first power supply stage is regulated using a negative feedback loop and wherein an error signal representative of a difference between a current target level for the output voltage of first power supply stage and a monitored level of the output voltage of first power supply stage is used to control switching in the first power supply stage.

13. The switching power supply according to claim 4, wherein the error signal is monitored to determine whether the switching power supply is operating in accordance with the first load condition or the second load condition.

14. A controller for switching power supply, the controller comprising: a power factor correction controller configured to control a power factor correction circuit arrangement to generate a regulated DC output voltage for provision to a resonant switching converter having a resonant switching frequency, wherein a level of the regulated DC output voltage is adjusted according to a level of power provided to the switching power converter in order to maintain a switching frequency of the resonant switching converter at or near the resonant frequency; anda detector circuit arrangement coupled to the power factor correction controller and configured to detect a level of power drawn by the switching power converter in order to adjust the level of the regulated DC output.

15. The controller according to claim 14, wherein the power factor correction circuit arrangement is configured to generate an error signal wherein the error signal is representative of a difference between a current target level for the regulated DC output voltage and a monitored level of the DC output voltage.

16. The controller according to claim 15, wherein the detector circuit arrangement monitors the error signal for detecting the level of power drawn by the switching power converter.

17. The controller according to claim 16, wherein the detector circuit arrangement comprises a hysteresis comparator configured to compare the error signal to a reference voltage level.

18. The controller according to claim 16, wherein the error signal is generated by a transconductance amplifier and is used to modulate switching in the power factor correction converter and further wherein the level of the regulated DC output voltage is adjusted by adjusting a reference voltage applied to the transconductance amplifier.

19. The controller according to claim 16, wherein the error signal is generated by a transconductance amplifier and is used to modulate switching in the power factor correction converter and further wherein the level of the regulated DC output voltage is adjusted by activating a current source coupled to the transconductance amplifier.

20. The controller according to claim 16, wherein an input current supplied to the power factor correction converter is monitored to modulate switching in the power factor correction converter and further wherein the level of the regulated DC output voltage is adjusted by adjusting a resistance value used to monitor the input current.

21. The controller according to claim 14, further comprising a first power supply stage configured to generate the regulated DC output voltage and further comprising a second power supply stage configured to receive the DC output voltage from the first power supply stage and the second power supply stage being configured to generate a DC output voltage for the second power supply stage.