Switching power supply gate driver

Abstract

One configuration of the present disclosure is directed to a switch driver circuit. The switch driver circuit can include an input to receive a control signal; an output to control a state of an switch in accordance with the control signal; and a set of parallel switches. The set of parallel switches in the switch driver circuit includes a P-type field effect transistor in parallel with an N-type field effect transistor. During operation, via variations in the control signal, the control signal selectively and electrically couples a voltage source signal to the output of the switch driver circuit to control the state of the switch.

Description

BACKGROUND

A conventional DC-DC converter is a synchronous buck converter, which typically has minimal components, and therefore is widely used in power supply applications. In an example application, the input voltage to a buck converter may be 12V_DC. An output voltage produced by the power supply may be 5.0V_DC, 3.3 V_DC, or lower.

A typical configuration of a power supply such as a so-called synchronous buck converter includes an inductor, a high side switch, and a low side switch. A controller associated with the buck converter repeatedly pulses the high side switch (e.g., control switch) ON to convey power from a power source through the inductor to a dynamic load. Via a switch driver circuit, the controller repeatedly pulses the low side switch (e.g., synchronous switch) ON to provide a low impedance path from a node of the inductor to ground in order to control an output of the buck converter. Thus, the energy stored in the inductor increases during a time when the high side switch is ON and decreases during a time when the low side switch is ON. During switching operation, the inductor transfers energy from the input to the output of the converter.

FIG. 1 is an example diagram illustrating a conventional switch driver circuit 100. Conventional switch driver circuit 100 includes a series combination of a P-type field effect transistor 110-1 and an N-type field effect transistor 110-2 to drive a respective gate of a high side switch (e.g., an external switch to the switch driver circuit 100) in a power supply circuit such as a buck converter. The pull-up control signal controls a state of field effect transistor 110-1; the pull-down control signal controls a state of field effect transistor 110-2.

Activation of the P-type field effect transistor 110-1 in the driver circuit, while the N-type field effect transistor is OFF, causes the switch driver circuit 100 to drive (based on a low resistance path between the drain and source of P-type field effect transistor 110-1) a gate of the external switch to an appropriate voltage (namely, V_DRIVE) to activate the external switch to an ON state. Conversely, activation of the N-type field effect transistor 110-2 while the P-type field effect transistor 110-1 is OFF causes the switch driver circuit 100 to drive a respective gate of the external switch circuitry to a low voltage to set the switch to an OFF state. Accordingly, the conventional switch driver circuit 100 is able to activate and deactivate a respective switch in a switching power supply.

BRIEF DESCRIPTION

Conventional applications such as those as discussed above can suffer from a number of deficiencies. For example, to accommodate a range of possible voltages values for V_DRIVE that can be used to power the driver, conventional switch driver circuits typically require implementing a relatively large P-type field effect transistor 110-1 to provide appropriate drive capability. Use of a large P-type field effect transistor is undesirable because such a device consumes a large amount of power and takes up significant space in a respective driver circuit.

Embodiments herein deviate with respect to conventional applications. For example, one embodiment herein is directed to a unique way of implementing a pair of switches to enhance performance of a switch driver circuit.

More specifically, one embodiment herein is directed to a switch driver circuit. The switch driver circuit includes an input to receive a control signal; an output to control a state of an external switch in accordance with the control signal; and at least a set of parallel switches. In one embodiment, the set of parallel switches in the switch driver circuit includes a P-type field effect transistor disposed in parallel with an N-type field effect transistor. During operation, via the set of parallel switches, the control signal selectively and electrically causes coupling of a voltage source signal to the output of the switch driver circuit to control the state of the external switch. Electrically coupling of the voltage source signal to the output via the set of parallel switches activates the external switch to an ON state via conveyance of the voltage source signal to the external switch.

In accordance with further embodiments, the control signal to control the set of parallel switches changes between at least a first setting (e.g., first voltage level, edge, etc.) and a second setting (e.g., a second voltage level, edge, etc.). For example, the first setting of the control signal causes simultaneous activation of both the P-type field effect transistor and the N-type field effect transistor to electrically couple the voltage source signal to the output to activate the external switch. In other words, in accordance with one embodiment, both switches in the set of parallel switches are activated at the same time to couple the voltage source signal to the output to drive the external switch. The second setting (e.g., first voltage level, edge, etc.) of the control signal causes simultaneous deactivation of both the P-type field effect transistor and the N-type field effect transistor to electrically disconnect the voltage source signal from the output.

In one embodiment, in this latter case during which the set of parallel switches is deactivated, another switch circuit in the switch driver couples the output to a second voltage source signal, which causes deactivation of the external switch (e.g., high side switch, low side switch, synchronous switch, control switch, etc.) in the power supply.

In yet another embodiment, the switch driver circuit as discussed herein can include a voltage booster circuit to generate a boosted voltage signal. The voltage booster circuit outputs the boosted voltage signal at an appropriate time to drive and activate the N-type field effect transistor to an ON state.

The boosted voltage signal generated by the voltage booster circuit to drive the N-type field effect transistor to the ON state can be substantially greater in magnitude than a corresponding voltage level applied to the P-type field effect transistor to deactivate the P-type field effect transistor. For example, the switch driver circuit can be configured to drive the P-type field effect transistor at different times with voltage levels in a first pair of voltage levels (e.g., V₁₁ and V₁₂) to switch the P-type field effect transistor between ON and OFF states. The switch driver circuit can be configured to drive the N-type field effect transistor at different times with voltages in a second pair of voltage levels (e.g., V₂₁ and V₂₂) to switch the N-type field effect transistor between ON and OFF states. In one embodiment, at least one magnitude of a voltage in the second pair of voltage levels is different than a magnitude of a voltage in the first pair of voltage levels.

As discussed further herein, a polarity of the voltage levels to control the P-type field effect transistor between ON and OFF states can be opposite to a polarity of the voltage levels to control the N-type field effect transistor between ON and OFF states. For example, V₁₁ can be greater in magnitude than V₁₂; V₂₂ can be greater in magnitude than V₂₁. Simultaneous activation of both the P-type and N-type field effect transistors can include simultaneously driving a gate of the P-type field effect transistor with V₁₂ while driving a gate of the N-type field effect transistor to V₂₂. Simultaneous deactivation of both the P-type and N-type field effect transistors can include simultaneously driving a gate of the P-type field effect transistor with V₁₁ while driving a gate of the N-type field effect transistor to V₂₁.

As mentioned above, because V₂₂ may be a boosted voltage value with respect to voltage V₁₁, note that a magnitude of a voltage level such as V₂₂ to activate the N-type field effect transistor to an ON state can be substantially greater in magnitude (because it is boosted) than a voltage level such as V₁₁ applied to the P-type field effect transistor to deactivate the P-type field effect transistor to an OFF state.

Embodiments herein are useful over conventional techniques. For example, inclusion of the N-type field effect transistor in a switch driver circuit as discussed herein reduces a size requirement of a functionality equivalent P-type field effect transistor that is needed to couple the voltage source signal to the output. More specifically, use of one or more parallel P-type field effect transistors can be used to drive an external switch to an ON state in a conventional application. However, to provide enhanced and substantially equivalent functionality as the parallel P-type and N-type field effect transistors as discussed herein, the single or parallel P-type field effect transistors would require a substantially larger circuit as previously discussed. Thus, use of the set of parallel switches (e.g., include one or more N-type switches in parallel with one or more P-type switches) as discussed herein, namely, inclusion of the parallel combination of the N-type field effect transistor to complement the P-type field effect transistor, reduces a size requirement of the switch driver circuit. In one embodiment, the N-type field effect transistor in the set of parallel switches provides a substantially equivalent R_DS as a corresponding substantially larger P-type field effect transistor when in an ON state.

These and other more specific embodiments are disclosed in more detail below.

It is to be understood that the systems, methods, apparatus, etc., as discussed herein can be embodied strictly as hardware, as a hybrid of software and hardware, or as software alone such as within a processor, or within an operating system or a within a software application.

As mentioned, one use of the unique switch driver circuit as discussed herein is a switching power supply in which the switch driver circuit drives a respective external switch such as a high side switch (e.g., a control switch) and/or a low side switch (e.g., a synchronous switch) to generate an output voltage. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well.

Additionally, note that although each of the different features, techniques, configurations, etc., herein may be discussed in different places of this disclosure, it is intended, where suitable, that each of the concepts can optionally be executed independently of each other or in combination with each other in a common embodiment. Accordingly, the one or more present inventions as described herein can be embodied and viewed in many different ways.

Also, note that this preliminary discussion of embodiments herein purposefully does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention(s). Instead, this brief description only presents general embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives (permutations) of the invention(s), the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments herein, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, with emphasis instead being placed upon illustrating the embodiments, principles, concepts, etc.

FIG. 1 is an example diagram of a conventional switch driver circuit.

FIG. 2 is an example diagram of a switch driver circuit including a parallel set of switches according to embodiments herein.

FIG. 3 is an example diagram of a switch driver circuit including a parallel set of switches and a voltage booster circuit according to embodiments herein.

FIG. 4 is an example diagram of a voltage booster circuit to boost a corresponding drive voltage according to embodiments herein.

FIG. 5 is an example diagram illustrating variation in a drain to source resistance for a range of possible Vcc input voltages according to embodiments herein.

FIG. 6 is an example diagram illustrating a power supply circuit including one or more drivers according to embodiments herein.

FIG. 7 is a flowchart illustrating an example method according to embodiments herein.

FIG. 8 is an example diagram illustrating use of an N-type switch device in a switch driver circuit including a voltage booster circuit according to embodiments herein.

DETAILED DESCRIPTION

One embodiment herein is directed to a switch driver circuit. The switch driver circuit can include an input to receive a control signal; an output to control a state of an external switch circuit in accordance with the control signal; and a set of parallel switches. The set of parallel switches in the switch driver circuit includes one or more P-type field effect transistors in parallel with one or more N-type field effect transistors. During operation, the control signal causes selective and electrical coupling of a voltage source signal to the output of the switch driver circuit to control the state of the external switch.

Now, more specifically, FIG. 2 is an example diagram of a switch driver circuit including a parallel set of switches according to embodiments herein.

The switch driver circuit 200 includes an input 240 to receive a control signal 220-1; an output 242 to control a state of a resource such as switch circuit 250 (e.g., an external switch with respect to the driver circuit) in accordance with the control signal 220-1; and a set of parallel switches 230 (e.g., P-type field effect transistor and an N-type field effect transistor).

By way of a non-limiting example, as shown, the set of parallel switches 230 in the switch driver circuit can include a P-type switch disposed in parallel with an N-type switch. In one embodiment, the P-type switch 230-P can be a P-type field effect transistor. The N-type switch 230-N can be an N-type field effect transistor.

In general, during operation, via the set of parallel switches 230, the control signal 220-1 selectively and electrically controls coupling of a voltage source signal 210 to the output of the switch driver circuit 200 to control the state of the switch circuit 250. For example, the N-type switch 230-N and P-type switch 230-P can be activated at substantially the same time to provide a low impedance path between the voltage source signal 210 and the output 242.

At a time when the control circuit 225 initiates activation of the set of parallel switches 230, the control circuit 225 initiates deactivation of the N-type switch 235-N so that the voltage source signal 210 is not shorted to the voltage of the switch node. FIG. 6 illustrates more details of a power supply circuit and respective switch node to which the source of N-type field effect transistor 235 (i.e., a switch) is connected.

Referring again to FIG. 1, electrically coupling of the voltage source signal 210 to the output 242 via the set of parallel switches 230 activates the switch circuit 250 to an ON state via conveyance of the voltage source signal 210.

In one embodiment, the switch driver circuit 200 is fabricated as a semiconductor chip or other suitable type of circuit; switch circuit 250 is an external switch such as a high side switch with respect to the switch driver circuit 200.

In accordance with further embodiments, the control signal 220 changes between at least a first setting (e.g., first voltage level, edge, etc.) and a second setting (e.g., a second voltage level, edge, etc.).

As mentioned above, the first setting of the control signal 220 causes the control circuit 225 to simultaneously activate both the P-type switch 230-P and the N-type switches 230-N to electrically couple the voltage source signal 210 to the output 242 to activate the switch circuit 250 (e.g., turn the switch to an ON state). In other words, during one setting, the control circuit 225 substantially activates both switches in the set of parallel switches 230 to couple the voltage source signal 210 to the output 242 to drive the switch circuit 250. Also, as mentioned, while the control circuit 225 initiates activation of the set of parallel switches 230, the control circuit 225 initiates deactivation of the N-type switch 235.

The second setting of the received control signal 240 causes the simultaneous deactivation of both the P-type switch 230-P and the N-type switch 230-N to electrically disconnect the voltage source signal 210 from the output 242. In one embodiment, in this latter case, while the set of parallel switches is deactivated, the control circuit generates a respective control signal to activate the N-type field effect transistor 235 in the switch driver 200. At such time, the N-type field effect transistor 235 couples a second voltage source signal such as a switch node to the output 242, which causes deactivation of the switch circuit 250.

Accordingly, detection of switching of the control signal 220 from one state to another causes the control circuit 225 to alternately couple the voltage source signal 210 and switch node voltage to the output 242 to produce control signal 222.

Note that the use of the combination of the N-type switch 230-N and the P-type switch 230-P is shown by way of non-limiting example only and that additional embodiments herein include use of only the N-type switch 230-N to provide selective connectivity to the voltage source 210.

FIG. 3 is an example diagram of a switch driver circuit 300 including a set of parallel switches and a voltage booster circuit according to embodiments herein.

As shown, the switch driver circuit 300 can include a voltage booster circuit 310 to generate a boosted voltage signal. As discussed in more detail below, the voltage booster circuit 310 outputs the boosted voltage signal at appropriate times to drive and activate the N-type field effect transistor 230-N to an ON state. Thus, the voltage levels to drive the N-type switch 230-N can be different than the voltage levels to drive the P-type switch 230-P.

In one embodiment, the boosted voltage signal (e.g., VBOOT or voltage source signal 210 plus an offset value) generated by the voltage booster circuit 310 to drive the N-type switch 230-N to the ON state can be substantially greater in magnitude than a corresponding voltage level applied to the P-type switch 230-P to deactivate the P-type switch 230-P.

More specifically, the switch driver circuit 300 can be configured to drive the P-type switch 230-P at different times with voltage levels in a first pair of voltage levels (e.g., V₁₁ and V₁₂) to switch the P-type switch between respective OFF and ON states. That is, input signal INB_PULL_UP can be set to V₁₁ or V₁₂ by the control circuit 225 depending on whether the P-type switch 230-P is to be activated or deactivated.

Assume that setting INB_PULL_UP to a magnitude of V₁₁ (e.g., a magnitude of VBOOT or a voltage such as Vcc minus a diode voltage drop) to the P-type switch 230-P causes deactivation of the P-type switch 230-P. Assume that setting INB_PULL_UP to a magnitude of V₁₂ (e.g., a magnitude of ground GND or the switch node SW) to the P-type switch 230-P causes activation of the P-type switch 230-P.

Additionally, the switch driver circuit 300 can be configured to drive the N-type field effect transistor 230-N at different times with voltage levels in a second pair of voltage levels (e.g., V₂₁ and V₂₂) to switch the N-type switch 230-N between respective OFF and ON states. That is, signal PUMP_DRV_SF produced by the voltage booster circuit 310 can be set to V₂₁ or V₂₂ by the control circuit 225 depending on whether the N-type switch 230-N is to be activated or deactivated.

Assume that setting PUMP_DRV_SF signal in the voltage booster circuit 310 to a magnitude of V₂₁ (e.g., a magnitude of the switch node SW) and applying this voltage to the N-type switch 230-N causes deactivation of the N-type switch 230-N. Assume that setting PUMP_DRV_SF signal to a magnitude of V₂₂ (e.g., a magnitude of VBOOT+OFFSET) to the N-type switch 230-N causes activation of the N-type switch 230-N.

As mentioned, in one embodiment, the voltage booster circuit 310 boosts the voltage, VBOOT (e.g., Vcc minus a diode voltage drop) by an OFFSET voltage (e.g., 5 volts or other suitable voltage) to produce VBOOT+OFFSET to drive the N-type switch to an off state. In one embodiment, the boosted voltage is substantially greater in magnitude than the magnitude of VBOOT.

Applying the increased voltage or boosted voltage, VBOOT+OFFSET, as opposed to merely driving the N-type switch 230-N with a magnitude of VBOOT to turn it ON decreases the RDS (i.e., drain to source resistance) of the N-type switch 230-N when it is in an ON state. Lowering the RDS of the set of parallel switches 230 (using the boosted voltage) when they are in an ON state increases a respective rate at which the switch driver circuit 300 activates (e.g., turns it ON) the switch circuitry 250.

Thus, in one embodiment, at least one magnitude of a voltage in the second pair (e.g., V₂₁ and V₂₂) is different than a magnitude of a voltage in the first pair of voltage levels (e.g., V₁₁ and V₁₂). That is, V₁₁ can be approximately VBOOT; V₂₂ can be approximately VBOOT+VOFFSET. V₁₂ can be approximately the voltage of switch node 620; V₂₁ can be approximately the voltage of switch node 620.

A polarity of the voltage levels to control the P-type switch between ON and OFF states can be opposite to a polarity of the voltage levels to control the N-type switch between ON and OFF states.

For example, as mentioned, V₁₁ can be greater in magnitude than V₁₂; V₂₁ can be lower in magnitude than V₂₂. Simultaneous activation of both the P-type and N-type switches 230 occurs by simultaneously driving a gate of the P-type switch 230-P with V₁₂ (e.g., voltage of switch node 620) while driving a gate of the N-type switch 230-N to V₂₂ (e.g., (e.g., VBOOT+VOFFSET). This activates both switches to electrically connect the output 242 to the voltage VBOOT through resistor R10.

Conversely, simultaneous deactivation of both the P-type switch 230-P and N-type switch 230-N occurs by simultaneously driving a gate of the P-type field effect 230-P transistor with V₁₁ while driving a gate of the N-type switch 230-N to V₂₁.

As mentioned above, note that a magnitude of a voltage level such as V₂₂ to activate the N-type switch 230-N to an ON state can be substantially greater in magnitude (because it is boosted) than a voltage level such as V₁₁ applied to the P-type switch 230-P to deactivate the P-type switch 230-P to an OFF state.

As discussed above, embodiments herein are useful over conventional techniques. For example, inclusion of the N-type switch 230-N in a switch driver circuit 200 or 300 as discussed herein reduces a size requirement of a functionality equivalent P-type switch 230-P needed to couple a respective voltage source signal 210 such as VBOOT to the output 242. More specifically, use of one or more parallel P-type switches can be used to drive an external switch to an ON state in a conventional application. However, to provide enhanced and substantially equivalent functionality as a large sized conventional P-type field effect transistor, embodiments herein include a parallel combination of a parallel N-type and P-type field effect transistor. Use of the set of parallel switches as discussed herein, namely, inclusion of the parallel combination of the N-type switch 230-N to complement the P-type switch 230-P, reduces a size requirement of the switch driver circuit compared to conventional techniques.

In one embodiment as shown in FIG. 3, a common node (e.g., the drain of switch 230-P is connected to the source of switch 230-N) connects a terminal (e.g., a the drain node) of the P-type switch 230-P and a terminal (e.g., the source node) of switch 230-N. A magnitude of the voltage of the common node 367 substantially varies depending at least in part on an ON/OFF state of the external switch. For example, the voltage of the common node 367 varies depending on a magnitude of the switch node 620 (FIG. 6).

As mentioned, use of the combination of the N-type switch 230-N and the P-type switch 230-P is shown by way of non-limiting example only. As previously discussed, the N-type switch 230-N can be configured to provide strong pull up capability that works in parallel with a respective weaker P-type 230-P pull-up capability. In certain cases, this parallel set of switches 230 holds the control signal 222 at VBOOT even after the boosted voltage on the N-type switch 230-N has leaked away (e.g., the gate-to-source voltage of N-type switch 230-N drops). In other words, PUMP_DRV_SF is a charged-pumped node, which will eventually leak to a lower voltage over time. The P-type switch 230-P keeps the output at voltage, VBOOT, when this happens.

An additional embodiment as shown in FIG. 8 (e.g., including switch driver circuit 800) illustrates use of only the N-type switch 230-N to provide selective connectivity to the voltage source 210. In this alternative embodiment, the P-type switch 230-N is removed and the N-type switch 230-N provides drive functionality as discussed herein. Use of only the N-type switch (and removal of the parallel P-type switch) is acceptable if the output 222 is not needed to be set to a voltage, VBOOT, for an extended amount of time.

FIG. 4 is an example diagram of a voltage booster circuit to boost a corresponding drive voltage according to embodiments herein.

Application of the timing signals 450 to the input of the voltage booster circuit 310 causes the signal PUMP_DRV_SF to switch between voltages V₂₁ and V₂₂ as previously discussed to drive the N-type switch OFF and ON.

FIG. 5 is an example diagram illustrating theoretical variation in a drain to source resistance for the set of parallel switches for a range of different possible Vcc input voltages according to embodiments herein.

As previously discussed, use of a single P-type switch circuit as used in conventional circuits of FIG. 1 requires a relatively large P-type switch to provide a low enough RDS (e.g., effective drain to source resistance) to couple VBOOT to the output 242 during a portion of a drive cycle in which the switch driver circuit initiates activation of switch circuit. The input voltage Vcc to the switch driver circuit may vary. Hence, such a conventional switch driver circuit must be sized appropriately to provide a low RDS at the low end of the Vcc range (e.g., near a magnitude of 5 volts) even though the large P-type switch may not be needed at the higher end of the Vcc range (e.g., nearer 20+ volts).

As shown, using a smaller, more compact circuit (i.e., the set parallel switches including a P-type switch and N-type switch as discussed herein) rather than the conventional large P-type device, embodiments herein provide a relatively constant RDS over a range of different possible Vcc input voltages. Use of a relatively smaller sized N-type field effect transistor in lieu of a larger P-type field effect transistor also reduces an amount of overhead power consumed in generating an output voltage. For example, the gate capacitance of the N-type field effect transistor (e.g., switch 230-N) as discussed herein has a lower gate capacitance because it is smaller in size, thus, reducing an amount of switching losses due to driving the switches ON and OFF.

FIG. 6 is an example diagram illustrating a power converter phase including one or more driver circuits according to embodiments herein.

In one embodiment, the drive circuits DR1 (e.g., switch driver circuit 300) and DR2 can include respective sets of transistors to sink and/or source current as previously discussed to turn switch 642 (e.g., high side switch circuitry) and switch 646 (e.g., low side switch circuitry) between ON and OFF states based on feedback 685.

In one embodiment, the phase controller circuit 610 compares the feedback 685 (e.g., magnitude of the output voltage 680) to a desired setpoint or threshold value. When voltage 680 is below the desired setpoint or threshold value, controller circuit 610 initiates turning field effect transistor 642 to a respective ON state while field effect transistor 646 is turned OFF. When the field effect transistor 642 is ON, inductor 144 is charged with energy from voltage source 630. The energy is conveyed to dynamic load 618 in the form of current, which increases output voltage 680.

Based on monitoring feedback 685, the phase controller circuit 610 detects when the output voltage 680 increases to or above an acceptable level again. When so reached, the controller circuit 610 shuts OFF field effect transistor 642 and turns ON field effect transistor 646.

In one embodiment, the controller circuit 610 does not turn ON field effect transistor 646 until field effect transistor 642 is completely turned to an OFF state. Thus, there may be a duration of time (e.g., so-called dead time) after turning field effect transistor 642 OFF, and before turning field effect transistor 6460N, that current flows from ground, through diode D2 of field effect transistor 646 and inductor 644 to power dynamic load 618.

The phase controller circuit 610 repeats turning ON and OFF the high side switch circuitry (e.g., a control switch) and low side switch circuitry (e.g., a synchronous switch) to maintain a magnitude of the output voltage 680 within a desired range. Accordingly, an external switch such as field effect transistor 642 can selectively couple a power source (e.g., voltage source 630) to switch node 620 of an inductor 644 of a power converter phase 600 in a switching power supply depending on a state of the output voltage 680.

FIG. 7 is a flowchart illustrating an example method of providing improved coupling in a switch driver circuit according to embodiments herein. Note that there will be some overlap with respect to concepts as discussed above. Also, note that the steps in the flowcharts can be executed in any suitable order.

In step 710, the switches driver circuit 300 receives a control signal 220 at input 240.

In step 720, the switch driver circuit 300 utilizes the control signal 220 to control a set of parallel switches in the switch driver circuit 300. As previously discussed, the parallel switches can include at least one p-type switch 230-P in parallel with at least one n-type switch 230-P. The set of parallel switches 230 are controlled in accordance with the control signal 220 to selectively and electrically couple a voltage source signal 210 (e.g., as derived from Vcc) to the output 242 to control the state of an external switch circuit such as field effect transistor 642.

In step 730, based on a first state of the control signal 220 produced by phase controller circuit 610, the switch driver circuit 300 initiates simultaneous activation of both the p-type switch 230-P and the n-type switch 230-N to electrically couple the voltage source signal 210 to the output 242. This activates field effect transistor 642 to electrically couple voltage source 630 to the switch node 620. Recall again that, via input from phase controller circuit 610, DR2 initiates deactivation of field effect transistor 646 while field effect transistor 642 is activated.

In step 740, based on a second state of the control signal 220, the switch driver circuit 300 initiates simultaneous deactivation of both the p-type switch 230-P and the n-type switch 230-N to electrically disconnect the voltage source signal 210 from the output 242. This deactivates field effect transistor 642 to electrically decouple voltage source 630 from the switch node 620. Recall again that, via input from phase controller circuit 610, DR2 initiates activation of field effect transistor 646 while field effect transistor 642 is deactivated.

Note again that techniques herein are well suited for use in power supply applications. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well.

While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application as defined by the appended claims. Such variations are intended to be covered by the scope of this present application. As such, the foregoing description of embodiments of the present application is not intended to be limiting. Rather, any limitations to the invention are presented in the following claims.

Claims

1. An apparatus comprising: a switch driver circuit, the switch driver circuit comprising:an input to receive a control signal;an output to control a state of a switch in accordance with the control signal;a set of parallel switches in the switch driver circuit including a P-type field effect transistor in parallel with an N-type field effect transistor, the set of parallel switches controlled based on the control signal to selectively and electrically couple a voltage source signal to the output to control the state of the switch;a first common node, the first common node connecting a source terminal of the P-type field effect transistor and a drain terminal of the N-type field effect transistor;a second common node, the second common node connecting a drain terminal of the P-type field effect transistor and a source terminal of the N-type field effect transistor; anda capacitor that electrically couples a node of the switch to the first common node;wherein the node of the switch is a source node;wherein the switch is a control switch in a switching power supply;wherein the source node of the switch is electrically coupled to each of: i) a drain node of a synchronous switch in the switching power supply, and ii) a node of an inductive element in the switching power supply; andwherein the capacitor provides capacitive coupling between the node of the switch and the first common node.

2. The apparatus as in claim 1, wherein a first setting of the control signal causes simultaneous activation of both the P-type field effect transistor and the N-type field effect transistor to electrically couple the voltage source signal to the output; and wherein a second setting of the control signal causes simultaneous deactivation of both the P-type field effect transistor and the N-type field effect transistor to electrically disconnect the voltage source signal from the output.

3. The apparatus as in claim 2, wherein simultaneous activation of both the P-type field effect transistor and the N-type field effect transistor activates the switch; and wherein simultaneous deactivation of both the P-type field effect transistor and the N-type field effect transistor and activation of another switch circuit in the switch driver circuit deactivates the switch.

4. The apparatus as in claim 1 further comprising: a voltage booster circuit to generate a boosted voltage signal, the voltage booster circuit outputting the boosted voltage signal to activate the N-type field effect transistor to an ON state.

5. The apparatus as in claim 4, wherein the boosted voltage signal generated by the voltage booster circuit is substantially greater in magnitude than a corresponding voltage level applied to the P-type field effect transistor to deactivate the P-type field effect transistor.

6. The apparatus as in claim 1 further comprising: driving the P-type field effect transistor at different times with voltages in a first pair of voltage levels to switch the P-type field effect transistor between ON and OFF states;driving the N-type field effect transistor at different times with voltages in a second pair of voltage levels to switch the N-type field effect transistor between ON and OFF states, wherein the second pair of voltage levels is different than the first pair of voltage levels.

7. The apparatus as in claim 6, wherein a polarity of the voltage levels to control the P-type field effect transistor between ON and OFF states is opposite to a polarity of the voltage levels to control the N-type field effect transistor between ON and OFF states.

8. The apparatus as in claim 7, wherein a magnitude of the voltage level to activate the N-type field effect transistor to an ON state is substantially greater in magnitude than a voltage level applied to the P-type field effect transistor to deactivate the P-type field effect transistor to an OFF state.

9. The apparatus as in claim 1, wherein inclusion of the N-type field effect transistor to complement the P-type field effect transistor reduces a size requirement of a functionality equivalent P-type field effect transistor otherwise needed to provide equivalent performance as the set of parallel switches.

10. The apparatus as in claim 1, wherein the N-type field effect transistor in the set of parallel switches provides a substantially equivalent RDS as a corresponding substantially larger P-type field effect transistor in an ON state.

11. The apparatus as in claim 1 further comprising: a voltage booster circuit that generates a boosted voltage signal, the voltage booster circuit outputting the boosted voltage signal to activate the N-type field effect transistor to an ON state, the boosted voltage signal applied to a gate of the N-type field effect transistor and decaying to a lower voltage over time subsequent to being initially generated, the P-type field effect transistor electrically coupling the voltage source signal to the output after the boosted voltage signal used to activate the N-type field effect transistor to an ON state has decayed to the lower voltage.

12. The apparatus as in claim 11 further comprising: a resistor bridging the second common node to the output, the output driving a gate of the switch.