Claims
- 1. A voltage regulator having an input terminal and an output terminal, comprising:a first transistor connecting the input terminal to an intermediate terminal; a second transistor connecting the intermediate terminal to ground; a controller that drives the first and second transistors to alternately couple the intermediate terminal between the input terminal and ground; and a filter disposed between the input terminal and the output terminal to provide a substantially DC voltage at the output terminal, the filter including at least one element connecting the intermediate terminal to the output terminal; wherein the first transistor includes a source, a drain and a gate, and the first transistor has a channel length between the source and the drain which is less than a channel length required for reliable behavior under steady state saturation conditions.
- 2. A voltage regulator having an input terminal and an output terminal, comprising:a first transistor connecting the input terminal to an intermediate terminal; a second transistor connecting the intermediate terminal to ground; a controller that drives the first and second transistors to alternately couple the intermediate terminal between the input terminal and ground; and a filter disposed between the input terminal and the output terminal to provide a substantially DC voltage at the output terminal, the filter including at least one element connecting the intermediate terminal to the output terminal; wherein the second transistor includes a source, a drain and a gate, and the second transistor has a channel length between the source and the drain which is less than a channel length required for reliable behavior under steady state saturation conditions.
- 3. A voltage regulator having an input terminal and an output terminal, comprising:a first transistor to intermittently couple the input terminal to the output terminal, wherein the first transistor includes a source, a drain, and a gate, and the first transistor has a channel length between the source and the drain which is less than a channel length required for reliable behavior under steady state saturation conditions; and a filter disposed between the input terminal and the output terminal to provide a substantially DC voltage at the output terminal.
- 4. The voltage regulator of claim 3, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
- 5. The voltage regulator of claim 3, wherein the channel length is about 1 micron.
- 6. The voltage regulator of claim 3, wherein the channel length is shorter than a channel length specified for standard hot electron specification of 10% degradation in a one year period of operation.
- 7. The voltage regulator of claim 3, wherein the transistor is fabricated using one or more of process proximity correction and phase shift mask technology.
- 8. The voltage regulator of claim 3, wherein the first transistor has a double diffused drain structure.
- 9. The voltage regulator of claim 3, further comprising a second transistor to connect an intermediate terminal between the input and output terminals to ground.
- 10. The voltage regulator of claim 9, wherein the first transistor includes a first gate oxide layer having a first thickness and the second transistor includes a second gate oxide layer having a second, different thickness.
- 11. The voltage regulator of claim 10, wherein the first and second oxide layers are formed on a surface of a semiconductor.
- 12. The voltage regulator of claim 9, further comprising a controller to drive the first and second transistors, wherein the controller drives the first transistor with a first gate voltage and drives the second transistor with a second, different gate voltage.
- 13. The voltage regulator of claim 12, wherein the controller includes a first plurality of transistors in a drive train of the first transistor and a second plurality of transistors in a drive train of the second transistor.
- 14. The voltage regulator of claim 13, wherein the second plurality of transistors are driven with the second gate voltage.
- 15. The voltage regulator of claim 13, wherein the first plurality of transistors includes a third transistor driven with the first gate voltage and a fourth transistor driven with the second gate voltage.
- 16. The voltage regulator of claim 12, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
- 17. The voltage regulator of claim 16, wherein the first gate voltage is larger than the second gate voltage and the first gate oxide layer is thicker than the second gate oxide layer.
- 18. The voltage regulator of claim 16, wherein the first gate voltage is larger than the second gate voltage.
- 19. The voltage regulator of claim 18, wherein the first gate voltage is substantially equal to an input voltage at the input terminal.
- 20. The voltage regulator of claim 18, wherein the second gate voltage is compatible with a logic voltage.
- 21. The voltage regulator of claim 20, wherein the first gate voltage is greater than the logic voltage.
- 22. The voltage regulator of claim 13, wherein the first transistor includes a first gate oxide layer having a first thickness and the second transistor includes a second gate oxide layer having a second, different thickness.
- 23. The voltage regulator of claim 12, wherein application of the first gate voltage turns the first transistor on.
- 24. The voltage regulator of claim 12, wherein application of the second gate voltage turns the second transistor on.
Parent Case Info
The present application is a division of U.S. application Ser. No. 09/475,713, filed Dec. 30, 1999, the entire disclosure of which is incorporated herein by reference.
US Referenced Citations (5)
Continuations (1)
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Number |
Date |
Country |
Parent |
09/457713 |
Dec 1999 |
US |
Child |
10/032797 |
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US |