Switching systems and methods for use in uninterruptible power supplies

Information

  • Patent Grant
  • 10355521
  • Patent Number
    10,355,521
  • Date Filed
    Monday, November 6, 2017
    6 years ago
  • Date Issued
    Tuesday, July 16, 2019
    4 years ago
Abstract
An uninterruptible power supply for providing an output power signal to a load comprises a ferroresonant transformer, a resonant capacitor, and an inverter. The resonant capacitor is operatively connected to the ferroresonant transformer. The inverter is operatively connected to the ferroresonant transformer. The inverter is configured to generate the output power signal based on at least one inverter control signal such that the output power signal is a quasi square wave having at least one change of phase and an upper limit. The at least one inverter control signal is held in an OFF state during at least a portion of the at least one change of phase, pulse-width modulated during at least a portion of the at least one change of phase, and held in an ON state when the output power signal is at the upper limit.
Description
TECHNICAL FIELD

The present invention relates the generation of a standby power signal and, more specifically, to uninterruptible power supply systems and methods that generate a standby signal using an inverter system.


BACKGROUND

Uninterruptible power supplies (UPS's) have long been used to provide at least temporary auxiliary power to electronic devices. Typically, a UPS is configured to switch between a primary power source and a standby power source as necessary to maintain constant power to a load. Typically, the primary power source for a UPS is a utility power supply, and the standby power source may take the form of a battery system. The UPS will normally operate in a line mode in which the utility power signal is passed to the load when the utility power signal is within predefined parameters. In the line mode, the UPS will typically also charge the battery system. When the utility power falls outside of the predefined parameters, the UPS will switch to standby mode in which an AC signal is generated based on the energy stored in the battery system.


A class of UPS's employs a ferroresonant transformer. A ferroresonant transformer is a saturating transformer that employs a tank circuit comprised of a resonant winding and capacitor to produce a nearly constant average output even if the input to the transformer varies. A typical UPS employing a ferroresonant transformer takes advantage of the voltage regulating properties of a ferroresonant transformer in both line and standby modes. In the context of a UPS, a ferroresonant transformer thus provides surge suppression, isolation, short circuit protection, and voltage regulation without the use of active components.


Conventionally, in line mode, a UPS employs an inverter circuit configured to form a switch mode power supply. An inverter circuit configured as a switch mode power supply typically comprises at least one and typically a plurality of power switches that are operated according to a pulse-width modulated (PWM) signal. The PWM method of generating an AC signal from a DC source allows the amplitude of the AC signal to be determined at any point in time by controlling the duty cycle at which the inverter power switches are operated. Controlling the duty cycle at which the inverter power switches are operated produces, through an output LC filter, a desired net average voltage. Typically, the parameters of the inverter control signal are varied according to a control signal generated by a feedback loop having an input formed by at least one characteristic, such as voltage, of the AC signal.


In a switch mode power supply, one of the major causes of loss of efficiency arises from the imperfect switching characteristics of modern power switches during the transition between the ON and OFF configurations of the power switches. An object of the present invention is to provide switch mode power supplies for use in UPS systems having improved efficiency.


SUMMARY

The present invention may be embodied as an uninterruptible power supply for providing an output power signal to a load comprising a ferroresonant transformer, a resonant capacitor, and an inverter. The resonant capacitor is operatively connected to the ferroresonant transformer. The inverter is operatively connected to the ferroresonant transformer. The inverter is configured to generate the output power signal based on at least one inverter control signal such that the output power signal is a quasi square wave having at least one change of phase and an upper limit. The at least one inverter control signal is held in an OFF state during at least a portion of the at least one change of phase, pulse-width modulated during at least a portion of the at least one change of phase, and held in an ON state when the output power signal is at the upper limit.


The present invention may also be embodied as a method of providing an output power signal to a load comprising the following steps. A resonant capacitor is operatively connected to a ferroresonant transformer. An inverter is operatively connected to the ferroresonant transformer. The inverter is configured to generate the output power signal based on at least one inverter control signal such that the output power signal is a quasi square wave having at least one change of phase and an upper limit. The at least one inverter control signal is held in an OFF state during at least a portion of the at least one change of phase. The at least one inverter control signal is pulse-width modulated during at least a portion of the at least one change of phase. The at least one inverter control signal is held in an ON state when the output power signal is at the upper limit.





DESCRIPTION OF THE DRAWINGS


FIG. 1 is a simplified block diagram of a first embodiment of an uninterruptible power supply system using a ferroresonant transformer system constructed in accordance with, and embodying, the principles of the present invention;



FIG. 2 is a timing diagram representing control and power signals employed by the UPS system depicted in FIG. 1; and



FIG. 3 depicts a first quasi-square wave form, a second quasi-square wave form, and a third quasi-square waveform.





DETAILED DESCRIPTION

Referring initially to FIG. 1 of the drawing, depicted therein is a first example of an uninterruptible power supply (UPS) system 20 constructed in accordance with, and embodying, the principles of the present invention. The present invention is of particular significance when applied to a UPS system adapted for use in a communications system, such as CATV or telephony system, and that use of the present invention will be disclosed herein in detail. However, it should be understood that the principles of the present invention may be applied to UPS systems adapted for use in environments other than communications systems.


The example UPS system 20 supplies power to a load 22 based on a primary power signal present on an AC power line 24 (line mode) or a secondary power signal generated by a battery pack 26 (standby mode). While the example secondary power signal is generated by a battery pack in the example UPS system 20, alternative power sources such as generators, fuel cells, solar cells, and the like may be used as the secondary power source.


The example UPS system 20 comprises an input section 30, an output section 32, an inverter section 34, and a ferroresonant transformer 36. The example input section 30 comprises a main switch 40 and first and second select switches 42 and 44. The example output section 32 comprises an output (e.g., resonant) capacitor 50. The output capacitor 50 forms a resonant or tank circuit with the transformer 36 as will be described in further detail below.


The inverter section 34 comprises an inverter circuit 60 and a controller 62. The inverter circuit 60 may be an H-bridge circuit or any other circuit capable of producing an appropriate AC power signal based on a DC power signal obtained from the battery pack 26. The inverter circuit 60 is or may be conventional and will not be described herein in further detail.


The example controller 62 controls the inverter circuit 60. The controller 62 may further control the charging of the battery pack 26 when the UPS system 20 operates in line mode based on temperature, voltage, and/or current signals associated with the battery pack 26.


The example inverter circuit 60 is pulse-width modulated, and the inverter section 34 functions as a switch mode power supply when the UPS system operates in the standby mode. As will be described in further detail below, the controller 62 generates one or more inverter control signals that control the inverter circuit to generate a switched output signal.


The example ferroresonant transformer 36 comprises a core 70, input windings 72, an inductor 74, inverter windings 76, and output windings 78. The core 70 is or may be a conventional laminate structure. The inductor 74 defines a primary side 80 and a secondary side 82 of the transformer 36. In the example UPS system 20, the output capacitor 50 is connected across first and second ends 90 and 92 of the output windings 78, and the load is connected between the second end 92 of the output windings 78 and a tap 94 in the output windings 78.


In the example transformer 36, only the input windings 72 are on the primary side 80 of the transformer 36. The inverter windings 76 and output windings 78 are on the secondary side 82 of the transformer 36. In particular, the output windings 78 are arranged between the inverter windings 76 and the inductor 74, and the inductor 74 is arranged between the output windings 78 and the input windings 72. A ferroresonant transformer appropriate for use as the example ferroresonant transformer 36 is described, for example, in U.S. Patent Application Ser. No. 60/305,926 and Ser. No. 12/803,787, and those applications are incorporated herein by references. The principles of the present invention may, however, be applied to other configurations of ferroresonant transformers.


In line mode, the main switch 40 is closed and the AC power line 24 is present on the input windings 72. The input windings 72 are electromagnetically coupled to the output windings 78 such that a primary AC output signal is supplied to the load 22 when the UPS system 20 operates in the line mode.


In standby mode, the main switch 40 is opened, and the battery pack 26 and inverter section 34 form a secondary power source supplies a standby AC output signal to the load 22. In particular, in standby mode the inverter section 34 generates the switched power signal across the inverter windings 76, and the inverter windings 76 are electromagnetically coupled to the output windings 78 and to the output capacitor such that the standby AC output signal is present across the tap 94 and the second end 92 of the output windings 78. Further, during standby mode, an optional switch (not shown) may be provided in series with the output capacitor 50 to allow the output capacitor 50 to be disconnected from the output windings, thereby reducing peak inverter currents observed due to charging and discharging of the output capacitor 50.


The example inverter section 34 conventionally comprises at a plurality of power switches (not shown) configured as a switch mode power supply. Typically, the power switches are MOSFETS configured as an H-bridge circuit or any other circuit capable of producing an appropriate standby AC power signal based on a DC power signal obtained from the battery pack 26.


The inverter control module 62 generates one or more inverter control signals based on a characteristic, such as voltage, of the standby AC output signal applied to the load 22. The inverter control signal or signals may be pulse-width modulated (PWM) signals the characteristics of which cause the power switches of the inverter circuit 60 to open and close as necessary to generate the standby AC output signal within predetermined voltage, frequency, and waveform parameters. In the example UPS system 20 operating in standby mode, the inverter circuit 60, inverter control circuit 62, the inverter windings 76, and output windings 78 thus form a feedback loop that controls a desired net average voltage as appropriate for the load 22.


The Applicants have recognized that loads, such as the example load 22 to which power is supplied by a UPS used in communications networks such as CATV networks, are constant power loads that typically employ a diode rectifier circuit supplying a large capacitor bank. Such loads demand very high current at the peak AC power voltage at the instant the AC voltage amplitude exceeds the bus capacitor voltage. The Applicants further recognized that a substantial portion, if not all, of the load power will be delivered in the period during which the AC voltage amplitude is higher than the DC bus capacitor. This results in higher peak current to compensate for the fact that less than 100% of the time is available to transfer energy to the load.


The inverter control module 62 of the present invention thus eliminates the pulse-width modulation at the peak of the standby AC output signal. The Applicant has discovered that the elimination of pulse-width modulation at the peak of the standby AC output signal allows the power switches of the inverter circuit 60 to be full ON (100% duty cycle) during the time of peak current transfer to the bus capacitors. Eliminating pulse-width modulation of the inverter control signal during at least part of the cycle of the standby AC output signal significantly improves (by between approximately 10-20%) the efficiency of the UPS system 20 when operating in standby mode.


Referring now to FIG. 2 of the drawing, depicted therein are several waveforms that may be implemented by the example UPS system 20 operating in standby mode. FIG. 2 conventionally plots each voltage (y-axis) versus time (x-axis). FIG. 2 is further divided into first through ninth time periods T1-9 separated by vertical broken lines.


Depicted at 120 is an example standby AC output signal 120 supplied to the load 22. Depicted at 130 in FIG. 2 is an example switched power signal 130 generated by the inverter section 34 and applied across the inverter windings 76. Depicted at 140 and 142 in FIG. 2 are representations of inverter control signals that may be generated by the inverter control module 62 for controlling the inverter power switches of the inverter circuit 60. As is conventional, the first inverter control signal using the principles of the present invention, the inverter control signals 140 and 142 may operate at a relatively high frequency, e.g., approximate 20 kHz, with a duty cycle that is varied between 0% and 100% as described below to obtain the desired waveform.


The period of peak current transfer occurs in the time periods T2, T5, and T8 in FIG. 2. During these periods, the inverter control signal generated by the inverter control module 62 for controlling the inverter circuit 60 is held in a state that closes the power switches (100% duty cycle) of the inverter circuit 60. FIG. 2 further shows that the switched power signal 130 generated by the example inverter section 34 is pulse-width modulated (switched between OFF and ON) during the time periods T1, T3, T4, T6, T7 and T9 outside of the periods of peak current transfer and is held HIGH (100% duty cycle) during the time periods T2, T5, and T8. The operation of these switches of the inverter circuit 60 in their least efficient mode (from ON to OFF or from OFF to ON) is thus avoided during the period of peak current transfer to the load 22. The inverter control signals 140 and 142 represent one example method of controlling an inverter circuit such as the example inverter circuit 60 to generate the switched power signal 130 and standby AC output signal 120 as depicted in FIG. 2


The example standby AC output signal 120 depicted in FIG. 2 is what is referred to as a modified or quasi square wave. A standby AC power signal having a modified or quasi square wave, such as the example signal 120, is appropriate for providing power to the load 22.


To provide voltage regulation, the duration of the periods of time T2, T5, and T5 in which the switches are operated at 100% duty cycle (held ON) can be varied as shown in FIG. 3. FIG. 3 illustrates second and third example standby AC power signals 150 and 160; the example standby AC power signal 120 is also reproduced in FIG. 3 for reference. The second example standby AC power signal 150 corresponds to a load having a low DC bus relative to the mid DC bus of the load corresponding to the first example standby AC output signal 120. The third example standby AC power signal 160 corresponds to a load having a high DC bus relative to the mid DC bus of the load corresponding to the first example standby AC output signal 120.


Additionally, to provide voltage regulation and maintain an acceptable modified or quasi square wave, the inverter control signals 140 and 142 are generated to alter the dV/dt, or slope, of the standby AC power signal 120 during the time periods T1, T3, T4, T6, T7 and T9 outside of the periods of peak current transfer. Additionally, the switched power signal 130 may be held at zero during phase change transitions to allow more control of voltage regulation.


The second example standby AC power signal 150 thus has a lower peak voltage during peak current transfer in the time periods T2, T5, and T5 and steeper slope during the time periods T1, T3, T4, T6, T7 and T9 outside of the periods of peak current transfer. The steeper slope in the time periods T1, T3, T4, T6, T7 and T9 is obtained by appropriate control of the duty cycle of the switched power signal 130.


The third example standby AC power signal 160, on the other hand, has a higher peak voltage during peak current transfer in the time periods T2, T5, and T8. The slope of the third example standby AC power signal is similar to the slope of the first example AC power signal 160 during the time periods T1, T3, T4, T6, T7 and T9 outside of the periods of peak current transfer. However, the third example standby AC power signal 160 is held at zero for a short time during crossover periods 162 and 164 when the AC power signal 160 changes phase. The zero voltage at the crossover periods 162 and 164 is obtained by turning the switched power signal 130 OFF (0% duty cycle) during the crossover periods 162 and 164.


More generally, the switching pattern of the inverter control signals and the design of the transformer are optimized to provide maximum efficiency across the specified output voltage and specified load range. Relevant optimization schemes include providing enough volt-seconds to the inverter winding to meet the voltage requirements of the load but not so many volt-seconds that the transformer saturates.


Given the foregoing, it should be apparent that the principles of the present invention may be embodied in forms other than those described above. The scope of the present invention should thus be determined by the claims to be appended hereto and not the foregoing detailed description of the invention.

Claims
  • 1. An uninterruptible power supply for providing an output power signal to a load comprising: a ferroresonant transformer;a resonant capacitor operatively connected to the ferroresonant transformer; andan inverter operatively connected to the ferroresonant transformer, wherein:the inverter is configured to generate the output power signal based on at least one inverter control signal such that the output power signal is a quasi square wave having at least one change of phase and an upper limit; andthe at least one inverter control signal is held in an OFF state during at least a portion of the at least one change of phase,pulse-width modulated during at least a portion of the at least one change of phase, andheld in an ON state when the output power signal is at the upper limit.
  • 2. An uninterruptible power supply as recited in claim 1, in which: the output power signal defines a plurality of changes of phase;the at least one inverter control signal is pulse-width modulated during at least a portion of each of the plurality of changes of phase, andheld in an OFF state during at least a portion of each of the plurality of changes of phase.
  • 3. An uninterruptible power supply as recited in claim 1, in which a duration of the ON state is varied to regulate the upper limit of the output power signal.
  • 4. An uninterruptible power supply as recited in claim 1, in which a duty cycle of the at least one inverter control signal is varied to control a slope of the output power signal.
  • 5. An uninterruptible power supply as recited in claim 1, in which: the quasi square wave of the output power signal further has a lower limit;the inverter section generates the standby power signal based on first and second inverter control signals;the first inverter control signal is held in an ON state when the output power signal is at the upper limit; andthe second inverter control signal is held in an ON state when the output power signal is at the lower limit.
  • 6. A method of providing an output power signal to a load comprising the steps of: operatively connecting a resonant capacitor to a ferroresonant transformer;operatively connecting an inverter to the ferroresonant transformer;configuring the inverter to generate the output power signal based on at least one inverter control signal such that the output power signal is a quasi square wave having at least one change of phase and an upper limit;holding the at least one inverter control signal in an OFF state during at least a portion of the at least one change of phase;pulse-width modulating the at least one inverter control signal during at least a portion of the at least one change of phase; andholding the at least one inverter control signal in an ON state when the output power signal is at the upper limit.
  • 7. A method as recited in claim 6, further comprising the steps of: configuring the inverter such that the output power signal defines a plurality of changes of phase;pulse-width modulating the at least one inverter control signal during at least a portion of each of the plurality of changes of phase; andholding the at least one inverter control signal in an OFF state during at least a portion of each of the plurality of changes of phase.
  • 8. A method as recited in claim 6, further comprising the step of varying a duration of the ON state to regulate the upper limit of the output power signal.
  • 9. A method as recited in claim 6, further comprising the step of varying a duty cycle of the at least one inverter control signal to control a slope of the output power signal.
  • 10. A method as recited in claim 6, further comprising the steps of: configuring the inverter such that the quasi square wave of the output power signal further has a lower limit;generating the standby power signal based on a first inverter control signal that is held in an ON state when the output power signal is at the upper limit; andgenerating the standby power signal based on a second inverter control signal that is held in an ON state when the output power signal is at the lower limit.
  • 11. A method as recited in claim 6, further comprising the step of generating the standby power signal based on first and second inverter control signals such that the first and second inverter control signals are in an OFF state during at least a portion of each of the plurality of changes of phase.
RELATED APPLICATIONS

This application, U.S. patent application Ser. No 15/804,977 filed Nov. 6, 2017, is a continuation of U.S. patent application Ser. No. 14/706,779 filed May 7, 2015, now U.S. Pat. No. 9,812,900, which issued on Nov. 7, 2017. U.S. patent application Ser. No. 14/706,779 is a continuation of U.S. patent application Ser. No. 13/352,308 filed Jan. 17, 2012, now U.S. Pat. No. 9,030,045, which issued on May 12, 2015. U.S. patent application Ser. No. 13/352,308 filed Jan. 17, 2012, claims benefit of U.S. Provisional Patent Application Ser. No. 61/435,317 filed Jan. 23, 2011. The contents of the related applications listed above are incorporated herein by reference.

US Referenced Citations (220)
Number Name Date Kind
352105 Zipernowsky et al. Nov 1886 A
375614 Eickemeyer Dec 1887 A
414266 Thomson Nov 1889 A
1718238 Kettering et al. Jun 1929 A
1950396 Boucher Mar 1934 A
2007415 Walker Jul 1935 A
2014101 Bryan Sep 1935 A
2037183 Strieby Apr 1936 A
2036994 Frank et al. Dec 1936 A
2085072 Bobe Jun 1937 A
2165969 Humbert et al. Jul 1939 A
2240123 Shoup et al. Apr 1941 A
2302192 Dannheiser Nov 1942 A
2352073 Boucher et al. Jun 1944 A
2427678 Laging Sep 1947 A
2444794 Uttal et al. Jul 1948 A
2512976 Smeltzly Jun 1950 A
2688704 Christenson Sep 1954 A
2856543 Dixon et al. Oct 1958 A
2920211 Gotoh Jan 1960 A
2996656 Sola Aug 1961 A
3022458 Sola Feb 1962 A
3064195 Freen Nov 1962 A
3221172 Rolison Nov 1965 A
3283165 Bloch Nov 1966 A
3293445 Levy Dec 1966 A
3304599 Nordin Feb 1967 A
3305762 Geib, Jr. Feb 1967 A
3339080 Howald Aug 1967 A
3345517 Smith Oct 1967 A
3348060 Jamieson Oct 1967 A
3389329 Quirk et al. Jun 1968 A
3435358 Rheinfelder Mar 1969 A
3458710 Dodge Jul 1969 A
3521152 Emerson Jul 1970 A
3525035 Kakalec Aug 1970 A
3525078 Baggott Aug 1970 A
3546571 Fletcher et al. Dec 1970 A
3590362 Kakalec Jun 1971 A
3636368 Sia Jan 1972 A
3678284 Peters Jul 1972 A
3678377 Chiffert Jul 1972 A
3686561 Spreadbury Aug 1972 A
3691393 Papachristou Sep 1972 A
3742251 Thompson et al. Jun 1973 A
3823358 Rey Jul 1974 A
3859589 Rush Jan 1975 A
3860748 Everhart et al. Jan 1975 A
3873846 Morio et al. Mar 1975 A
3909560 Martin et al. Sep 1975 A
3916295 Hunter Oct 1975 A
3938033 Borkovitz et al. Feb 1976 A
3943447 Shomo, III Mar 1976 A
4004110 Whyte Jan 1977 A
4010381 Fickenscher et al. Mar 1977 A
4122382 Bernstein Oct 1978 A
4130790 Heisey Dec 1978 A
4170761 Koppehele Oct 1979 A
4217533 Van Beek Aug 1980 A
4251736 Coleman Feb 1981 A
4262245 Wendt Apr 1981 A
4270080 Kostecki May 1981 A
4277692 Small Jul 1981 A
4313060 Fickenscher et al. Jan 1982 A
4353014 Willis Oct 1982 A
4366389 Hussey Dec 1982 A
4366390 Rathmann Dec 1982 A
4385263 Luz et al. May 1983 A
4400624 Ebert, Jr. Aug 1983 A
4400625 Hussey Aug 1983 A
4423379 Jacobs et al. Dec 1983 A
4460834 Gottfried Jul 1984 A
4466041 Witulski et al. Aug 1984 A
4472641 Dickey et al. Sep 1984 A
4475047 Ebert Oct 1984 A
4510401 Legoult Apr 1985 A
4604530 Shibuya Aug 1986 A
4616305 Damiano et al. Oct 1986 A
4628426 Steigerwald Dec 1986 A
4631471 Fouad et al. Dec 1986 A
4656412 McLyman Apr 1987 A
4670702 Yamada et al. Jun 1987 A
4673825 Raddi et al. Jun 1987 A
4686375 Gottfried Aug 1987 A
4697134 Burkum et al. Sep 1987 A
4700122 Cimino et al. Oct 1987 A
4709318 Gephart et al. Nov 1987 A
4719427 Morishita et al. Jan 1988 A
4719550 Powell et al. Jan 1988 A
4775800 Wood Jan 1988 A
4724290 Campbell Feb 1988 A
4724478 Masuko et al. Feb 1988 A
4730242 Divan Mar 1988 A
4733223 Gilbert Mar 1988 A
4740739 Quammen et al. Apr 1988 A
4745299 Eng et al. May 1988 A
4748341 Gupta May 1988 A
4748342 Dijkmans May 1988 A
4763014 Model et al. Aug 1988 A
4791542 Piaskowski Dec 1988 A
4829225 Podrazhansky et al. May 1989 A
4860185 Brewer et al. Aug 1989 A
4864483 Divan Sep 1989 A
4882717 Hayakawa et al. Nov 1989 A
4885474 Johnstone et al. Dec 1989 A
4890213 Seki Dec 1989 A
4916329 Dang et al. Apr 1990 A
4920475 Rippel Apr 1990 A
4922125 Casanova et al. May 1990 A
4926084 Furutsu et al. May 1990 A
4943763 Bobry Jul 1990 A
4952834 Okada Aug 1990 A
4954741 Furutsu et al. Sep 1990 A
4975649 Bobry Dec 1990 A
4988283 Nagasawa et al. Jan 1991 A
5010469 Bobry Apr 1991 A
5017800 Divan May 1991 A
5027264 DeDoncker et al. Jun 1991 A
5029285 Bobry Jul 1991 A
5057698 Widener et al. Oct 1991 A
5099410 Divan Mar 1992 A
5137020 Wayne et al. Aug 1992 A
5148043 Hirata et al. Sep 1992 A
5154986 Takechi et al. Oct 1992 A
5168205 Kan et al. Dec 1992 A
5172009 Mohan Dec 1992 A
5185536 Johnson, Jr. et al. Feb 1993 A
5193067 Sato et al. Mar 1993 A
5198698 Paul et al. Mar 1993 A
5198970 Kawabata et al. Mar 1993 A
5200643 Brown Apr 1993 A
5224025 Divan et al. Jun 1993 A
5229650 Kita et al. Jul 1993 A
5237208 Tominaga et al. Aug 1993 A
5281919 Palanisamy Jan 1994 A
5302858 Folts Apr 1994 A
5334057 Blackwell Aug 1994 A
5400005 Bobry Mar 1995 A
5402053 Divan et al. Mar 1995 A
5410720 Osterman Apr 1995 A
5440179 Severinsky Aug 1995 A
5457377 Jonsson Oct 1995 A
5483463 Qin et al. Jan 1996 A
5532525 Kaiser et al. Jul 1996 A
5579197 Mengelt et al. Nov 1996 A
5602462 Stich et al. Feb 1997 A
5610451 Symonds Mar 1997 A
5635773 Stuart Jun 1997 A
5638244 Mekanik et al. Jun 1997 A
5642002 Mekanik et al. Jun 1997 A
5739595 Mekanik et al. Apr 1998 A
5745356 Tassitino, Jr. et al. Apr 1998 A
5747887 Takanaga et al. May 1998 A
5747888 Zilberberg May 1998 A
5760495 Mekanik Jun 1998 A
5768117 Takahashi et al. Jun 1998 A
5783932 Namba et al. Jul 1998 A
5790391 Stich et al. Aug 1998 A
5804890 Kakalec et al. Sep 1998 A
5844327 Batson Dec 1998 A
5880536 Mardirossian Mar 1999 A
5892431 Osterman Apr 1999 A
5897766 Kawatsu Apr 1999 A
5901057 Brand et al. May 1999 A
5925476 Kawatsu Jul 1999 A
5961604 Anderson et al. Oct 1999 A
5982412 Nulty Nov 1999 A
5982645 Levran et al. Nov 1999 A
5982652 Simonelli et al. Nov 1999 A
5994793 Bobry Nov 1999 A
5994794 Wehrlen Nov 1999 A
6011324 Kohlstruck et al. Jan 2000 A
6014015 Thorne et al. Jan 2000 A
6028414 Chouinard et al. Feb 2000 A
6069412 Raddi et al. May 2000 A
6074246 Seefeldt et al. Jun 2000 A
6100665 Alderman Aug 2000 A
6198178 Schienbein et al. Mar 2001 B1
6212081 Sakai Apr 2001 B1
6218744 Zahrte et al. Apr 2001 B1
6288456 Cratty Sep 2001 B1
6288916 Liu et al. Sep 2001 B1
6295215 Faria et al. Sep 2001 B1
6348782 Oughton et al. Feb 2002 B1
6426610 Janik Jul 2002 B1
6433905 Price et al. Aug 2002 B1
6465910 Young et al. Oct 2002 B2
6486399 Armstrong et al. Nov 2002 B1
6602627 Liu et al. Aug 2003 B2
6738435 Becker May 2004 B1
6841971 Spée et al. Jan 2005 B1
6906933 Taimela Jun 2005 B2
6933626 Oughton Aug 2005 B2
7040920 Johnson et al. May 2006 B2
7182632 Johnson et al. Feb 2007 B1
7449798 Suzuki et al. Nov 2008 B2
7567520 Ostrosky Jul 2009 B2
8575779 Le et al. Nov 2013 B2
9030045 Richardson et al. May 2015 B2
9030048 Heidenreich et al. May 2015 B2
9234916 Peck et al. Jan 2016 B2
9633781 Le et al. Apr 2017 B2
9812900 Richardson et al. Nov 2017 B2
20050258927 Lu Nov 2005 A1
20070262650 Li Nov 2007 A1
20090076661 Pearson et al. Mar 2009 A1
20090196082 Mazumder et al. Aug 2009 A1
20090240377 Batzler et al. Sep 2009 A1
20100324548 Godara et al. Dec 2010 A1
20110187197 Moth Aug 2011 A1
20110238345 Gauthier et al. Sep 2011 A1
20110273151 Lesso et al. Nov 2011 A1
20120091811 Heidenreich et al. Apr 2012 A1
20120212051 Heidenreich et al. Aug 2012 A1
20120217800 Heidenreich et al. Aug 2012 A1
20120217806 Heidenreich et al. Aug 2012 A1
20120217808 Richardson et al. Aug 2012 A1
20140062189 Le et al. Mar 2014 A1
20170229906 Le et al. Aug 2017 A1
20180062427 Richardson et al. Mar 2018 A1
Foreign Referenced Citations (54)
Number Date Country
687528 Feb 1998 AU
2015203667 Mar 2017 AU
1265231 Jan 1990 CA
2033685 Oct 1991 CA
2036296 Nov 1991 CA
1297546 Mar 1992 CA
2086897 Jul 1993 CA
2149845 Dec 1995 CA
2168520 Aug 1996 CA
2028269 Jan 2000 CA
2403888 Sep 2001 CA
2713017 Jul 2009 CA
2504101 May 2010 CA
2760581 Nov 2010 CA
2602789 Jul 1977 DE
2809514 Sep 1978 DE
3321649 Dec 1983 DE
0284541 Sep 1988 EP
0196004 Nov 1993 EP
2425515 Mar 2012 EP
2587620 May 2013 EP
762789 Apr 1934 FR
861215 Feb 1941 FR
005201 Apr 1885 GB
260731 Sep 1925 GB
2005118 Apr 1979 GB
2120474 Nov 1983 GB
2137033 Mar 1984 GB
2171861 Sep 1986 GB
2185326 Oct 1986 GB
2355350 Apr 2001 GB
5482053 Jun 1979 JP
S5482053 Jun 1979 JP
55032133 Mar 1980 JP
S5532133 Mar 1980 JP
5650417 May 1981 JP
S5650417 May 1981 JP
56155420 Dec 1981 JP
S56155420 Dec 1981 JP
2000350381 Dec 2000 JP
2001190035 Jul 2001 JP
2005295776 Oct 2005 JP
2010136547 Jun 2010 JP
2221320 Oct 2004 RU
200941897 Oct 2009 TW
I539721 Jun 2016 TW
8501842 Apr 1985 WO
0021180 Apr 2000 WO
2009094540 Jul 2009 WO
2010135406 Nov 2010 WO
2011103131 Dec 2011 WO
2012099911 Jul 2012 WO
2012148512 Nov 2012 WO
2012112252 Jan 2013 WO
Non-Patent Literature Citations (28)
Entry
Bridge et al., “Preventing outages without batteries”, CED, Jun. 1999, 7 pages.
Broadband Business and News Perspective, “Cable operators feeling power surge”, Reprinted from CED, Apr. 2000, 4 pages.
Contino et al., Water-Cooling Applications for Telecommunications and Computer Energy Systems, Telecommunications Energy Conference, IEEE, 1988, pp. 441-447.
H.C. Gerdes et al., A Practical Approach to Understanding Ferroresonance, EEE—Circuit Design Engineering, pp. 87-89, Apr. 1966.
Harry P. Hart et al., The Derivation and Application of Design Equations for Ferroresonant Voltage Regulators and Regulated Rectifiers, IEEE Transactions on Magnetics, vol. MAG-7, No. 1, Mar. 1971, pp. 205-211.
IEEE Standard for Ferroresonant Voltage Regulators, Electronics Transformer Technical Committee of the IEEE Power Electronics Society, IEEE Std. 449-1990, May 16, 1990, 29 pages.
International Search Report, PCT/US99/19677, dated Feb. 8, 2000, 5 pages.
International Searching Authority, “PCT/US2011/025000”, International Search Report, dated Oct. 26, 2011, 9 pages.
International Searching Authority, “PCT/US2012/021619”, International Search Report, dated May 17, 2012, 7 pages.
International Searching Authority, PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, dated Dec. 8, 2016, 8 pages.
Ivensys, “Power When You Really Need It!”, Publication No. CSG29FXA, Feb. 2000, 2 pages.
Ivensys, “Sometimes Less Is More!”, Publication No. CSG28FXA, Feb. 2000, 2 pages.
Jain et al., High Frequency Triport UPS Topologies for Emerging Fiber Networks, Telecommunications Energy Conference, IEEE, 1998, pp. 505-512.
Jefferson T. Mitchell et al., Rectifiers and Energy Conservation, Telecommunications, Mar. 1979, 3 pages.
Kakalec, “A Feedback-Controlled Ferroresonant Voltage Regulator,” IEEE Transactions of Magnetics, Mar. 1970, 5 pages, vol. MAG-6, No. 1.
Lectro Products Incorporated, “Lectro Ferro Family”, Publication No. CSGI6FXA, Nov. 1998, 4 pages.
Lectro Products Incorporated, “Solving CATV Power Solutions”, Publication No. CSG24FYA, Jun. 1999, 12 pages.
Marcotte et al., “Powering Cable TV Systems”, Reprinted from Broadband Systems & Design, Jun. 1996, 4 pages.
Marcotte, “Power migration strategies for future-proofing”, Reprinted from CED Magazine, Jun. 1997, 4 pages.
McGraw-Hill, Dictionary of Scientific and Technical Terms Fifth Edition, p. 745 and pp. 1696-1697, 1994.
Multipower, Inc., “Confluence Newsletters, vols. I and II”, “MP 900”, and “MP1350”, web site http://www.multipowerups.com/index.htm, Aug. 2000, 16 pages.
RANDO, AC Tripoli—A New Uninterruptible AC Power Supply, Telephone Energy Conference, IEEE, 1978, pp. 50-58.
Rex Teets, Application and Design of Ferroresonant Transformers, No Date, pp. 28-34.
Robert J. Kakalec et al., New Technology for Battery-Charging Rectifiers, Bell Laboratories Record, May 1979, pp. 131-134.
Spears, “Disturbances Can Toast Your System”, Reprint from Communications Technology, Apr. 2000, 4 pages.
Stewart Nowak, Power Problems: Selecting a UPS, Electronics Test, Jul. 13, 1990, 4 pages, No. 7, San Francisco, CA, US.
Wallace et al., Wireless Load Sharing of Single Phase Telecom Inverters, Telecommunication Energy Conference, 1999, 13 pages.
Xia, Ordinary Meter Measures Battery Resistance, EDN—Design Ideas, Jun. 24, 1993, 2 pages.
Related Publications (1)
Number Date Country
20180062427 A1 Mar 2018 US
Provisional Applications (1)
Number Date Country
61435317 Jan 2011 US
Continuations (2)
Number Date Country
Parent 14706779 May 2015 US
Child 15804977 US
Parent 13352308 Jan 2012 US
Child 14706779 US