Switching transistor driver circuit

Abstract

Of a pair of switching transistors connected in series between a high voltage power source and the ground, when the switching transistor on the high potential side is controlled by an RS flip-flop in response to an input signal, in order to prevent a malfunction caused by the influence of dv/dt transient phenomena of an output terminal for driving a load, a latch circuit is reset using an input signal from a low side input terminal LIN in a period during which the voltage of the output terminal for driving the load abruptly decreases.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a switching transistor driver circuit according to Embodiment 1 of the present invention;

FIG. 2 specifically shows edge detection circuits 35 and 36 according to Embodiment 1;

FIG. 3 is a timing chart of the edge detection circuits 35 and 36 according to Embodiment 1;

FIG. 4 is a timing chart showing that two reset pulses are generated according to Embodiment 1;

FIG. 5 is a timing chart showing that the reset pulses are combined into one according to Embodiment 1;

FIG. 6 is a switching transistor driver circuit according to Embodiment 2 of the present invention;

FIG. 7 is a switching transistor driver circuit according to Embodiment 3 of the present invention;

FIG. 8 is a timing chart of Embodiment 3;

FIG. 9 is a switching transistor driver circuit according to Embodiment 4 of the present invention;

FIG. 10 is a timing chart of Embodiment 4;

FIG. 11 shows a switching transistor driver circuit according to Embodiment 5 of the present invention;

FIG. 12 is a timing chart of Embodiment 5;

FIG. 13 shows a switching transistor driver circuit according to Embodiment 6 of the present invention;

FIG. 14 is a timing chart of Embodiment 6;

FIG. 15 shows a conventional switching transistor driver circuit;

FIG. 16 shows a specific circuit example of a pulse oscillator 214 of a conventional example and edge detection circuits 37 and 38 of Embodiment 5 of the present invention;

FIG. 17 is a timing chart showing the pulse oscillator 214 of the conventional example;

FIG. 18 is a circuit diagram showing one of pulse filters 219 of the conventional example;

FIG. 19 is a timing chart of FIG. 18;

FIG. 20 is a connection diagram of an inductive load;

FIG. 21 is a connection diagram of a capacitive load; and

FIG. 22 is a connection diagram of another capacitive load.

Claims

1. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled, wherein the low side circuit is switched based on a second input pulse signal fed to a low side input terminal and generates the control pulse signal for turning on/off the low side switching transistor, andthe high side circuit is configured such that a latch circuit is set/reset by each edge detection pulse having detected leading edge and trailing edge of a first input pulse signal fed to a high side input terminal, the control pulse signal for turning on/off the high-side switching transistor is generated, and the latch circuit is reset in one of a period during which a terminal voltage of the output terminal is inverted or a period immediately after the inversion.

2. The switching transistor driver circuit according to claim 1, wherein the latch circuit is reset when the low-side switching transistor is turned on after the high-side switching transistor is turned off or in a period during which current passes through the output terminal from the low-side switching transistor after the high-side switching transistor is turned off.

3. The switching transistor driver circuit according to claim 1, wherein the low side circuit comprises: a delay circuit which is disposed on a path from the low side input terminal to the low-side switching transistor to make a correction of a signal delay time in the high side circuit and contributes to formation of the control pulse signal for turning on/off the low-side switching transistor,a reset pulse generation circuit for preventing a malfunction, the reset pulse generation circuit delaying the second input pulse signal fed from the low side input terminal and generating a reset signal for the high side circuit,the high side circuit comprises:a first edge detection circuit for detecting the leading edge of the first input pulse signal and a second edge detection circuit for detecting the trailing edge of the first input pulse signal,the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the reset input being also fed with a signal obtained by changing, in the level shift circuit, a voltage level of the output signal from the reset pulse generation circuit,the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor, and the high-side switching transistor is driven based on an output signal from the latch circuit.

4. The switching transistor driver circuit according to claim 3, wherein the level shift circuit changes the voltage level of the output signal from the reset pulse generation circuit and the voltage levels of the first and second edge signals outputted from the first and second edge detection circuits.

5. The switching transistor driver circuit according to claim 3, wherein the reset pulse generation circuit generates a reset signal for the latch circuit in synchronization with one of a leading edge or a trailing edge of the second input pulse signal in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.

6. The switching transistor driver circuit according to claim 3, wherein the reset pulse generation circuit is fed with an output signal of the first delay circuit as an input signal, the delay circuit is made up of the first delay circuit fed with the second input pulse signal as an input signal and a second delay circuit fed with the output signal of the first delay circuit as an input signal, and the low-side switching transistor is driven based on an output signal of the second delay circuit.

7. The switching transistor driver circuit according to claim 3, wherein the delay circuit is made up of first and second delay circuits, each being fed with the second input pulse signal as an input signal, the reset pulse generation circuit is fed with an output signal of the first delay circuit having a shorter delay time than the second delay circuit, andthe low-side switching transistor is driven based on an output signal of the second delay circuit.

8. The switching transistor driver circuit according to claim 3, further comprising a delay circuit between inputs of the first and second edge detection circuits and the high side input terminal.

9. The switching transistor driver circuit according to claim 3, wherein in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion, a generator of a reset signal inputted to the latch circuit sets timing of start of reset in response to the signal from the second edge detection circuit for switching the high-side switching transistor from on to off, the reset is completed in synchronization with one of a leading edge or a trailing edge of the second input pulse signal, a reset pulse width serving as a reset period is set by the output signal of the reset pulse generation circuit, and a continuous reset pulse signal is generated by delaying a rear edge of the output signal of the second edge detection circuit for detecting the trailing edge of the first input pulse signal or advancing a front edge of a reset pulse signal of an output of the reset pulse generation circuit.

10. The switching transistor driver circuit according to claim 1, further comprising: a delay circuit constructed on a path from the low side input terminal to the low-side switching transistor,a reset pulse generation circuit for preventing a malfunction, the reset pulse generation circuit being fed with an input signal from the delay circuit, anda first edge detection circuit for detecting the leading edge of the first input pulse signal,wherein the latch circuit has a set input fed with a signal obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a reset input fed with a signal obtained by changing, in the level shift circuit, a voltage level of an output signal from the reset pulse generation circuit,the latch circuit has a minimum reference potential terminal connected to the low potential side of the high-side switching transistor, andthe high-side switching transistor is driven based on an output signal from the latch circuit.

11. The switching transistor driver circuit according to claim 10, wherein the reset pulse generation circuit generates a reset signal for the latch circuit in synchronization with one of a leading edge or a trailing edge of the second input pulse signal in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.

12. The switching transistor driver circuit according to claim 10, wherein the reset pulse generation circuit is fed with an output signal of the first delay circuit as an input signal, the delay circuit is made up of the first delay circuit fed with the second input pulse signal as an input signal and a second delay circuit fed with the output signal of the first delay circuit as an input signal, and the low-side switching transistor is driven based on an output signal of the second delay circuit.

13. The switching transistor driver circuit according to claim 10, wherein the delay circuit is made up of first and second delay circuits, each being fed with the second input pulse signal as an input signal, the reset pulse generation circuit is fed with an output signal of the first delay circuit having a shorter delay time than the second delay circuit, andthe low-side switching transistor is driven based on an output signal of the second delay circuit.

14. The switching transistor driver circuit according to claim 1, further comprising: a first delay circuit constructed on a path from the low side input terminal to the low-side switching transistor,a first edge detection circuit for detecting the leading edge of the pulse signal fed to the high side input terminal, anda second edge detection circuit for detecting the trailing edge of the pulse signal fed to the high side input terminal,wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on the output signal of the latch circuit, andthe signal from the second edge detection circuit is inputted as a reset signal to the latch circuit by delaying the signal from the second edge detection circuit or delaying a rear edge of the signal from the second edge detection circuit, the rear edge indicating timing of end of reset, in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.

15. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled, the switching transistor driver circuit comprising:a first delay circuit constructed on a path from a low side input terminal to the low-side switching transistor,a first edge detection circuit for detecting a leading edge of a pulse signal fed to a high side input terminal, anda second edge detection circuit for detecting a trailing edge of the pulse signal fed to the high side input terminal,wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on an output signal of the latch circuit, andin a period during which the high-side switching transistor is turned off by the pulse signal fed to the high side input terminal, the set input to the latch circuit is prohibited on an input side of the level shift circuit by using one of a first period during which a signal for turning on the low-side switching transistor is inputted from the low side input terminal and a second period obtained by delaying the first period.

16. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled, the switching transistor driver circuit comprising:a first delay circuit constructed on a path from a low side input terminal to the low-side switching transistor,a first edge detection circuit for detecting a leading edge of a pulse signal fed to a high side input terminal, and a second edge detection circuit for detecting a trailing edge of the pulse signal fed to the high side input terminal,wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on an output signal of the latch circuit, andin a period during which the low-side switching transistor is turned off by a pulse signal fed to the low side input terminal, an on signal to the low-side switching transistor is prohibited on an input path from an output of the first delay circuit to the low-side switching transistor by using one of a third period during which the pulse signal fed from the high side input terminal is inputted to turn on the high-side switching transistor or a fourth period obtained by delaying the third period.