The present application relates to switching voltage regulators, in particular estimating input power of switching voltage regulators.
In many electrical systems a load is connected to a source through a switching power converter. It is advantageous to know how the actions of the load affect the power strain on the incoming source. For example, knowledge of the regulator input power is typically used for telemetry purposes, fault monitoring and system optimization. The power required from the source equals that consumed by the load plus losses within the switching power converter. If there is no loss between the source and the power converter, the power demanded from the source equals the input power to the converter. Input voltage to a converter is an existing measurement required for protection and possibly control of the converter. Then, only input current must be known to obtain the input power of the power converter. Obtaining the input current value is considerably more involved than voltage measurement if accuracy is to be maintained without adversely affecting efficiency. In addition, obtaining the input current generally requires the addition of a series element such as a sense resistor in order to obtain a measurement of the current through the series element.
Input power is the product of input voltage and input current. Input voltage is an existing telemetry value required for power supply protection and control. Input current is measured or estimated. In the case of measurement, external components are required on the board, increasing cost and board area consumed. In terms of estimation, the input current estimate relies heavily on the accuracy of the sensed input voltage. The input voltage rail is typically noisy which leads to incorrect current estimation and incorrect input voltage reporting. A combination of erroneous current and voltage estimates results in erroneous input power reporting. Hence, a more accurate switching voltage regulator input power estimation technique is desirable.
According to an embodiment of a method of estimating input power of a voltage regulator, the method comprises: estimating output power of the voltage regulator based on output voltage and output current of the voltage regulator; estimating power loss of the voltage regulator; and estimating input power of the voltage regulator based on the estimated output power and the estimated power loss.
According to an embodiment of a voltage regulator, the voltage regulator comprises a power stage and a controller. The power stage is configured to deliver output current to a load through an inductor. The controller is operable to estimate output power of the voltage regulator based on output voltage and output current of the voltage regulator, estimate power loss of the voltage regulator and estimate input power of the voltage regulator based on the estimated output power and the estimated power loss.
According to another embodiment of a voltage regulator controller, the voltage regulator comprises an input power estimator operable to: estimate output power of the voltage regulator based on output voltage and output current of the voltage regulator; estimate power loss of the voltage regulator; and estimate input power of the voltage regulator based on the estimated output power and the estimated power loss.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Embodiments described herein provide for estimating input power of a switching voltage regulator without measuring the regulator input current. As a result, no additional components are required for estimating the voltage regulator input power. In addition, the input power estimate has a small dependence on input voltage. Switching power converters are required to know their output voltage and current with a high degree of accuracy for control and protection requirements. Using these known quantities and information indicating how hard the converter is working to maintain regulation, an estimate of how much power is being consumed by the system can be determined. That is, losses and input power are estimated based on the output power and control effort of the regulator. In one case, input voltage sensing is used but the potential downfalls can be mitigated by having a loose reliance on its accuracy. In other cases, input power and loss estimates are not based on input voltage sensing.
Each phase 104 has a high-side transistor (Q1) and a low-side transistor (Q2) for coupling to the load 107 through the corresponding inductor. The high-side transistor of each phase 104 switchably connects the load 107 to an input voltage (Vin) of the switching voltage regulator 100, and the corresponding low-side transistor switchably connects the load 107 to ground at different periods. N phases are shown in
The controller 106 regulates the voltage (Vout) delivered to the load 107 by the power stage 102, by adjusting the phase currents delivered to the load 107. The controller 106 can include a pulse width modulator (PWM) 108 for switching each phase 104 of the power stage 102 via a corresponding PWM control signal (PWM1, PWM2, . . . , PWMn) so that the power stage 102 sources or sinks current to the load 107 through the corresponding inductor and the high-side or low-side transistor. When the PWM control signal is at a logic level high, the high-side transistor is placed in a conductive state, the inductor current is sourced or sunk through the high-side transistor, and the current through the inductor increases for the duration. This is generally referred to as the ‘on-time’ and the power stage 102 is considered to be ‘turned on’. When the PWM control signal is at a logic level low, the low-side transistor is placed in a conductive state, current is sourced or sunk from the low-side transistor, and the current through the inductor decreases for the duration. This is generally referred to as the ‘off-time’ and the power stage 102 is considered to be ‘turned off’. When the PWM control signal is at a trivalent or high impedance logic level (the PWM control signal is neither high nor low), both the high-side and the low-side transistors are placed in a non-conductive state, current is sourced or sunk through either the low-side or high side transistor body diodes, and the magnitude of the current through the inductor decreases towards zero. This is generally referred to as the ‘HiZ-time’ or ‘inactive time’ and the power stage 102 is considered to be in ‘High Z’ or inactive.
In DCM (discontinuous conduction mode), the low-side transistor is not allowed to be conductive when the inductor current reaches zero. The cycle then consists of an on-time, followed by an off-time, followed by a HiZ time. During the HiZ time, the inductor current approaches zero and does not change for the duration of the cycle once it is zero. As a result, the inductor current does reach zero during part of the switching cycle in DCM. In CCM (continuous conduction mode), the inductor current does not stop at zero between switching cycles. That is in DCM, the inductor current is always positive or zero and in CCM the inductor current can be positive or negative but does not stay at zero. The inductor current can cross zero and go negative e.g. at no-load, and the voltage regulator 100 can operate in CCM where the triangular inductor current is centered at zero.
In either CCM or DCM, drivers 110 of the power stage 102 provide gate drive signals to the gates of the high-side and low-side transistors of the corresponding phases 104 in response to the PWM control signals provided by the controller 106. The activation state of the phases 104 and the duty cycle of the high-side and low-side transistors are determined at least in part based on the output voltage (Vout) applied to the load 107 so that the switching voltage regulator 100 can react as quickly and reliably as possible to changing load conditions.
The controller 106 can manage changes from one reference voltage to another. The controller 106 can also determine errors between the output voltage (Vout) and a reference voltage, and convert the error voltage into a digital representation provided to the PWM 108 for modifying the switching cycle of the phases 104 e.g. by adjusting the duty cycle. Such voltage regulation functions are standard in typical digitally-controlled switching voltage regulators, and therefore no further explanation is given in this regard.
In addition to regulating the voltage delivered to the load 107, the controller 106 estimates the input power (Pin) of the switching voltage regulator 100 without measuring the regulator input current. In one embodiment, the controller 106 further includes input voltage ADC (analog-to-digital conversion) sense circuitry 112 for measuring the input voltage (Vin) to the power stage 102. The controller 106 also monitors the phase currents delivered by the phases 104 to the load 107 e.g. by measuring the phase currents (ILn) injected into the corresponding inductors by DCR sensing. The controller 106 estimates the total current (Iout) delivered to the load 107 by the switching voltage regulator 100 based on the phase currents measured by DCR sensing. The controller 106 can estimate the input power (Pin) of the switching voltage regulator 100 based on the measured input voltage and measured output current. The controller 106 can measure the regulator output current using any standard current sense circuitry.
For example in the embodiment shown in
In both embodiments of
The controller 106 also includes an input power estimator 120 for estimating the input power of the switching voltage regulator 100 without having to measure the regulator input current.
The output voltage Vout of the voltage regulator 100 can be measured with output voltage ADC sense circuitry 122 of the controller 106. The output current Iout of the voltage regulator 100 can be measured with the current ADC sense circuitry 114. The measured output current Iout represents a summation of the current output by each active phase 104 of the switching voltage regulator 100. The input power estimator 120 can then calculate the power loss (Ploss) of the voltage regulator 100 based on the measured output voltage and measured output current. In another embodiment, the output voltage (Vout) of the voltage regulator 100 is measured with the output voltage ADC sense circuitry 122, the output current (Iout) of the voltage regulator 100 is measured with the current ADC sense circuitry 114, and the input voltage (Vin) to the power stage 102 is measured with the input voltage ADC sense circuitry 112.
The controller 106 also measures a controller parameter which is indicative of a control signal generated by the controller 106. The control signal is provided to the power stage 102 for controlling operation of the power stage 102. The input power estimator 120 then calculates the power loss (Ploss) of the voltage regulator 100 based on the measured output voltage, output current, input voltage, and controller parameter. For example, the controller parameter can be measured by sampling or averaging the PWM duty cycle of the controller 106. In another embodiment, the controller parameter can be measured by sampling or averaging the output of the loop compensation filter 118. In each case, the input power of the switching voltage regulator 100 is estimated without having to measure the regulator input current.
duty·Vin=Vout+Iout·Rloss (1)
where Vin is the measured regulator input voltage, Iin is the regulator input current, ‘duty’ is the duty cycle of the power stage, duty·Vin corresponds to the input power, Vout is the measured regulator output voltage, and Iout is the measured total regulator output current. Equation (1) can be expressed as:
Iin·Vin=Iout·Vout+Iout2·Rloss (2)
Substituting Iin=Iout·duty into equation (2) yields the following first-order model for the regulator input power:
where
is a term which represents the power loss of the switching voltage regulator 100.
The input power expression given by equation (3) is based on a single loss term Rloss which in lumps together linear and non-linear variables. This simple first-order model can be expressed in different ways as described in more detail below to yield a more accurate estimation of the regulator input power.
In one embodiment, the input power estimator 120 provides an estimate of the regulator input power (Pin) as given by:
where Iout is the output current of the voltage regulator 100 measured with the current ADC sense circuitry 114 and represents a summation of the current output by each active phase 104 of the switching voltage regulator 100, Vout is the output voltage of the voltage regulator 100 measured with the output voltage ADC sense circuitry 122, Vin is the input voltage of the voltage regulator 100 measured with the input voltage ADC sense circuitry 112, and ‘duty’ is the duty cycle of the voltage regulator 100 as determined by the controller 106. Also, α1 is a scaling (gain) factor applied to the voltage regulator output power estimate Pout, α2 is a scaling (gain) factor applied to the voltage regulator power loss term Ploss which is represented by
in equation (4), and Δ is a power offset term.
As such, the input power Pin of the voltage regulator 100 can be estimated by adding a scaled estimate of the regulator output power, a scaled estimate of the regulator power loss and a power offset. For example in equation (4), the estimated output power Pout of the voltage regulator 100 is multiplied by a first scale factor α1 to yield the scaled estimate of the output power. The estimated power loss Ploss of the voltage regulator 100 is scaled by a second scale factor α2 to yield the scaled estimate of the power loss. The scaling factors α1 and α2 and the power offset Δ at least partly account for the linear and non-linear variables lumped into the simplified Rloss term illustrated in
The model complexity can increase with minimal increase of computational complexity. For example, the second scaling factor α2 can be approximated as a linear function of the output current Iout by simplifying reliance on the regulator duty cycle. Also, terms that include Vout/duty can be replaced by the input voltage Vin measurement to further reduce computational complexity.
In another embodiment, equation (4) is further manipulated to reduce the influence of the input voltage measurement Vin on the input power estimate as given by:
According to this model of the voltage regulator input power, the influence of the input voltage measurement Vin on the input power estimate is reduced for the regulator power loss term
If there is zero error in all measurements, then the input power estimate given by equation (4) equals the input power estimate given by equation (5). In one embodiment, the first scale factor α1 is 1 and the second scale factor α2 is 1. The power offset Δ can be 0 or non-zero. The first and second scale factors α1, α2 can be programmable, as can be the power offset Δ.
Equation (6) below is an expression for the voltage regulator input power during CCM. When the switching voltage regulator 100 operates in CCM, the inductor current may cross zero, but does not stay at zero between switching cycles.
Pin=Pout+Ploss
Pin=Pout+PHS(Q1)+PLS(Q2)+PLo+PCo
PHS(Q1)=Pswitch,on+Pswitch,off+Pconduction+Pgate+PCoss
PLS(Q2)=Pdiode+Pconduction+Pgate
PLo=Lconduction+Pcore
Pin=α1·Pout+Ioutα2Veq(duty,Iout)+NphΔ (6)
where PHS(Q1) is the power loss component for the high-side transistor Q1, PLS(Q2) is the power loss component for the low-side transistor Q2, PLo is the power loss component for the output inductor Lout, PCo is the power loss component for the output capacitor Cout, Pswitch,on is the power loss component for transistor Q1 while transitioning from the off-state to the on-state, Pswitch,off is the power loss component for transistor Q1 transitioning from the on-state to the off-state, Pconduction is a conduction power loss component, Pgate is a gate (input) capacitance power loss component for each transistor Q1/Q2, PCoss is an output capacitance power loss component, and Pdiode is a diode power loss component. The expression Ioutα2Veq (duty, Iout) in equation (6) represents the power loss term for the switching voltage regulator 100.
The variable Nph corresponds to the number of phases 104 included in the power stage 102. As such, the power offset Δ can be scaled based on the number of active phases 104. Alternatively, a different value is used for the power offset Δ for each combination of active phases 104 (Nph=1, Nph=2, etc.). The power offset Δ also can be updated when the load 107 regulated by the voltage regulator 100 changes.
In one embodiment, the expression Veq(duty, Iout) in equation (6) is expressed as given by:
where Veq(duty, Iout) is an equivalent voltage term, 2VFtdFsw is a diode loss term,
is a DC conduction loss term,
is a switching loss term, Vf is diode forward voltage, td is the dead-time between the high-side and low-side transistors Q1/Q2, FSW is the switching frequency of the power stage transistors Q1/Q2 in CCM, Rds,HS is the on-state resistance of the high-side transistor Q1, Rds,LS is the on-state resistance of the low-side transistor Q2, DCR is the non-ideal DC resistance of the output inductor Lout, and tSW is the time to switch the high-side transistor Q1 on or off (not the inverse of switching frequency).
In general, the power offset term Δ can be a per-phase quantity. The regulator controller 106 is aware of its phase count and can adjust Δ accordingly as explained above. The power offset term Δ can be different for CCM and PFM (pulse frequency modulation) mode which is also known as DCM. The controller 106 is aware of the operating state and can adjust Δ accordingly. The first and second scale (gain) factors α1 and α2 also have phase count and operating mode dependencies. The controller 106 can adjust α1 and/or α2 based on phase count and CCM/PFM (DCM) mode. In PFM (DCM), on-time reduction can result in further adjustments to α1, α2 and/or Δ. For example, on-time reductions from 100% to e.g. 75% to e.g. 50% can result in three separate α1, α2 and Δ values. These values can be stored in the data registers 124 accessible by the controller 106.
In one embodiment for CCM, the power offset term Δ is expressed as given by:
where VgsFsw(Qg,HS+Qg,LS) represents gate conduction loss of the high-side and low-side transistors, kΔILxFswy represents core loss,
represents AC conduction loss, and
represents output capacitance loss. Also, Rds,HS is the drain-to-source resistance of the high-side transistor Q1, Rds,LS is the drain-to-source resistance of the low-side transistor Q2, Qg,HS is the gate charge of the high-side transistor Q1, Qg,LS is the gate charge of the low-side transistor Q2, k is a constant term for the inductor magnetic material, and Coss is the output capacitance of the high-side transistor Q1.
Equation (9) below is an expression for the voltage regulator input power during DCM (PFM) of operation. When the switching voltage regulator 100 operates in DCM (PFM), the inductor current of the voltage regulator 100 reaches zero between switching cycles. The input power estimator 120 provides an estimate of the voltage regulator input power Pin in DCM (PFM) as given by:
Pin=Pout+Ploss
Pin=Pout+PHS(Q1)+PLS(Q2)+PLo+PCo
PHS(Q1)=Pswitch,off+Pconduction+Pgate
PLS(Q2)=Pdiode+Pconduction+Pgate
Pin=Pout+αPFMIoutVeq.PFM(FPFM,Iout)+ΔPFM (9)
where ΔPFMIoutVeq,PFM(FPFM, Iout) relates the regulator duty cycle to input power and ΔPFM is a frequency/inductor ripple loss offset term.
In one embodiment, the expression Veq,PFM(FPFM, Iout) in equation (9) is expressed as given by:
where
represents diode loss,
represents conduction loss,
represents switching loss, and FPFM is the switching frequency in PFM (DCM).
In one embodiment for DCM (PFM), the power offset term ΔPFM is expressed as given by:
ΔPFM=VgsFPFM(Qg,HS+Qg,LS)+kΔILxFPFMy (11)
where VgsFPFM(Qg,HS+Qg,LS) represents gate loss and kΔILxFPFMy represents core loss.
In DCM (PFM) mode of operation, Veq and duty cycle are functions of the PFM switching frequency FPFM which in turn is a function of the regulator output current Iout. For more accurate results, Veq and duty cycle are updated when the load 107 changes. The scaling (gain) factor αPFM can be continually adjusted to further reduce calculation complexity.
In one embodiment, the scaling factors and power offset previously described herein are determined by measuring the input power of the voltage regulator 100 during a verification process. The scaling factors and power offset are adjusted until the output power reported by the voltage regulator 100 during the verification process is within a predetermined tolerance of the measured input power. Alternatively, the scaling factors and power offset can be computed e.g. in accordance with the equations presented herein. In either case, the scaling factors and power offset can be stored in the data registers 124 accessible by the controller 106.
Described next is an embodiment of determining initial values for the scaling factors and power offset. The first order model represented by equations (1) though (3) lumps multi-variable loss elements as resistive losses. Based on this simple model, it is then unclear what initial values for the scaling factors and power offset should be used to tune the input power estimator 120. One starting point is a function of the individual design e.g. the power stage transistors, drivers and inductors used, the switching frequency, the nominal operating voltages, etc. For example, the regulator output power Pout can be expressed as given by:
By setting α3=1, like terms can be collected as given by:
The scaling (gain) term al can be expressed as given by:
and η is efficiency.
In any switching voltage regulator design, the devices and their parameters are known. Efficiency at some input voltage Vin, output voltage Vout and output current Iout is known/simulated/calculated. The scaling factors and power offset can be calculated at the known operating point.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
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