Claims
- 1. A method of generating boolean expressions for a cyclic redundancy check circuit comprising:a) generating a loop iteration to provide symbolic simulation of a circuit; b) executing the loop iteration for each bit of a data stream to calculate a symbolic expression for a cyclic redundancy check in each iteration; c) generating a boolean expression for each symbolic expression; and d) generating circuit definition language for the boolean expressions.
- 2. The method as recited in claim 1 wherein the circuit definition language generates a ripple tree implementation of the expressions.
- 3. The method as recited by claim 1 wherein the circuit definition language generates a balanced tree implementation of the expressions.
- 4. The method as recited by claim 3 wherein the balanced tree has greater than 8 inputs.
- 5. The method as recited by claim 3 wherein the balanced tree has 16 inputs.
- 6. The method as recited by claim 3 wherein the balanced tree has 32 inputs.
- 7. The method as recited in claim 3 wherein the balanced tree comprises a plurality of XOR gates.
- 8. An apparatus to generate boolean expressions for a cyclic redundancy check circuit comprising:a) means for generating a loop iteration to provide symbolic simulation of a circuit; b) means for executing the loop iteration for each bit of a data stream to calculate a symbolic expression for a cyclic redundancy check in each iteration; c) means for generating a boolean expression for each symbolic expression; and d) means for generating circuit definition language for the boolean expressions.
- 9. The apparatus of claim 8, wherein the means for generating circuit definition language generates a ripple tree implementation of the expressions.
- 10. The apparatus of claim 8 wherein the means for generating circuit definition language generates a balanced tree implementation of the expressions.
- 11. The apparatus of claim 10 wherein the balanced tree has greater than 8 inputs.
- 12. The apparatus of claim 10 wherein the balanced tree has 16 inputs.
- 13. The apparatus of claim 10 wherein the balanced tree has 32 inputs.
- 14. The apparatus of claim 10 wherein the balanced tree comprises a plurality of XOR gates.
- 15. A machine-readable medium comprising at least one instruction to generate boolean expressions for a cyclic redundancy check circuit, which when executed by a processor, causes the processor to perform operations comprising:a) generating a loop iteration to provide symbolic simulation of a circuit; b) executing the loop iteration for each bit of a data stream to calculate a symbolic expression for a cyclic redundancy check in each iteration; c) generating a boolean expression for each symbolic expression; and d) generating circuit definition language for the boolean expressions.
- 16. The machine-readable medium of claim 15 wherein the means for generating circuit definition language generates a ripple tree implementation of the expressions.
- 17. The machine-readable medium of claim 15 wherein generating circuit definition language generates a balanced tree implementation of the expressions.
- 18. The machine-readable medium of claim 17 wherein the balanced tree has greater than 8 inputs.
- 19. The machine-readable medium of claim 17 wherein the balanced tree has 16 inputs.
- 20. The machine-readable medium of claim 17 wherein the balanced tree has 32 inputs.
- 21. The machine-readable medium of claim 17 wherein the balanced tree comprises a plurality of XOR gates.
- 22. A signal for generating boolean expressions for a cyclic redundancy check circuit comprising:a) a first source code segment to generate a loop iteration to provide symbolic simulation of a circuit; b) a second source code segment to execute the loop iteration for each bit of a data stream to calculate a symbolic expression for a cyclic redundancy check in each iteration; c) a third source code segment to generate a boolean expression for each symbolic expression; and d) a fourth source code segment to generate circuit definition language for the boolean expressions.
- 23. The signal of claim 22 wherein the fourth source code to generate circuit definition language generates a ripple tree implementation of the expressions.
- 24. The signal of claim 22 wherein the fourth source code to generate circuit definition language generates a balanced tree implementation of the expressions.
- 25. The signal of claim 24 wherein the balanced tree has greater than 8 inputs.
- 26. The signal of claim 24 wherein the balanced tree has 16 inputs.
- 27. The signal of claim 24 wherein the balanced tree has 32 inputs.
- 28. The signal of claim 24 wherein the balanced tree comprises a plurality of XOR gates.
- 29. A system to generate boolean expressions for a cyclic redundancy check circuit comprising:a) a first sub-system to generate a loop iteration to provide symbolic simulation of a circuit; b) a second sub-system to execute the loop iteration for each bit of a data stream to calculate a symbolic expression for a cyclic redundancy check in each iteration; c) a third sub-system to generate a boolean expression for each symbolic expression; and d) a fourth sub-system to generate circuit definition language for the boolean expressions.
- 30. The system of claim 29 wherein the fourth sub-system to generate circuit definition language generates a ripple tree implementation of the expressions.
- 31. The system of claim 29 wherein the fourth sub-system to generate circuit definition language generates a balanced tree implementation of the expressions.
- 32. The system of claim 31 wherein the balanced tree has greater than 8 inputs.
- 33. The system of claim 31 wherein the balanced tree has 16 inputs.
- 34. The system of claim 31 wherein the balanced tree has 32 inputs.
- 35. The system of claim 31 wherein the balanced tree comprises a plurality of XOR gates.
RELATED APPLICATIONS
This application claims benefit of co-pending U.S. provisional application Ser. No. 60/062,923 titled Symbol Based Algorithm for Hardware Implementation of Cyclic Redundancy Check filed Oct. 20, 1997.
US Referenced Citations (4)
Non-Patent Literature Citations (2)
Entry |
Helness, “Implementation of a parallel Cyclic Redundancy Check Generator”, Computer Design, Mar. 1974, pp. 91-96, Mar. 1974.* |
Pei et al., “High-Speed Parallel CRC Circuits in VLSI”, IEEE Trans. on Communications, vol. 40, No. 4, Apr. 1992, pp. 653-657, Apr. 1992. |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/062923 |
Oct 1997 |
US |