The present invention relates to a symbol timing determining device and method, especially to a symbol timing determining device and method for a communication system.
In an Orthogonal Frequency-Division Multiplexing (OFDM) communication system using multiple antennas for communication, beamforming is a signal processing technique for directional signal transmission or reception; more specifically, this technique is achieved by combining elements in the multiple antennas in a way such that signals at particular phase angles experience constructive interference while others experience destructive interference. In order to prevent an unexpected antenna beamforming effect and nonuniform transmission in the air, a transmitter of the OFDM communication system makes use of Cyclic Shift Diversity (CSD) technique to increase spatial diversity. For instance, as shown in
Some literatures in re CSD technique research are listed below:
An object of the present invention is to provide a symbol timing determining device and method capable of preventing the problems of the prior arts.
An object of the present invention is to provide a symbol timing determining device and method capable of determining whether a symbol timing is related to a pseudo path and thereby selecting a correct symbol timing favorable for the performance of a receiver.
The present invention discloses a symbol timing determining device capable of preventing erroneous symbol timing synchronization of a communication system. An embodiment of the symbol timing determining device includes a symbol timing detecting circuit, an estimation signal generating circuit, a channel impulse response signal generating circuit, a power measuring circuit and a decision circuit. The symbol timing detecting circuit is configured to detect a reception signal to obtain a first symbol timing and configured to shift the first symbol timing to obtain a second symbol timing. The estimation signal generating circuit is configured to process the reception signal according to the first symbol timing to obtain a first channel estimation frequency-domain signal and configured to process the reception signal according to the second symbol timing to obtain a second channel estimation frequency-domain signal. The channel impulse response signal generating circuit is configured to generate a first channel estimation impulse response time-domain signal according to the first channel estimation frequency-domain signal and configured to generate a second channel estimation impulse response time-domain signal according to the second channel estimation frequency-domain signal. The power measuring circuit is configured to measure first energy of the first channel estimation impulse response time-domain signal according to a first predetermined signal region of the first channel estimation impulse response time-domain signal, and configured to measure second energy of the second channel estimation impulse response time-domain signal according to a second predetermined signal region of the second channel estimation impulse response time-domain signal. The decision circuit is configured to adopt one of the first symbol timing and the second symbol timing by determining whether a relation between the first energy and the second energy conforms to a predetermined relation.
The present invention also discloses a symbol timing determining method capable of preventing erroneous symbol timing synchronization of a communication system. An embodiment of the symbol timing determining method includes the following steps: receiving a reception signal to obtain a first symbol timing; processing the reception signal according to the first symbol timing to obtain a first channel estimation frequency-domain signal; generating a first channel estimation impulse response time-domain signal according to the first channel estimation frequency-domain signal; measuring first energy of the first channel estimation impulse response time-domain signal according to a first predetermined signal region of the first channel estimation impulse response time-domain signal; shifting the first symbol timing to obtain a second symbol timing; processing the reception signal according to the second symbol timing to obtain a second channel estimation frequency-domain signal; generating a second channel estimation impulse response time-domain signal according to the second channel estimation frequency-domain signal; measuring second energy of the second channel estimation impulse response time-domain signal according to a second predetermined signal region of the second channel estimation impulse response time-domain signal; determining whether a relation between the first energy and the second energy conforms to a predetermined relation; when the relation conforms to the predetermined relation, adopting the second symbol timing; and when the relation does not conform to the predetermined relation, adopting the first symbol timing.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.
Orthogonal Frequency-Division Multiplexing (OFDM) technique is widely used in a communication system such as an IEEE 802.11a/g/n/ac/ax system or a Long Term Evolution (LTE) system. An OFDM communication system needs highly accurate setting of carrier frequency offset and symbol timing synchronization. In order to increase the performance of the communication system, a transmitter of the communication system puts a preamble in the front of a frame so that a receiver can use the well-defined preamble to estimate the carrier frequency offset and detect the symbol timing and thereby execute calibration to the carrier frequency offset and/or the symbol timing before receiving the data payload of the frame. An instance of the format of the above-mentioned preamble is shown in
A conventional method for symbol timing synchronization carries out cross correlation calculation to a known LTS and a reception signal in the time-domain as shown in the following equation 1:
ε(T)=Σn=0L-1r(τ+n)s*(n) (Eq. 1),
in which τ is a time variable, r(τ+n) is the reception signal, s*(n) is the LTS, the superscript “*” stands for complex conjugate, L is the length of the LTS, and n is the sampling point. When |ε(τ)| is greater than a predetermined value, the τ is the detected symbol timing and the ε(τ) is the channel impulse response (e.g.,
For better understanding, the following description is written on the basis of a transmitter carrying out CSD transmission by two antennas. People of ordinary skill in the art can derive the modifications of the present invention in accordance with the present disclosure and the existing knowledge.
In order to determine the symbol timing τ is τ′0 or τ0, the present invention discloses a symbol timing determining device for this determination.
The symbol timing detecting circuit 410 is configured to detect a reception signal (e.g., a signal outputted by an analog-to-digital converter of a receiver of a communication system) according to Eq. 1 and thereby obtain a first symbol timing τ1. The symbol timing detecting circuit 410 is further configured to shift the first symbol timing τ1 to obtain a second symbol timing τ2, in which the shift amount of the above-mentioned shift operation is related to the CSD time shift adopted by a transmitter transmitting a signal that is received as the reception signal. In an exemplary implementation, the timing difference tτ (i.e., symbol timing shift) between the first symbol timing τ1 and the second symbol timing τ2 is 150 nanosecond or 200 nanosecond; more specifically, according to the aforementioned Table 1, when the number of antennas is not greater than four, the maximum difference between the CSD time shifts of different transmit chains is 150 nanosecond or 200 nanosecond, and thus it is logical to assume that the timing difference between a pseudo path caused by CSD technique and a real path is 150 nanosecond (when a transmitter uses four antenna for CSD transmission) or 200 nanosecond (when a transmitter uses two or three antennas for CSD transmission) and then set the timing difference tτ accordingly. Since a receiver may not ascertain the number of antennas for the transmitter carrying out CSD transmission, every possible timing difference (e.g., 150 nanosecond and 200 nanosecond) could be tried to find out the best option.
The estimation signal generating circuit 420 is configured to process the reception signal according to the first symbol timing τ1 to obtain a first channel estimation frequency-domain signal Ĥ1, and configured to process the reception signal according to the second symbol timing τ2 to obtain a second channel estimation frequency-domain signal Ĥ2. The signals generated by the estimation signal generating circuit 420 can be outputted to a backend circuit for the execution of some process (e.g., signal detection process and decoding process of a receiver in a communication system). In an exemplary implementation, the estimation signal generating circuit 420 is a circuit of a receiver in a communication system and operable to carry out the removal of cyclic prefix, the series-to-parallel conversion, the Fast Fourier Transform (FFT) and the channel estimation; more specifically, the estimation signal generating circuit 420 executes FFT to at least a part of the second LTS of the reception signal, which has gone through the series-to-parallel conversion, according to the first symbol timing τ1 and the second symbol timing τ2 obtained by the symbol timing detecting circuit 410, and thereby the estimation signal generating circuit 420 generates a first frequency-domain sequence X1 and a second frequency-domain sequence X2 as shown in the following equation 2:
X1=FFT{r(τ1)}
X2=FFT{r(τ2)} (Eq. 2),
in which r(τ1) is a reception signal sequence starting at the time point τ1 and the length of r(τ1) is 3.2 microsecond, and r(τ2) is a reception signal sequence starting at the time point τ2 and the length of r(τ2) is 3.2 microsecond. Afterwards, the estimation signal generating circuit 420 uses a known long training frequency-domain sequence “S” and the Least Square algorithm to do channel estimation to the frequency-domain sequences X1 and X2 so as to obtain the first channel estimation frequency-domain signal Ĥ1 and the second channel estimation frequency-domain signal Ĥ2 as shown in the following equation 3:
An embodiment of the channel impulse response signal generating circuit 430 is/includes a circuit capable of executing inverse Fast Fourier Transform (iFFT). The channel impulse response signal generating circuit 430 is configured to generate a first channel estimation impulse response time-domain signal ĥ1 and a second channel estimation impulse response time-domain signal ĥ2 according to the first channel estimation frequency-domain signal Ĥ1 and the second channel estimation frequency-domain signal Ĥ2 respectively, which can be expressed as follows:
ĥ1=iFFT{Ĥ1}
ĥ2=iFFT{Ĥ2} (Eq. 4)
In an exemplary implementation, each of ĥ1 and ĥ2 is a channel estimation impulse response time-domain sequence whose length is 3.2 microsecond. If the aforementioned first symbol timing τ1 is a symbol timing of a pseudo path (e.g., the symbol timing ρ′0 in
The power measuring circuit 440 is configured to measure the energy P1 of the first channel estimation impulse response time-domain signal ĥ1 according to a first predetermined signal region of ĥ1. The power measuring circuit 440 is also configured to measure the energy P2 of the second channel estimation impulse response time-domain signal ĥ2 according to a second predetermined signal region of ĥ2. In an exemplary implementation, the range of the first predetermined signal region is equivalent to the range of the second predetermined signal region; for instance, each of the first and the second predetermined signal regions is a region from the aforementioned t0 (e.g., 0.8 microsecond) to the aforementioned t1 (e.g., 2.4 microsecond), and the calculation of the energy P1 and the energy P2 can be expressed as follows:
In an exemplary implementation, if the aforementioned first symbol timing t1 is a symbol timing of a pseudo path (e.g., the symbol timing τ′0 in
The decision circuit 150 is configured to determine whether a relation between the energy P1 of the first channel estimation impulse response time-domain signal and the energy P2 of the second channel estimation impulse response time-domain signal conforms to a predetermined relation and thereby adopt one of the first symbol timing τ1 and the second symbol timing τ2. In an exemplary implementation, when the energy P1 is equal to the energy P2 or the absolute value of the difference between P1 and P2 is not greater than a threshold which can be properly set by one carrying out the present invention, the decision circuit 150 determines that the relation conforms to the predetermined relation and thereby determines that the second symbol timing τ2 is a symbol timing of a real path, and then the decision circuit 150 directly or indirectly (e.g., through the symbol timing detecting circuit 410) has the estimation signal generating circuit 420 (as indicated by the dashed line in
The present invention further discloses a symbol timing determining method capable of preventing erroneous symbol timing synchronization of a communication system. An embodiment of the method includes the following steps as shown in
Since those of ordinary skill in the art can appreciate the details and the modifications of the embodiment of
To sum up, the present invention can determine whether a symbol timing is associated with a pseudo path or a real path and accordingly adopt a correct symbol timing favorable for the performance of a receiver in a communication system.
The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of present invention are all consequently viewed as being embraced by the scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 107101022 A | Jan 2018 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 10225034 | Wigren | Mar 2019 | B2 |
| 10567134 | Schelstraete | Feb 2020 | B1 |
| 20070217524 | Wang et al. | Sep 2007 | A1 |
| 20120281556 | Sayana | Nov 2012 | A1 |
| 20130136198 | Chavali et al. | May 2013 | A1 |
| 20180365975 | Xu | Dec 2018 | A1 |
| 20190028304 | Rode | Jan 2019 | A1 |
| Entry |
|---|
| Yu-Zhen Chen, “Interoperable Symbol Timing Synchronization Algorithm between IEEE 802.11n and IEEE 802.11ag”, Jul. 2012, National Taipei University of Technology. |
| Fang Yuan, “Symbol timing synchronization for IEEE 802.11n WLAN systems”, Jul. 2013, vol. 21 No. 13, Electronic Design Engineering. |
| “Taiwan IPO, office action for the TW patent application 107101022 (no English translation is available) dated Oct. 22, 2018 (6 pages)”. |
| M. Cho, et al., “Symbol Timing Synchronization for IEEE 802.11n WLAN Systems,” IEEE 2009 First Asian Himalayas International Conference on Internet, Nov. 3-5, 2009. |
| Number | Date | Country | |
|---|---|---|---|
| 20190215143 A1 | Jul 2019 | US |