Patent Application
20250173906
The present disclosure describes aspects generally related to mesh coding.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Image/video compression can help transmit image/video data across different devices, storage and networks with minimal quality degradation. In some examples, video codec technology can compress video based on spatial and temporal redundancy. In an example, a video codec can use techniques referred to as intra prediction that can compress an image based on spatial redundancy. For example, the intra prediction can use reference data from the current picture under reconstruction for sample prediction. In another example, a video codec can use techniques referred to as inter prediction that can compress an image based on temporal redundancy. For example, the inter prediction can predict samples in a current picture from a previously reconstructed picture with motion compensation. The motion compensation can be indicated by a motion vector (MV).
Advances in three-dimensional (3D) capture, modeling, and rendering have promoted 3D content across various platforms and devices. For example, a baby's first step in one continent is captured and grandparents may see (and in some cases interact) and enjoy a full immersive experience with the child in another continent. In order to achieve such realism, models are becoming more sophisticated, and a significant amount of data is linked to the creation and consumption of those models. 3D meshes are widely used to represent such immersive contents.
Aspects of the disclosure include bitstreams, methods, and apparatuses for mesh processing. In some examples, an apparatus for mesh processing includes processing circuitry.
According to an aspect of the disclosure, a method of mesh decoding is provided. In the method, a bitstream of a mesh that includes a plurality of vertices is received. When the mesh is symmetric with respect to a symmetry plane, a first group of vertices of the mesh that is positioned at a first side of the symmetry plane is reconstructed. A second group of vertices of the mesh that is positioned at a second side of the symmetry plane is reconstructed by reflecting the reconstructed first group of vertices with respect to the symmetry plane.
According to another aspect of the disclosure, a method of mesh encoding is provided. In the method, whether a mesh is symmetric with respect to a symmetry plane is determined, where the mesh includes a plurality of vertices. When the mesh is symmetric with respect to the symmetry plane, the plurality of vertices is divided into a first group of vertices that is positioned at a first side of the symmetry plane, a second group of vertices that is positioned at a second side of the symmetry plane opposite to the first side, and a third group of vertices that is positioned on the symmetry plane. The second group of vertices is encoded by reflecting the first group of vertices with respect to the symmetry plane.
According to yet another aspect of the disclosure, a method of processing mesh data is provided. In the method, a bitstream of the mesh data is processed according to a format rule. The bitstream includes coded information of a mesh that includes a plurality of vertices. The format rule specifies that when the mesh is symmetric with respect to a symmetry plane, a first group of vertices of the mesh that is positioned at a first side of the symmetry plane is reconstructed. The format rule specifies that a second group of vertices of the mesh that is positioned at a second side of the symmetry plane is reconstructed by reflecting the reconstructed first group of vertices with respect to the symmetry plane.
Aspects of the disclosure also provide an apparatus for mesh encoding. The apparatus for mesh encoding including processing circuitry configured to implement any of the described methods for mesh encoding.
Aspects of the disclosure also provide an apparatus for mesh decoding. The apparatus for mesh decoding including processing circuitry configured to implement any of the described methods for mesh decoding.
Aspects of the disclosure also provide a non-transitory computer-readable medium storing instructions which, when executed by a computer, cause the computer to perform any of the described methods for mesh decoding, encoding, and mesh data processing.
Technical solutions of the disclosure include aspects to more efficiently compress polygon meshes with reflection symmetry. In an example, a bitstream of a mesh that includes a plurality of vertices is received. When the mesh is symmetric with respect to a symmetry plane, a first group of vertices of the mesh that is positioned at a first side of the symmetry plane is reconstructed. A second group of vertices of the mesh that is positioned at a second side of the symmetry plane is reconstructed by reflecting the reconstructed first group of vertices with respect to the symmetry plane. By reflecting the reconstructed first group of vertices with respect to the symmetry plane, coded information of the first group of vertices may be utilized to predict the second group of vertices. Accordingly, the amount of coded information required to code the second group of vertices may be reduced, and coding efficiency may be improved.
In a related example, all vertices in a mesh are mirrored when the mesh is symmetric with respect to a symmetry plane. In the current disclosure, vertices in the symmetry plane may not be mirrored.
Further features, the nature, and various advantages of the disclosed subject matter will be more apparent from the following detailed description and the accompanying drawings in which:
The video processing system (100) includes a capture subsystem (113), that can include a video source (101). The video source (101) may include one or more images captured by a camera and/or generated by a computer. For example, a digital camera, creating for example a stream of video pictures (102) that are uncompressed. In an example, the stream of video pictures (102) includes samples that are taken by the digital camera. The stream of video pictures (102), depicted as a bold line to emphasize a high data volume when compared to encoded video data (104) (or coded video bitstreams), can be processed by an electronic device (120) that includes a video encoder (103) coupled to the video source (101). The video encoder (103) can include hardware, software, or a combination thereof to enable or implement aspects of the disclosed subject matter as described in more detail below. The encoded video data (104) (or encoded video bitstream), depicted as a thin line to emphasize the lower data volume when compared to the stream of video pictures (102), can be stored on a streaming server (105) for future use. One or more streaming client subsystems, such as client subsystems (106) and (108) in FIG. I can access the streaming server (105) to retrieve copies (107) and (109) of the encoded video data (104). A client subsystem (106) can include a video decoder (110), for example, in an electronic device (130). The video decoder (110) decodes the incoming copy (107) of the encoded video data and creates an outgoing stream of video pictures (111) that can be rendered on a display (112) (e.g., display screen) or other rendering device (not depicted). In some streaming systems, the encoded video data (104), (107), and (109) (e.g., video bitstreams) can be encoded according to certain video coding/compression standards. Examples of those standards include ITU-T Recommendation H.265. In an example, a video coding standard under development is informally known as Versatile Video Coding (VVC). The disclosed subject matter may be used in the context of VVC.
It is noted that the electronic devices (120) and (130) can include other components (not shown). For example, the electronic device (120) can include a video decoder (not shown) and the electronic device (130) can include a video encoder (not shown) as well.
The receiver (231) may receive one or more coded video sequences, included in a bitstream for example, to be decoded by the video decoder (210). In an aspect, one coded video sequence is received at a time, where the decoding of each coded video sequence is independent from the decoding of other coded video sequences. The coded video sequence may be received from a channel (201), which may be a hardware/software link to a storage device which stores the encoded video data. The receiver (231) may receive the encoded video data with other data, for example, coded audio data and/or ancillary data streams, that may be forwarded to their respective using entities (not depicted). The receiver (231) may separate the coded video sequence from the other data. To combat network jitter, a buffer memory (215) may be coupled in between the receiver (231) and an entropy decoder/parser (220) (“parser (220)” henceforth). In certain applications, the buffer memory (215) is part of the video decoder (210). In others, it can be outside of the video decoder (210) (not depicted). In still others, there can be a buffer memory (not depicted) outside of the video decoder (210), for example to combat network jitter, and in addition another buffer memory (215) inside the video decoder (210), for example to handle playout timing. When the receiver (231) is receiving data from a store/forward device of sufficient bandwidth and controllability, or from an isosynchronous network, the buffer memory (215) may not be needed, or can be small. For use on best effort packet networks such as the Internet, the buffer memory (215) may be required, can be comparatively large and can be advantageously of adaptive size, and may at least partially be implemented in an operating system or similar elements (not depicted) outside of the video decoder (210).
The video decoder (210) may include the parser (220) to reconstruct symbols (221) from the coded video sequence. Categories of those symbols include information used to manage operation of the video decoder (210), and potentially information to control a rendering device such as a render device (212) (e.g., a display screen) that is not an integral part of the electronic device (230) but can be coupled to the electronic device (230), as shown in
The parser (220) may perform an entropy decoding/parsing operation on the video sequence received from the buffer memory (215), so as to create symbols (221).
Reconstruction of the symbols (221) can involve multiple different units depending on the type of the coded video picture or parts thereof (such as: inter and intra picture, inter and intra block), and other factors. Which units are involved, and how, can be controlled by subgroup control information parsed from the coded video sequence by the parser (220). The flow of such subgroup control information between the parser (220) and the multiple units below is not depicted for clarity.
Beyond the functional blocks already mentioned, the video decoder (210) can be conceptually subdivided into a number of functional units as described below. In a practical implementation operating under commercial constraints, many of these units interact closely with each other and can, at least partly, be integrated into each other. However, for the purpose of describing the disclosed subject matter, the conceptual subdivision into the functional units below is appropriate.
A first unit is the scaler/inverse transform unit (251). The scaler/inverse transform unit (251) receives a quantized transform coefficient as well as control information, including which transform to use, block size, quantization factor, quantization scaling matrices, etc. as symbol(s) (221) from the parser (220). The scaler/inverse transform unit (251) can output blocks comprising sample values that can be input into aggregator (255).
In some cases, the output samples of the scaler/inverse transform unit (251) can pertain to an intra coded block. The intra coded block is a block that is not using predictive information from previously reconstructed pictures, but can use predictive information from previously reconstructed parts of the current picture. Such predictive information can be provided by an intra picture prediction unit (252). In some cases, the intra picture prediction unit (252) generates a block of the same size and shape of the block under reconstruction, using surrounding already reconstructed information fetched from the current picture buffer (258). The current picture buffer (258) buffers, for example, partly reconstructed current picture and/or fully reconstructed current picture. The aggregator (255), in some cases, adds, on a per sample basis, the prediction information the intra prediction unit (252) has generated to the output sample information as provided by the scaler/inverse transform unit (251).
In other cases, the output samples of the scaler/inverse transform unit (251) can pertain to an inter coded, and potentially motion compensated, block. In such a case, a motion compensation prediction unit (253) can access reference picture memory (257) to fetch samples used for prediction. After motion compensating the fetched samples in accordance with the symbols (221) pertaining to the block, these samples can be added by the aggregator (255) to the output of the scaler/inverse transform unit (251) (in this case called the residual samples or residual signal) so as to generate output sample information. The addresses within the reference picture memory (257) from where the motion compensation prediction unit (253) fetches prediction samples can be controlled by motion vectors, available to the motion compensation prediction unit (253) in the form of symbols (221) that can have, for example X, Y, and reference picture components. Motion compensation also can include interpolation of sample values as fetched from the reference picture memory (257) when sub-sample exact motion vectors are in use, motion vector prediction mechanisms, and so forth.
The output samples of the aggregator (255) can be subject to various loop filtering techniques in the loop filter unit (256). Video compression technologies can include in-loop filter technologies that are controlled by parameters included in the coded video sequence (also referred to as coded video bitstream) and made available to the loop filter unit (256) as symbols (221) from the parser (220). Video compression can also be responsive to meta-information obtained during the decoding of previous (in decoding order) parts of the coded picture or coded video sequence, as well as responsive to previously reconstructed and loop-filtered sample values.
The output of the loop filter unit (256) can be a sample stream that can be output to the render device (212) as well as stored in the reference picture memory (257) for use in future inter-picture prediction.
Certain coded pictures, once fully reconstructed, can be used as reference pictures for future prediction. For example, once a coded picture corresponding to a current picture is fully reconstructed and the coded picture has been identified as a reference picture (by, for example, the parser (220)), the current picture buffer (258) can become a part of the reference picture memory (257), and a fresh current picture buffer can be reallocated before commencing the reconstruction of the following coded picture.
The video decoder (210) may perform decoding operations according to a predetermined video compression technology or a standard, such as ITU-T Rec. H.265. The coded video sequence may conform to a syntax specified by the video compression technology or standard being used, in the sense that the coded video sequence adheres to both the syntax of the video compression technology or standard and the profiles as documented in the video compression technology or standard. Specifically, a profile can select certain tools as the only tools available for use under that profile from all the tools available in the video compression technology or standard. Also necessary for compliance can be that the complexity of the coded video sequence is within bounds as defined by the level of the video compression technology or standard. In some cases, levels restrict the maximum picture size, maximum frame rate, maximum reconstruction sample rate (measured in, for example megasamples per second), maximum reference picture size, and so on. Limits set by levels can, in some cases, be further restricted through Hypothetical Reference Decoder (HRD) specifications and metadata for HRD buffer management signaled in the coded video sequence.
In an aspect, the receiver (231) may receive additional (redundant) data with the encoded video. The additional data may be included as part of the coded video sequence(s). The additional data may be used by the video decoder (210) to properly decode the data and/or to more accurately reconstruct the original video data. Additional data can be in the form of, for example, temporal, spatial, or signal noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, and so on.
The video encoder (303) may receive video samples from a video source (301) (that is not part of the electronic device (320) in the
The video source (301) may provide the source video sequence to be coded by the video encoder (303) in the form of a digital video sample stream that can be of any suitable bit depth (for example: 8 bit, 10 bit, 12 bit, . . . ), any colorspace (for example, BT.601 Y CrCB, RGB, . . . ), and any suitable sampling structure (for example Y CrCb 4:2:0, Y CrCb 4:4:4). In a media serving system, the video source (301) may be a storage device storing previously prepared video. In a videoconferencing system, the video source (301) may be a camera that captures local image information as a video sequence. Video data may be provided as a plurality of individual pictures that impart motion when viewed in sequence. The pictures themselves may be organized as a spatial array of pixels, wherein each pixel can comprise one or more samples depending on the sampling structure, color space, etc. in use. The description below focuses on samples.
According to an aspect, the video encoder (303) may code and compress the pictures of the source video sequence into a coded video sequence (343) in real time or under any other time constraints as required. Enforcing appropriate coding speed is one function of a controller (350). In some aspects, the controller (350) controls other functional units as described below and is functionally coupled to the other functional units. The coupling is not depicted for clarity. Parameters set by the controller (350) can include rate control related parameters (picture skip, quantizer, lambda value of rate-distortion optimization techniques, . . . ), picture size, group of pictures (GOP) layout, maximum motion vector search range, and so forth. The controller (350) can be configured to have other suitable functions that pertain to the video encoder (303) optimized for a certain system design.
In some aspects, the video encoder (303) is configured to operate in a coding loop. As an oversimplified description, in an example, the coding loop can include a source coder (330) (e.g., responsible for creating symbols, such as a symbol stream, based on an input picture to be coded, and a reference picture(s)), and a (local) decoder (333) embedded in the video encoder (303). The decoder (333) reconstructs the symbols to create the sample data in a similar manner as a (remote) decoder also would create. The reconstructed sample stream (sample data) is input to the reference picture memory (334). As the decoding of a symbol stream leads to bit-exact results independent of decoder location (local or remote), the content in the reference picture memory (334) is also bit exact between the local encoder and remote encoder. In other words, the prediction part of an encoder “sees” as reference picture samples exactly the same sample values as a decoder would “see” when using prediction during decoding. This fundamental principle of reference picture synchronicity (and resulting drift, if synchronicity cannot be maintained, for example because of channel errors) is used in some related arts as well.
The operation of the “local” decoder (333) can be the same as a “remote” decoder, such as the video decoder (210), which has already been described in detail above in conjunction with
In an aspect, a decoder technology except the parsing/entropy decoding that is present in a decoder is present, in an identical or a substantially identical functional form, in a corresponding encoder. Accordingly, the disclosed subject matter focuses on decoder operation. The description of encoder technologies can be abbreviated as they are the inverse of the comprehensively described decoder technologies. In certain areas a more detail description is provided below.
During operation, in some examples, the source coder (330) may perform motion compensated predictive coding, which codes an input picture predictively with reference to one or more previously coded picture from the video sequence that were designated as “reference pictures.” In this manner, the coding engine (332) codes differences between pixel blocks of an input picture and pixel blocks of reference picture(s) that may be selected as prediction reference(s) to the input picture.
The local video decoder (333) may decode coded video data of pictures that may be designated as reference pictures, based on symbols created by the source coder (330). Operations of the coding engine (332) may advantageously be lossy processes. When the coded video data may be decoded at a video decoder (not shown in
The predictor (335) may perform prediction searches for the coding engine (332). That is, for a new picture (or a mesh) to be coded, the predictor (335) may search the reference picture memory (334) for sample data (as candidate reference pixel blocks) or certain metadata such as reference picture motion vectors, block shapes, and so on, that may serve as an appropriate prediction reference for the new pictures. The predictor (335) may operate on a sample block-by-pixel block basis to find appropriate prediction references. In some cases, as determined by search results obtained by the predictor (335), an input picture may have prediction references drawn from multiple reference pictures stored in the reference picture memory (334).
The controller (350) may manage coding operations of the source coder (330), including, for example, setting of parameters and subgroup parameters used for encoding the video data.
Output of all aforementioned functional units may be subjected to entropy coding in the entropy coder (345). The entropy coder (345) translates the symbols as generated by the various functional units into a coded video sequence, by applying lossless compression to the symbols according to technologies such as Huffman coding, variable length coding, arithmetic coding, and so forth.
The transmitter (340) may buffer the coded video sequence(s) as created by the entropy coder (345) to prepare for transmission via a communication channel (360), which may be a hardware/software link to a storage device which would store the encoded video data. The transmitter (340) may merge coded video data from the video encoder (303) with other data to be transmitted, for example, coded audio data and/or ancillary data streams (sources not shown).
The controller (350) may manage operation of the video encoder (303). During coding, the controller (350) may assign to each coded picture a certain coded picture type, which may affect the coding techniques that may be applied to the respective picture. For example, pictures often may be assigned as one of the following picture types:
An Intra Picture (I picture) may be coded and decoded without using any other picture in the sequence as a source of prediction. Some video codecs allow for different types of intra pictures, including, for example Independent Decoder Refresh (“IDR”) Pictures.
A predictive picture (P picture) may be coded and decoded using intra prediction or inter prediction using a motion vector and reference index to predict the sample values of each block.
A bi-directionally predictive picture (B Picture) may be coded and decoded using intra prediction or inter prediction using two motion vectors and reference indices to predict the sample values of each block. Similarly, multiple-predictive pictures can use more than two reference pictures and associated metadata for the reconstruction of a single block.
Source pictures commonly may be subdivided spatially into a plurality of sample blocks (for example, blocks of 4×4, 8×8, 4×8, or 16×16 samples each) and coded on a block-by-block basis. Blocks may be coded predictively with reference to other (already coded) blocks as determined by the coding assignment applied to the blocks' respective pictures. For example, blocks of I pictures may be coded non-predictively or they may be coded predictively with reference to already coded blocks of the same picture (spatial prediction or intra prediction). Pixel blocks of P pictures may be coded predictively, via spatial prediction or via temporal prediction with reference to one previously coded reference picture. Blocks of B pictures may be coded predictively, via spatial prediction or via temporal prediction with reference to one or two previously coded reference pictures.
The video encoder (303) may perform coding operations according to a predetermined video coding technology or standard, such as ITU-T Rec. H.265. In its operation, the video encoder (303) may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancies in the input video sequence. The coded video data, therefore, may conform to a syntax specified by the video coding technology or standard being used.
In an aspect, the transmitter (340) may transmit additional data with the encoded video. The source coder (330) may include such data as part of the coded video sequence. Additional data may comprise temporal/spatial/SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, SEI messages, VUI parameter set fragments, and so on.
A video may be captured as a plurality of source pictures (video pictures) in a temporal sequence. Intra-picture prediction (often abbreviated to intra prediction) makes use of spatial correlation in a given picture, and inter-picture prediction makes uses of the (temporal or other) correlation between the pictures. In an example, a specific picture under encoding/decoding, which is referred to as a current picture, is partitioned into blocks. When a block in the current picture is similar to a reference block in a previously coded and still buffered reference picture in the video, the block in the current picture can be coded by a vector that is referred to as a motion vector. The motion vector points to the reference block in the reference picture, and can have a third dimension identifying the reference picture in case multiple reference pictures are in use.
In some aspects, a bi-prediction technique can be used in the inter-picture prediction. According to the bi-prediction technique, two reference pictures, such as a first reference picture and a second reference picture that are both prior in decoding order to the current picture in the video (but may be in the past and future, respectively, in display order) are used. A block in the current picture can be coded by a first motion vector that points to a first reference block in the first reference picture, and a second motion vector that points to a second reference block in the second reference picture. The block can be predicted by a combination of the first reference block and the second reference block.
Further, a merge mode technique can be used in the inter-picture prediction to improve coding efficiency.
According to some aspects of the disclosure, predictions, such as inter-picture predictions and intra-picture predictions, are performed in the unit of blocks, such as a polygon-shaped or triangular block. For example, according to the HEVC standard, a picture in a sequence of video pictures is partitioned into coding tree units (CTU) for compression, the CTUs in a picture have the same size, such as 64×64 pixels, 32×32 pixels, or 16×16 pixels. In general, a CTU includes three coding tree blocks (CTBs), which are one luma CTB and two chroma CTBs. Each CTU can be recursively quadtree split into one or multiple coding units (CUs). For example, a CTU of 64×64 pixels can be split into one CU of 64×64 pixels, or 4 CUs of 32×32 pixels, or 16 CUs of 16×16 pixels. In an example, each CU is analyzed to determine a prediction type for the CU, such as an inter prediction type or an intra prediction type. The CU is split into one or more prediction units (PUs) depending on the temporal and/or spatial predictability. Generally, each PU includes a luma prediction block (PB), and two chroma PBs. In an aspect, a prediction operation in coding (encoding/decoding) is performed in the unit of a prediction block. Using a luma prediction block as an example of a prediction block, the prediction block includes a matrix of values (e.g., luma values) for pixels, such as 8×8 pixels, 16×16 pixels, 8×16 pixels, 16×8 pixels, and the like.
It is noted that the video encoders (103) and (303), and the video decoders (110) and (210) can be implemented using any suitable technique. In an aspect, the video encoders (103) and (303) and the video decoders (110) and (210) can be implemented using one or more integrated circuits. In another aspect, the video encoders (103) and (303), and the video decoders (110) and (210) can be implemented using one or more processors that execute software instructions.
Aspects of the disclosure includes methods and systems directed to improvement of compression of polygon meshes that have a reflection symmetry.
A mesh may include several polygons that describe a surface of a volumetric object. Each polygon may be defined by vertices of the mesh in a 3D space and information of how the vertices are connected, referred to as connectivity information. In an aspect, vertex attributes, such as colors, normals, displacements, etc., may be associated with the mesh vertices. Attributes may also be associated with a surface of the mesh by exploiting mapping information that parameterizes the mesh with two-dimensional (2D) attribute maps. Such mapping may be described by a set of parametric coordinates, referred to as UV coordinates or texture coordinates, associated with the mesh vertices. 2D attribute maps may be used to store high resolution attribute information such as texture, normals, displacements, etc. Such information may be used for various purposes, such as texture mapping, shading and mesh reconstruction etc.
Meshes created from 3D scans or digital content creation tools may exhibit symmetries, which are properties of a geometry object when an operation maps the geometry object to itself. Types of symmetries may include a reflection, a translation, a rotation, and a combination of the reflection, the translation, and the rotation. Among the various symmetries, a reflection symmetry or a bilateral symmetry is a most common symmetry that exists in both a biological world and a non-biological world. For example, as shown in
A number of meshes have a reflection symmetry, and efficient methods are needed to compress those meshes with the reflection symmetry.
In the disclosure, methods are proposed to more efficiently compress polygon meshes with a reflection symmetry. The methods may be applied individually or by any form of combinations for mesh compression.
In an aspect, for an input mesh M whether the input mesh M has a reflection symmetry or not is evaluated. To measure whether the input mesh M has the reflection symmetry, the symmetry of the input mesh M may be evaluated by a similarity measure, which is a comparison between the input mesh M and a mirror of the input mesh M across a plane (or symmetry plane). If the symmetry of the input mesh M has been detected and the symmetry plane p: ax+by+cz=d has been determined, the input mesh M may be divided into two halves: a left mesh ML and a right mesh MR. For example, as shown in
Similarly, faces of the input mesh M may be categorized into left FL (a left set of faces), right FR (a right set of faces), and faces intersecting the plane FP. For intersecting faces (e.g., face (506) in
In an example, to determine whether a mesh is symmetric, a symmetry plane may be defined at first. For example, the symmetry plane is defined as ax+by+cz=d. Further, for each vertex (or point) in the mesh, a perpendicular distance from the vertex to the symmetry plane is calculated. The vertex is then reflected across the symmetry plane by moving the vertex with the perpendicular distance in an opposite direction along a normal to the symmetry plane. A reflected point (or vertex) is a symmetric counterpart of the vertex. For each reflected point (or vertex), a closest point (or vertex) is defined in the mesh. If a distance between the reflected point and the closest point corresponding to the reflected point is within a specified tolerance (e.g., a threshold value), the reflected point and the corresponding point are considered symmetric.
In an aspect, when an input mesh M is divided into a left mesh ML and a right mesh MR, the left mesh ML may be first encoded/decoded. In an encoder side, the left mesh ML is mirrored (or reflected) with respect to a symmetry plane p to generate a mirrored mesh. In a decoder side, a reconstructed (or decoded) left mesh is mirrored (or reflected) with respect to the symmetry plane p to generate a mirrored mesh. The right mesh ML is then predicted based on the reflected mesh. For example, in the encoder side, the mirrored mesh is then compared with the right mesh MR to generate displacements to fit (or predict) MR. The displacements may further be signaled to the decoder side. The decoder may reconstruct the right mesh MR based on the reflected mesh and the displacements. The fitted (or reconstructed) right mesh and the decoded left mesh may be glued (or combined) to form a watertight mesh. The watertight mesh may be defined as a reconstructed mesh of the input mesh M.
In an example, to mirror ML, each vertex v in VL is reflected with respect to the symmetry plan p to generate a reflected vertex v′ such that a vector from the vertex v to the reflected vertex v′ is perpendicular to the symmetry plan p.
In an aspect, for vertices VP in the symmetry plane p, each vertex in VP may be considered as a mirrored (reflected) vertex of the vertex itself. Thus, the vertices VP in the symmetry plane have no need to be glued (or combined) to form the watertight mesh. In an example, in an encoder side, each of the vertices VP is encoded by encoding an original value of the respective vertex. In a decoder side, each of the vertices VP is decoded (or reconstructed) based on the encoded value of the vertex that is received in a bitstream.
In an aspect, vertices in VP may be treated as vertices in one group of the mesh, such as VL. Thus, the vertices in VP may further be mirrored (or reflected) with respect to the symmetry plane p. Vertices on the symmetry plane p may be detected when the mirrored (reflected) vertices have same 3D coordinates as the original ones (e.g., the vertices in VP). The vertices in VP and the mirrored vertices in the symmetric place (or symmetry plane) may further be merged. In an aspect, in an encoder side, the vertices in VP may be encoded based on merged vertices. For example, the vertices in VP are encoded by encoding values of the merged vertices. In an aspect, in a decoder side, the vertices in VP may be reconstructed based on the merged vertices. For example, the vertices in VP are reconstructed (or decoded) based on the encoded values of the merged vertices that are received in a bitstream.
At (S610), a bitstream of a mesh that includes a plurality of vertices is received.
At (S620), when the mesh is symmetric with respect to a symmetry plane, a first group of vertices of the mesh that is positioned at a first side of the symmetry plane is reconstructed.
At (S630), a second group of vertices of the mesh that is positioned at a second side of the symmetry plane is reconstructed by reflecting the reconstructed first group of vertices with respect to the symmetry plane.
Then, the process proceeds to (S699) and terminates.
The process (600) can be suitably adapted. Step(s) in the process (600) can be modified and/or omitted. Additional step(s) can be added. Any suitable order of implementation can be used.
At (S710), whether a mesh is symmetric with respect to a symmetry plane is determined, where the mesh includes a plurality of vertices.
At (S720), when the mesh is symmetric with respect to the symmetry plane, the plurality of vertices is divided into a first group of vertices that is positioned at a first side of the symmetry plane, a second group of vertices that is positioned at a second side of the symmetry plane opposite to the first side, and a third group of vertices that is positioned on the symmetry plane.
At (S730), the second group of vertices is encoded by reflecting the first group of vertices with respect to the symmetry plane.
Then, the process proceeds to (S799) and terminates.
The process (700) can be suitably adapted. Step(s) in the process (700) can be modified and/or omitted. Additional step(s) can be added. Any suitable order of implementation can be used.
In an aspect, a method of processing mesh data includes processing a bitstream of the mesh data according to a format rule. For example, the bitstream may be a bitstream that is decoded/encoded in any of the decoding and/or encoding methods described herein. The format rule may specify one or more constraints of the bitstream and/or one or more processes to be performed by the decoder and/or encoder.
In an example, a bitstream of the mesh data is processed according to a format rule. The bitstream includes coded information of a mesh that includes a plurality of vertices. The format rule specifies that when the mesh is symmetric with respect to a symmetry plane, a first group of vertices of the mesh that is positioned at a first side of the symmetry plane is reconstructed. The format rule specifies that a second group of vertices of the mesh that is positioned at a second side of the symmetry plane is reconstructed by reflecting the reconstructed first group of vertices with respect to the symmetry plane.
The techniques described above, can be implemented as computer software using computer-readable instructions and physically stored in one or more computer-readable media. For example,
The computer software can be coded using any suitable machine code or computer language, that may be subject to assembly, compilation, linking, or like mechanisms to create code comprising instructions that can be executed directly, or through interpretation, micro-code execution, and the like, by one or more computer central processing units (CPUs), Graphics Processing Units (GPUs), and the like.
The instructions can be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, internet of things devices, and the like.
The components shown in
Computer system (800) may include certain human interface input devices. Such a human interface input device may be responsive to input by one or more human users through, for example, tactile input (such as: keystrokes, swipes, data glove movements), audio input (such as: voice, clapping), visual input (such as: gestures), olfactory input (not depicted). The human interface devices can also be used to capture certain media not necessarily directly related to conscious input by a human, such as audio (such as: speech, music, ambient sound), images (such as: scanned images, photographic images obtain from a still image camera), video (such as two-dimensional video, three-dimensional video including stereoscopic video).
Input human interface devices may include one or more of (only one of each depicted): keyboard (801), mouse (802), trackpad (803), touch screen (810), data-glove (not shown), joystick (805), microphone (806), scanner (807), camera (808).
Computer system (800) may also include certain human interface output devices. Such human interface output devices may be stimulating the senses of one or more human users through, for example, tactile output, sound, light, and smell/taste. Such human interface output devices may include tactile output devices (for example tactile feedback by the touch-screen (810), data-glove (not shown), or joystick (805), but there can also be tactile feedback devices that do not serve as input devices), audio output devices (such as: speakers (809), headphones (not depicted)), visual output devices (such as screens (810) to include CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch-screen input capability, each with or without tactile feedback capability—some of which may be capable to output two dimensional visual output or more than three dimensional output through means such as stereographic output; virtual-reality glasses (not depicted), holographic displays and smoke tanks (not depicted)), and printers (not depicted).
Computer system (800) can also include human accessible storage devices and their associated media such as optical media including CD/DVD ROM/RW (820) with CD/DVD or the like media (821), thumb-drive (822), removable hard drive or solid state drive (823), legacy magnetic media such as tape and floppy disc (not depicted), specialized ROM/ASIC/PLD based devices such as security dongles (not depicted), and the like.
Those skilled in the art should also understand that term “computer readable media” as used in connection with the presently disclosed subject matter does not encompass transmission media, carrier waves, or other transitory signals.
Computer system (800) can also include an interface (854) to one or more communication networks (855). Networks can for example be wireless, wireline, optical. Networks can further be local, wide-area, metropolitan, vehicular and industrial, real-time, delay-tolerant, and so on. Examples of networks include local area networks such as Ethernet, wireless LANs, cellular networks to include GSM, 3G, 4G, 5G, LTE and the like, TV wireline or wireless wide area digital networks to include cable TV, satellite TV, and terrestrial broadcast TV, vehicular and industrial to include CANBus, and so forth. Certain networks commonly require external network interface adapters that attached to certain general purpose data ports or peripheral buses (849) (such as, for example USB ports of the computer system (800)); others are commonly integrated into the core of the computer system (800) by attachment to a system bus as described below (for example Ethernet interface into a PC computer system or cellular network interface into a smartphone computer system). Using any of these networks, computer system (800) can communicate with other entities. Such communication can be uni-directional, receive only (for example, broadcast TV), uni-directional send-only (for example CANbus to certain CANbus devices), or bi-directional, for example to other computer systems using local or wide area digital networks. Certain protocols and protocol stacks can be used on each of those networks and network interfaces as described above.
Aforementioned human interface devices, human-accessible storage devices, and network interfaces can be attached to a core (840) of the computer system (800).
The core (840) can include one or more Central Processing Units (CPU) (841), Graphics Processing Units (GPU) (842), specialized programmable processing units in the form of Field Programmable Gate Areas (FPGA) (843), hardware accelerators for certain tasks (844), graphics adapters (850), and so forth. These devices, along with Read-only memory (ROM) (845), Random-access memory (846), internal mass storage such as internal non-user accessible hard drives, SSDs, and the like (847), may be connected through a system bus (848). In some computer systems, the system bus (848) can be accessible in the form of one or more physical plugs to enable extensions by additional CPUs, GPU, and the like. The peripheral devices can be attached either directly to the core's system bus (848), or through a peripheral bus (849). In an example, the screen (810) can be connected to the graphics adapter (850). Architectures for a peripheral bus include PCI, USB, and the like.
CPUs (841), GPUs (842), FPGAs (843), and accelerators (844) can execute certain instructions that, in combination, can make up the aforementioned computer code. That computer code can be stored in ROM (845) or RAM (846). Transitional data can also be stored in RAM (846), whereas permanent data can be stored for example, in the internal mass storage (847). Fast storage and retrieve to any of the memory devices can be enabled through the use of cache memory, that can be closely associated with one or more CPU (841), GPU (842), mass storage (847), ROM (845), RAM (846), and the like.
The computer readable media can have computer code thereon for performing various computer-implemented operations. The media and computer code can be those specially designed and constructed for the purposes of the present disclosure, or they can be of the kind well known and available to those having skill in the computer software arts.
As an example and not by way of limitation, the computer system having architecture (800), and specifically the core (840) can provide functionality as a result of processor(s) (including CPUs, GPUs, FPGA, accelerators, and the like) executing software embodied in one or more tangible, computer-readable media. Such computer-readable media can be media associated with user-accessible mass storage as introduced above, as well as certain storage of the core (840) that are of non-transitory nature, such as core-internal mass storage (847) or ROM (845). The software implementing various aspects of the present disclosure can be stored in such devices and executed by core (840). A computer-readable medium can include one or more memory devices or chips, according to particular needs. The software can cause the core (840) and specifically the processors therein (including CPU, GPU, FPGA, and the like) to execute particular processes or particular parts of particular processes described herein, including defining data structures stored in RAM (846) and modifying such data structures according to the processes defined by the software. In addition or as an alternative, the computer system can provide functionality as a result of logic hardwired or otherwise embodied in a circuit (for example: accelerator (844)), which can operate in place of or together with software to execute particular processes or particular parts of particular processes described herein. Reference to software can encompass logic, and vice versa, where appropriate. Reference to a computer-readable media can encompass a circuit (such as an integrated circuit (IC)) storing software for execution, a circuit embodying logic for execution, or both, where appropriate. The present disclosure encompasses any suitable combination of hardware and software.
The use of “at least one of” or “one of” in the disclosure is intended to include any one or a combination of the recited elements. For example, references to at least one of A, B, or C; at least one of A, B, and C; at least one of A, B, and/or C; and at least one of A to C are intended to include only A, only B, only C or any combination thereof. References to one of A or B and one of A and B are intended to include A or B or (A and B). The use of “one of” does not preclude any combination of the recited elements when applicable, such as when the elements are not mutually exclusive.
While this disclosure has described several examples of aspects, there are alterations, permutations, and various substitute equivalents, which fall within the scope of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise numerous systems and methods which, although not explicitly shown or described herein, embody the principles of the disclosure and are thus within the spirit and scope thereof.
The present application claims the benefit of priority to U.S. Provisional Application No. 63/603,002, “Improved Symmetric Coding for Polygon Mesh Compression” filed on Nov. 27, 2023, which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63603002 | Nov 2023 | US |
