Patent Application
20070288905
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
In some embodiments, the target hardware 104 comprises a megacell or a system-on-chip (SoC) which includes a control logic such as a processor 122 (e.g., digital signal processor (DSP)) and a storage 124 (e.g., random access memory (RAM)). The storage 124 stores one or more target applications 126 (e.g., embedded applications) which, when executed by the processor 122, perform any suitable function associated with the target hardware 104. As described further below, the host computer 102 is used to test and/or debug the one or more target applications 126. The remainder of this discussion assumes that a single target application 126 is being tested/debugged, although in some embodiments, multiple applications may be tested and debugged using the techniques described herein.
While the target application 126 is being debugged by the host computer 102, various information is transferred from the processor 122 to the host computer 102. Such information may include trace information. Trace information describes the various activities of the processor 122 as the processor 122 executes the target application 126. The trace information is provided so that a user of the host computer 102 can “step through” the software code of the target application 126 and determine how the processor 122 reacts to each line of code that is executed. Accordingly, the target hardware 104 also includes a trace acquisition module (TAM) 120. The TAM 120 collects trace information output by the processor 122, processes the trace information, and transfers the trace information to the host computer 102 via the cable 107. The host computer 102 is now described.
The host computer 102 comprises a processor 106 coupled to the I/O port 130. The processor 106 also couples to a storage medium 108, one or more output devices 114, one or more input devices 118, and a network port 116. The storage medium 108 may comprise volatile memory (e.g., RAM), non-volatile storage such as ROM, a hard disk, a CD-ROM, a flash drive, a floppy disk, a compact disc, and/or combinations thereof. The storage 108 stores a debugging application 112 and a decoder 110. The decoder 110 comprises a software decoder, although in some embodiments, a hardware decoder coupled to the processor 106 may be used instead. The input devices 118 may include any one or more of a keyboard, mouse, audio input device, touchpad, etc. The output devices 114 may include any one or more of a display, a printer, a storage device (e.g., a hard drive, flash drive), etc. The processor 106 may use the network port 116 to exchange information with another electronic device communicably coupled to the network port 116, such as another computer on an Internet or intranet network connection. For example, the network port 116 may be used to download the debugging application 112 onto the host computer 102.
The debugging application 112 is executed on the processor 106 and is used to test and/or debug the target application 126 on the target hardware 104. More specifically, when the processor 106 executes the debugging application 112, the processor 106 sends signals to and receives signals from the target hardware 104 via the cable 107 and the ports 130 and 128. Signals transferred from the host computer 102 to the target hardware 104 generally comprise test and debug signals, and signals transferred from the target hardware 104 to the computer 102 generally comprise response signals, including trace information. In this way, the target application 126 embedded on the target hardware 104 is tested and debugged using the application 112.
Trace information output by the processor 122 and/or TAM 120 of the target hardware 104 preferably is partitioned into three separate streams of information: a timing stream, a program counter (PC) stream and a data stream. The timing stream contains various timing information associated with the processor 122 as the processor 122 executes the target application 126, such as whether the processor 122 is active or stalled for each processor clock cycle, etc. The PC stream includes various program counter information associated with the processor 122 as the processor 122 executes the target application 126, such as how the program counter is affected by exceptions, branches, etc. The data stream includes various data information associated with the processor 122 as the processor 122 executes the target application 126, such as data values that are accessed by the processor 122, etc. In some embodiments, fewer or more information streams may be used.
Each information stream includes one or more markers called “synchronization points,” or “sync points.” In some embodiments, a sync point comprises a packet of information generated by the target hardware 104 and destined for the host computer 102. At least some sync points across the three streams may include a common identifier which is used to synchronize the streams. For example,
In the example provided in
Sync points are useful in various situations, one of which is when a software developer (i.e., user of the debugging application 112) desires to test and/or debug a specific portion of the target application 126. For example, if the developer desires to debug a specific portion of the target application 126, starting sync points (e.g., sync points 214, 224, 234) may be inserted such that the streams are synchronized before information associated with the specific portion of the application 126 appears in the streams. The starting sync points and ending sync points generally are used to indicate a starting point and an ending point of streams containing information that the user of the debugging application 112 desires to trace.
Various types of sync points are within the scope of disclosure. Starting sync points (e.g., PC sync point 224) may be used when a trace stream is being activated. An ending sync point (e.g., PC sync point 226) may be used when a trace stream is being deactivated. Sync points found between starting and ending sync points are periodic sync points that provide various additional trace information to the host computer 102. In accordance with embodiments of the invention, the sync points shown in
If an active PC stream is to switch to an inactive stream after the sync point 298 is issued, the PC bit preferably indicates an “inactive” status. Likewise, if an inactive PC stream is to switch to an active stream after the sync point 298 is issued, the PC bit preferably indicates an “active” status. A similar principle may apply to timing and data bits, which are described below.
Further, as shown in
When a sync point 298 is transferred to the host computer 102, the decoder 110 decodes the sync point 298 and determines the status of one or more of the bits 300, 302 and/or 304 to determine the current status of one or more of the trace streams. Because the sync point preferably does not contain information regarding previous statuses of any of the trace streams, information transfer between the target hardware 104 and the host computer 102, as well as the operation of the decoder 110, is made more efficient. The decoder 110 may additionally determine the status of the bit 306 to determine whether the sync point comprises a periodic sync point or a non-periodic sync point, thereby providing context information associated with the sync point. The techniques described herein also facilitate a simpler decoder design, since additional software code is not needed to process extraneous information in each sync point received.
The scope of disclosure is not limited to the views described above. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
