Synchronization detector of video signal processor and synchronization selector including the synchronization detector

Abstract

A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional video signal processor;

FIG. 2 illustrates a CVBS signal that is used as an input analog video signal of FIG. 1;

FIG. 3 is a block diagram of a synchronization detector of a video signal processor according to an embodiment of the present invention;

FIG. 4 is a diagram for explaining a line buffer of FIG. 3 according to an embodiment of the present invention;

FIGS. 5A and 5B are diagrams for explaining an operation of a parameter extraction unit of FIG. 3 to extract a horizontal synchronization parameter from a line buffer;

FIGS. 6A and 6B are diagrams for explaining an operation of the parameter extraction unit of FIG. 3 to extract a vertical synchronization parameter from a line buffer;

FIG. 7 is a block diagram of a synchronization detection unit of FIG. 3;

FIG. 8 is a block diagram of a horizontal synchronization detection unit of FIG. 7;

FIG. 9 is a block diagram of a vertical synchronization detection unit of FIG. 7;

FIGS. 10A and 10B are diagrams for explaining a field detecting operation of a field detector of FIG. 9; and

FIG. 11 is a block diagram of a synchronization selector of a video signal processor including the synchronization detector of FIG. 3 according to an embodiment of the present invention.

Claims

1. A synchronization detector of a video signal processor comprising: a line buffer that sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal;a parameter extraction unit that continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and that continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line; anda synchronization detection unit that generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

2. The synchronization detector of claim 1, wherein the input analog video signal comprises a CVBS signal, a separate video signal or a component signal.

3. The synchronization detector of claim 1, further comprising a video signal processing unit that converts the input analog video signal into a digital video signal to conform the input analog video signal to a standard level of a video signal processed in the video signal processor and that removes a color component from the digital video signal to output a filter output signal including a luminance signal and a synchronization signal, the filter output signal corresponding to the digital video signal.

4. The synchronization detector of claim 3, wherein the video signal processing unit comprises: an analog-to-digital converter that samples the input analog video signal and that converts the input analog video signal into the digital video signal to conform the input analog video signal to the standard level of the video signal; anda low pass filter that low-pass-filters the output signal of the analog-to-digital converter to remove a color burst signal and a chrominance signal and that generates the filter output signal.

5. The synchronization detector of claim 4, wherein the line buffer comprises: a bit value output unit that quantizes the filter output signal line by line and that outputs bits corresponding to the quantization values;an upper bit selection unit that selects upper bits from the bits and that outputs the upper bits; andline memories that sequentially stores the upper bits corresponding to data included in the lines, respectively.

6. The synchronization detector of claim 5, wherein the parameter extraction unit adds up the upper bits respectively stored in the line memories for continuous samples included in each line to obtain sum values corresponding to the number of the line memories, adds up the sum values to obtain the horizontal synchronization parameter at a predetermined time, and adds up the upper bits stored in a part of the line memories to obtain the vertical synchronization parameter at a predetermined time.

7. The synchronization detector of claim 6, wherein the synchronization detection unit comprises: a horizontal synchronization detection unit that generates the horizontal synchronization signal using time information related to the local minimum values of the horizontal synchronization parameters; anda vertical synchronization detection unit that generates the vertical synchronization signal using time information related to the local minimum values of the vertical synchronization parameters.

8. The synchronization detector of claim 7, wherein the horizontal synchronization detection unit comprises: a horizontal counter that outputs horizontal count values;a horizontal synchronization position output unit that outputs horizontal synchronization positions corresponding to time information related to the local minimum values of the horizontal synchronization parameters in response to the horizontal count values;a line length output unit that calculates a difference between the horizontal synchronization positions to generate the current line length detection value, that resets the horizontal counter whenever generating the current line length detection value, that adds the current line length detection value to a previous line length detection value to which a first horizontal coefficient has been multiplied, that divides the added value by a second horizontal coefficient, and that stores and outputs the resultant value as a final line length detection value; anda horizontal synchronization signal generator that generates the horizontal synchronization signal using a horizontal position count value that is one of the horizontal count values and corresponds to the horizontal synchronization positions and the final line length detection value,wherein the final line length detection value is used as a previous line length detection value when a subsequent final line length detection value is calculated.

9. The synchronization detector of claim 8, wherein the vertical synchronization detection unit comprises: a vertical counter that outputs vertical count values;a vertical synchronization position output unit that outputs vertical synchronization positions corresponding to time information related to the local minimum values of the vertical synchronization parameters in response to the vertical count values;a field length output unit that calculates a difference between the vertical synchronization positions to generate the current field length detection value, that resets the vertical counter whenever generating the current field length detection value, that adds the current field length detection value to a previous field length detection value to which a first vertical coefficient has been multiplied, that divides the added value by a second vertical coefficient, and that stores and outputs the resultant value as a final field length detection value; anda vertical synchronization signal generator that generates the vertical synchronization signal using a vertical position count value that is one of the vertical count values and corresponds to the vertical synchronization positions and the final field length detection value,wherein the final field length detection value is used as a previous field length detection value when a subsequent final field length detection value is calculated.

10. The synchronization detector of claim 9, wherein the vertical synchronization detection unit further comprises: a line system detector that detects a line system of the input analog video signal in response to the final field length detection unit; anda field detector that detects whether the field of the input analog video signal is an odd field or an even field using the phase relation of the horizontal synchronization signal and the vertical synchronization signal.

11. A synchronization selector of a video signal processor comprising: a first synchronization detector that detects a synchronization signal in a video signal processor receiving an input analog video signal including lines having a specific length;a second synchronization detector that detects a synchronization signal in a video signal processor receiving an input analog video signal including lines having different lengths;a multiplexer that selects one of the synchronization signals respectively output from the first and second synchronization detectors in response to a selection signal and that outputs the selected synchronization signal; anda controller that generates the selection signal in response to at least one of the input analog video signal, a field length of the input analog video signal and a length of a line included in the field of the input analog video signal, which are detected by the first and second synchronization detectors,wherein the first synchronization detector comprises:a line buffer that sequentially stores a digital video signal corresponding to the input analog video signal line by line of the input analog video signal;a parameter extraction unit that continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and that continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line; anda synchronization detection unit that outputs the field length and the line length using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

12. The synchronization selector of claim 11, wherein the output signal of the first synchronization detector is used for a TV system or an optical disk player and the output signal of the second synchronization detector is used for a VCR.

13. The synchronization selector of claim 11, wherein the controller calculates the absolute value of a difference between the line lengths of neighboring lines and generates the selection signal for selecting the output signal of the first synchronization detector when the absolute value is less than or equal to a predetermined reference value.

14. The synchronization selector of claim 11, wherein the controller calculates the absolute values of differences between the line lengths of neighboring lines and generates the selection signal for selecting the output signal of the first synchronization detector when the sum of the absolute values in the field length less than or equal to a predetermined reference value.

15. The synchronization selector of claim 11, wherein the controller calculates a value obtained by dividing the field length by ½ of the number of the lines of the input analog video signal and the absolute value of a value obtained by subtracting the line length from the divided field length and generates the selection signal for selecting the output signal of the first synchronization detector when the sum of the absolute values in the field length is less than or equal to a predetermined reference value.

16. The synchronization selector of claim 11, wherein the controller comprises a line counter that counts the lines of the input analog video signal and generates the selection signal for selecting the output signal of the first synchronization detector when the value counted by the line counter is continuous.