Patent Application
20120163523
None.
The present invention relates generally to synchronization methods for use in low frequency downhole communications, particularly, that are suitable for both uni-directional and half-duplex communications without feedback.
Typical petroleum drilling operations employ a number of techniques to gather information about the borehole and the formations through which it is drilled. Such techniques are commonly referred to in the art as measurement while drilling (MWD) and logging while drilling (LWD). As used in the art, there is not always a clear distinction between the terms LWD and MWD. Generally speaking MWD typically refers to measurements taken for the purpose of drilling the well (e.g., navigation and caliper) and often includes information about the size, shape, and direction of the borehole. LWD typically refers to measurements taken for the purpose of analysis of the formation and surrounding borehole conditions and often includes various formation properties, such as acoustic velocity, density, and resistivity. It will be understood that the present invention is relevant to both MWD and LWD operations. As such they will be referred to collectively herein as “MLWD.”
In many subterranean drilling operations, MLWD measurements are preferably made as close to the drill bit as possible, for example, within a few feet of the drill bit. These measurements are commonly transmitted from a near-bit sub to an upper portion of the bottom hole assembly (BHA) (i.e., above the drilling motor and/or steering tool) using an electromagnetic “short-hop” downhole communication channel. U.S. Pat. No. 5,160,925 to Dailey et al discloses one apparatus for making very low radio frequency (VLRF) electromagnetic communications in a borehole. Short-hop electromagnetic communications, such as those disclosed in the '925 patent, commonly utilized first and second, lower and upper transceivers deployed in corresponding lower and upper transceiver modules (referred to herein as LXM and UXM). Transmission from the LXM to the UXM is referred to herein as an uplink while transmission from the UXM to the LXM is referred to as a downlink.
Short hop electromagnetic communication data channels are known to be highly asymmetric. Such asymmetry is due at least in part to form factor constraints and severe channel noise at the LXM owing to its close proximity to the drill bit. This asymmetry commonly results in downlink communications being slower and less reliable than uplink communications. In certain high noise drilling environments, downlink communication can become very slow and intermittent or even virtually impossible. Prior art short hop communications techniques generally require bi-directional feedback between the LXM and the UXM. One significant drawback of this requirement is that the entire data channel (uplink and downlink) can be constrained by the aforementioned asymmetry (i.e., a slowdown or loss of downlink communications results in a corresponding slowdown or loss of uplink communications). This can be particularly problematic, for example, in geosteering and payzone steering operations in which near-bit MLWD measurements are utilized to make substantially real-time steering decisions while drilling.
There is a need in the art for a robust, multi-level synchronization scheme that enables downhole short hop electromagnetic communication without the need for any feedback between the LXM and UXM. Prior art synchronization methods are generally inadequate for downhole operations for a number of reasons. For example, these methods generally require a large number of symbols (a large data volume) for convergence and therefore have unacceptably high latency at the low frequencies used in a downhole VLRF channel. Moreover, these methods tend to be highly sensitive to noise, e.g., as is commonly encountered downhole, and are therefore prone to synchronization loss and error. There is a need in the downhole arts for synchronization methods that converge quickly and that can tolerate a highly noisy data channel without excessive loss of synchronization.
The present invention addresses the above-described need for improved synchronization methods for downhole communications. Aspects of this invention include methods for phase synchronization, symbol synchronization, and frame synchronization of a received waveform. The phase and symbol synchronization methods make use of distinct loop filters which process corresponding feedback signals so as to output phase clock and symbol clock adjustments. Frame synchronization methods accumulate a preamble correlation on a symbol stream having at least one repeating preamble. Embodiments of the invention may make use of any one or more (including all three) of the phase, symbol, and frame synchronization methods.
Exemplary embodiments of the present invention may advantageously provide several technical advantages. For example, exemplary phase, symbol, and frame synchronization methods according to this invention tend to provide both rapid and accurate convergence. These methods also tend to be insensitive to white noise.
Moreover, phase, symbol, and frame synchronization methods in accordance with the invention may therefore be advantageously utilized in either uni-directional (contiguous) communications or half-duplex communications without the need for feedback. The inventive methods may also be utilized in half-duplex communications that make use of time division on channel accesses. By eliminating the need for feedback, the inventive methods also enable a rapid resynchronization in the event of a synchronization loss (e.g., due to a burst of noise). Eliminating the need for feedback also tends to significantly increase the uplink communication speed (e.g., by an order of magnitude or more). These and other advantages are described in more detail below with respect to various embodiments of the invention.
In one aspect the present invention includes a method for synchronizing a received waveform with respect to a transmitted waveform. A waveform is received in a subterranean borehole and pre-processed to obtain in-phase and out-of-phase digitized waveforms. The in-phase and out-of-phase digitized waveforms are processed to obtain at least one phase adjustment and a symbol clock adjustment which are in turn further processed to obtain a decoded symbol sequence. The decoded symbol sequence is then processed to obtain a frame boundary.
In another aspect the present invention includes a method for synchronizing a received waveform with respect to a starting phase of a transmitted waveform. A waveform is received in a subterranean borehole and pre-processed to obtain in-phase and out-of-phase digitized waveforms. The in-phase and out-of-phase digitized waveforms are processed in combination with one another to obtain a feedback signal which is in turn further processed using a loop filter to obtain a phase adjustment.
In still another aspect, the present invention includes a method for synchronizing a received waveform with respect to a symbol transition in a transmitted waveform. A waveform is received in a subterranean borehole and pre-processed to obtain in-phase and out-of-phase digitized waveforms. At least one of the in-phase and out-of-phase digitized waveforms is processed to obtain a feedback signal which is in turn processed using a loop filter to obtain a symbol clock adjustment.
In yet another aspect, the present invention includes a method for synchronizing a received symbol sequence with respect to a frame boundary in a transmitted waveform. A decoded symbol sequence is received at a downhole processor. The symbol sequence includes a plurality of frames and at least one repeating preamble sequence, each of the frames including a preamble sequence and a corresponding payload. Each preamble sequence includes a plurality of decoded symbols. A correlation of each preamble sequence in the decoded symbol sequence is computed to obtain a frame boundary. The decoded symbol sequence and the frame boundary are then processed to decode the payload symbols.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
It will be understood by those of ordinary skill in the art that the deployment illustrated on
Referring now to
As described above in the Background Section, prior art short hop communications techniques generally require bi-directional feedback between the LXM and the UXM. One significant drawback of this requirement is that the entire data channel (both uplink and downlink) is constrained by any asymmetry in the communications channel. As a result of the asymmetry inherent in downhole short hop communication systems (particularly near bit systems), a slowdown or loss of communications in one direction (commonly the downlink) results in a corresponding slowdown or loss communications in the other direction. The present invention is intended to overcome this problem by providing rapid and robust synchronization methods that enable uni-directional communication (e.g., uplink only). Received data may be synchronized with a transmitted data signal at one or more levels including, for example, phase synchronization, symbol synchronization, and frame synchronization without the need for any feedback.
The received waveform is pre-processed at 90 prior to synchronization. The pre-processing commonly includes, for example, known filtering, amplification, analog to digital conversion, and quadrature downconversion steps. In the exemplary embodiment depicted the quadrature downconversion step (shown at 92 in
Preferred embodiments of the phase synchronization 100, symbol synchronization 200, and frame synchronization 300 steps are described in more detail below in PHASE SYNCHRONIZATION, SYMBOL SYNCHRONIZATION, and FRAME SYNCHRONIZATION.
x(t)=d1 sin Φ(t)+d2 cos Φ(t) Equation 1
where x(t) represents the digitized waveform, d1, d2 ∈ {1, −1} represent the input data bits, and Φ(t) represents the carrier phase in the general form ωt+θ, where ω represents the carrier frequency in radians per second and θ represents the initial phase at the transmitter.
The digitized waveform undergoes a quadrature downconversion at 92 to generate I and Q (in-phase and out-of-phase) digitized waveforms. Quadrature downconversion to zero frequency (i.e., DC) is preferred in that it significantly simplifies subsequent processing. Those of ordinary skill in the art will readily appreciate that the information encoded in x(t) is fully preserved in the DC components of the I and Q channels.
With continued reference to
When used with a QPSK modulation scheme, phase synchronization method 100 may be configured to converge to one out of four possible phase points in the range 0≦θ<2π. The four possible phase points θ1, θ2, θ3, and θ4 may be evenly spaced at intervals of π/2 radians such that the phase points may be related to one another mathematically, for example, as follows: θ4=θ3+π/2=θ2+π=θ1+3π/2. As described in more detail below, decoded symbols may be obtained for each of the four phase points. This apparent phase ambiguity is addressed below in the FRAME SYNCHRONIZATION section of this disclosure. While the exemplary method embodiments are described herein with respect to QPSK encoding, it will be understood that the invention is not so limited. Certain embodiments of the invention are suitable for other encoding schemes such as frequency shift keying (FSK) or quadrature amplitude modulation (QAM). It will also be understood that embodiments of the invention may be extended in a straightforward way for utilization with other N-phase shift keying modulation (e.g., N=8, 16, etc).
One exemplary embodiment of method 100 is now described in further detain with respect to
εI=({circumflex over (d)}1 sin Φ(t)+{circumflex over (d)}2 cos Φ(t))cos {circumflex over (Φ)}
εQ=−({circumflex over (d)}1 sin Φ(t)+{circumflex over (d)}2 cos Φ(t))sin {circumflex over (Φ)} Equation 2
where {circumflex over (d)}1 and {circumflex over (d)}2 represent the first and second input bits of the input symbol, Φ(t) is as defined above, and {circumflex over (Φ)} represents the estimated phase at the receiver where φ=Φ−{circumflex over (Φ)} represents the estimated phase error residual which forms the feedback signal in the loop filter.
In the exemplary embodiment depicted, εI and εQ may be numerically low-pass filtered at 112 and 122, for example, using a cut-off frequency of 2ω so as to remove harmonic oscillations of the carrier frequency (i.e., first order and higher). The filtered outputs may be represented mathematically, for example, as follows:
εI={circumflex over (d)}1 cos φ+{circumflex over (d)}2 sin φ
εQ={circumflex over (d)}1 sin φ−{circumflex over (d)}2 cos φ Equation 3
where εI, εQ, {circumflex over (d)}1, {circumflex over (d)}2, and φ are as defined above.
With continued reference to
Ψ(t)={circumflex over (d)}22 εI+{circumflex over (d)}12 εQ=2 sin φ Equation 4
where εI, εQ, {circumflex over (d)}1, {circumflex over (d)}2, and φ are as defined above and where {circumflex over (d)}22+{circumflex over (d)}12=2 after an appropriate normalization of Ψ(t) . Those of ordinary skill in the art will readily appreciate that a simple negative linear feedback system can be created using Ψ(t) since sin φ is essentially linearly related to φ when φ approaches zero (i e., since
It will be understood that the invention is not limited to embodiments utilizing the particular feedback signal described above with respect to Equation 4. In one alternative embodiment a difference of the sums computed in 114 and 124 yields a feedback signal having the following mathematical form:
Ψ(t)={circumflex over (d)}22 εQ−{circumflex over (d)}12 εI=2 cos φ Equation 5
It will be appreciated that a feedback signal of 2−Ψ(t)=2(1−cos φ) will tend to converge since
(i.e., when Ψ(t) approaches 1, φ2 approaches zero).
Those of ordinary skill in the art will appreciate that the feedback signal (e.g., as computed in Equation 4) may be filtered (e.g., using a finite impulse response or an infinite impulse response filter) prior to executing the loop filter at 140. The invention is not limited in these regards.
Phase loop filter 140 is configured for use with a waveform (e.g., a QPSK waveform) having a random sequence of symbols. In the exemplary embodiments depicted, the phase loop filter 140 is configured to iteratively adjust (update) the phase at some predetermined filter update interval. These phase adjustments (the outputs from the loop filter) may be input into the quadrature downconversion 92 as depicted on
In one preferred embodiment of the invention, a two-stage loop filter is utilized. In the first stage (referred to as the phase locking stage), a short update interval is utilized to promote a rapid convergence. The short update interval may be, for example, approximately equal to the number of digital samples in a single phase cycle (e.g., M=100 samples). In the second stage (referred to as the phase tracking stage), a longer update interval is utilized to promote accuracy. The longer update interval may be, for example, approximately equal to the number of digital samples in a symbol period (i.e. sM samples where s represents the number of phase cycles per symbol and M represents the number of digital samples per phase cycle, e.g., 2000 samples when s=20 and M=100). It will be understood that the invention is not limited to an update interval having any particular number of samples. Nor is the invention limited to an update interval having an integer multiple of the number of samples per phase cycle.
Since the digitized waveform commonly includes one or more symbol transitions, the loop filter is preferably not memoryless (i.e., prior values of the feedback signal are preferably incorporated into the computation of the phase adjustment). One exemplary zeroth order loop filter that incorporates prior values of the feedback signal may be represented mathematically, for example, as follows:
where NCO represents the numerically controlled oscillator (which is related to the phase adjustment), Ψ represents the feedback signal, δ represents the update interval, η represents the magnitude of the gain factor, and H represents the number of intervals in memory. As described in Equation 6, the phase adjustment is calculated based on an aggregate of a fixed number of prior feedbacks (intervals), with each adjustment being fixed to a desired level of granularity based on selected values of η and H. Those of skill in the signal processing arts will appreciate that the loop filter described by Equation 6 is a proportional controller when H equals 1 and a proportional integral controller having a simplified gain control when H is greater than 1.
One exemplary first order (linear) filter that incorporates prior values of the feedback signal may be represented mathematically, for example, as follows:
NCO=λ1ΓP+λ2ΛP Equation 7
where NCO again represents the numerically controlled oscillator (which is related to the phase adjustment), ΓP and ΛP represent the phase loop integral magnitude and proportional magnitude for the PI controller, and λ1 and λ2 represent gain factors for the phase loop integral and proportional controllers. In one exemplary embodiment, the phase loop integral magnitude ΓP may be determined via a summation operation while the phase loop proportional magnitude ΛP may be equal to the feedback signal at any particular time such that ΓP and ΛP may be expressed mathematically, for example, as follows:
where H0 represents the total number of phase loop-filter iterations since the start of the start of the phase synchronization process (e.g., since the initial start up or since the most recent loss of synchronization).
The loop filter models described above with respect to Equations 6 and 7 advantageously tend to be robust even when the loop filter update interval is changed (e.g., from a phase locking to a phase tracking stage) so long as the feedback signals {Ψ(t)|t=δ, 2δ, 3δ . . . } are properly normalized. It has been observed that the first order model generally converges faster than the zeroth-order model; however, the zeroth-order model tends to be simpler to adjust and is less computationally intensive (which can be advantageous in downhole operations).
The feedback signal Ψ(t) described above tends to be both robust and highly sensitive to phase errors. Therefore, phase synchronization methods in accordance with the present invention tend to advantageously converge quickly. The feedback signal also tends to be insensitive to white noise (those of ordinary skill in the art will readily appreciate that white noise sums to zero at 114 and 124). Being insensitive to white noise, the feedback signal also tends to be insensitive to interruption of the transmitted signal, e.g., during half duplex communications employing time division. Phase synchronization methods in accordance with the invention may therefore be advantageously utilized in either uni-directional (contiguous) communications or half-duplex communications that make use of time division. The invention is not limited in these regards.
Symbol synchronization methods in accordance with the present invention may be utilized in combination with or independent of the above described a phase synchronization methods. As a result, symbol synchronization may be performed essentially in parallel with phase synchronization (i.e., such that the phase and symbol synchronizations are initiated at substantially the same time).
Symbol synchronization method 200 is similar to phase synchronization method 100 in that it generates a feedback signal that is input into a loop filter (symbol loop filter 240). Each of the I and Q channels receives a continuous data stream from the quadrature downconversion at 92. A predetermined snapshot of data in each channel (e.g., a single symbol period including sM samples) may be processed at 210 and 220, for example, to determine I channel and Q channel symbol statistics (e.g., a sum or weighted average). These symbol statistics may be further processed at 230 to generate a feedback signal. The feed back signal is input into a loop filter (e.g., a proportional (P), proportional integral (PI), or proportional integral differential (PID) controller as described above with respect to
In a preferred embodiment in which the snapshot equals the symbol length (i.e., when there are sM samples in the snapshot), the following invariants hold: (i) at least one of LHI and THI does not include a symbol transition and (ii) at least one of LHQ and THQ does not include a symbol transition. Moreover, in the event of a type D symbol transition (a transition from one symbol to a different symbol), at least one of LHI, LHQ, THI, and THQ includes a phase transition representative of the symbol transition (which is representative of the starting point of the symbol).
With continued reference to
One aspect of the present invention is the realization that the demodulated sums computed in 214, 216, 224, and 226 are also indicative of the location of a symbol transition (a TD transition). In the absence of noise and phase error (e.g., due to incomplete phase synchronization), each phase cycle located before the transition sums to approximately 1 and each phase cycle located after the transition sums to approximately negative 1. For example a demodulated sum of approximately −4 is expected for an LHI including 10 phase cycles and having a symbol transition located between the third and fourth phase cycles (3−7=−4).
A suitable feedback signal may be obtained at 230 (
Those of ordinary skill in the art will appreciate that the presence of colored noise in the data channel and/or an incomplete phase synchronization can result in a feedback signal having a non-integer value. The symbol clock preferably adjusts the symbol starting point by an integer number of cycles and retains the remainder as a residual (e.g., in loop filter memory as described in more detail below) for use in future intervals.
Those of ordinary skill in the art will also appreciate that there are 12 possible types of TD transitions in QPSK processing (three types of transitions—I channel, Q channel, or I and Q channel at four distinct phase points). Provided that the symbol period is an integer multiple of phase cycles, the feedback signal described above advantageously provides a statistically identical signal for each of these possible transitions. This provides for robust symbol synchronization irrespective of the symbol transition. Convergence tends to be advantageously rapid and accurate.
While the preferred loop update interval (snapshot) is equal to the symbol length sM, it will be understood that the invention is not limited in this regard. Substantially any other loop update interval may be utilized with the understanding that (i) a lengthy update interval (e.g., greater than about 2 sM) tends to reduce convergence speed and (ii) a short interval (e.g., less than about sM/2) tends to unnecessarily increase variation in the feedback signal.
The computed feedback signal(s) are input into a symbol loop filter as depicted in
NSC=μ1ΓS+μ2ΛS Equation 9
where NSC represents the numerically derived symbol clock (which is related to the symbol clock adjustment), ΓS and ΛS represent the symbol loop integral magnitude and proportional magnitude for the PI controller, and μ1 and μ2 represent gain factors for the symbol loop integral and proportional controllers. In one exemplary embodiment, the symbol loop integral magnitude ΓS may be determined via a summation operation while the symbol loop proportional magnitude ΛS may be equal to the feedback signal at any particular time such that ΓS and ΛS may be expressed mathematically, for example, as follows:
where Ω(t) represents the symbol feedback signal (e.g., at intervals t=sM, 2 sM, 3 sM . . . ), and K0 represents the total number of symbol loop filter iterations since the start of the start of the symbol synchronization process (e.g., since the initial start up or since the most recent loss of synchronization).
In the exemplary embodiment described above, the feedback signal Ω(t) is derived from the leading half and trailing half of a single symbol period. It will be understood that the invention is not limited in this regard. The feedback signal may also be determined from the leading half of a first symbol period and the trailing half of a second symbol period. Moreover, in such embodiments, the first and second symbol periods need not even be consecutive.
The feedback signal Ω(t) described above tends to provide an accurate indication of the number of phase cycles by which the symbol clock is offset. Symbol synchronization methods in accordance with the present invention therefore tend to advantageously converge quickly. The feedback signal also tends to be insensitive to white noise (those of ordinary skill in the art will readily appreciate that white noise sums to zero when computing the demodulated leading half and trailing half sums). Being insensitive to white noise, the feedback signal also tends to be insensitive to interruption of the transmitted signal, e.g., during half duplex communications employing time division. Symbol synchronization methods in accordance with the invention may therefore be advantageously utilized in either uni-directional (contiguous) communications or half-duplex communications that make use of time division. The invention is not limited in these regards.
Frame synchronization methods in accordance with the present invention may be advantageously independent of the above described phase and symbol synchronization methods. When used in combination with phase synchronization method 100 described above with respect to
A preamble correlation may be computed at 310 on the received symbol sequence to obtain a frame boundary. As described in more detail below, the exemplary embodiment depicted includes a correlation step at 312 in which the received symbol sequence is checked for the occurrence of the preamble. The correlation obtained at 312 may then be accumulated at 314 at a predetermined frame spacing. The accumulated correlation may be searched at 316 for the highest value. A frame boundary (or starting point) may be set at 320 to the location of the highest value found in 316. Any phase ambiguity remaining from the phase correlation step 100 (
In a preferred embodiment of the invention a first-in first-out (FIFO) symbol buffer B1 is defined in 312. The buffer may include, for example, twice the number of symbols as a single frame (i.e., 2K symbols where K equals the number of symbols per frame). The buffer is initially set to zero. During the frame synchronization process the algorithm checks the latest κ symbols (where κ represents the number of symbols in the frame preamble) for each of the four possible preamble symbol combinations Θ1, Θ2, Θ3, and Θ4 corresponding to the four possible phase points θ1, θ2, θ3, and θ4 described above in PHASE SYNCHRONIZATION. The algorithm returns an index corresponding to the number of matched symbols for each of Θ1, Θ2, Θ3, and Θ4, wherein the index may equal, for example, 0, 1, 2, . . . , κ. The invention is not limited to any particular indexing scheme. In another embodiment, the index equals, for example, −2κ, −2κ+2, . . . , 2κ−2, 2κ. The returned indices are saved to the corresponding position in B1.
A second FIFO buffer B2 (e.g., of the same length as B1) is defined in 314 for accumulating indices stored in B1. Initially B2 is also cleared to zero. The correlated indices are accumulated (e.g., summed) at intervals equal to the frame length and stored to the corresponding position in B2. After at least a full frame of symbols has been correlated and accumulated at 312 and 314, buffer B2 is searched for the largest accumulated value at 316 as described above. The frame boundary may be set at the symbol location of the largest value in B2 at 320. The particular phase point θ1, θ2, θ3, or θ4 may be determined at 330 based upon which of the preambles, Θ1, Θ2, Θ3, or Θ4, returns the largest accumulated value at 316.
While the exemplary embodiment is described above with respect to the use of a single preamble (i.e., repeating the same preamble frame after frame), it will be understood that the invention is not limited in this regard. Alternating preambles may also be utilized (e.g., alternating first and second preambles). Such a process may require longer buffers as well as modified indices and counters. Notwithstanding, those of ordinary skill in the art will readily be able to extend the exemplary embodiments described above to embodiments that make use of more than one preamble.
Accumulation of the correlated preambles tends to amplify the presence of the frame boundary (since the correlation is summed). Frame synchronization methods in accordance with the present invention therefore tend to advantageously converge quickly. Frame synchronization method 300 also tends to be insensitive to an interruption of the transmitted signal in the payload portion of the frame, e.g., as may occur during half duplex communications employing time division. Symbol synchronization methods in accordance with the invention may therefore be advantageously utilized in either uni-directional (contiguous) communications or half-duplex communications that make use of time division. The invention is not limited in these regards.
Those of ordinary skill in the art will appreciate that the methods described above in accordance with the present invention are configured for digital implementation. These methods are well suited for downhole applications in that, as compared to analog methods, they tend to (i) reduce real-estate requirements on printed circuit boards, (ii) reduce power consumption, (iii) improve robustness and reliability due to the use of fewer circuit components.
It will be understood that the aspects and features of the present invention may be embodied as logic that may be processed by, for example, a computer, a microprocessor, hardware, firmware, programmable circuitry, or any other processing device well known in the art. Similarly the logic may be embodied on software suitable to be executed by a processor, as is also well known in the art. The invention is not limited in this regard. The software, firmware, and/or processing device may be included, for example, on a downhole assembly in the form of a circuit board, on board a sensor sub, or MWD/LWD sub. Alternatively the processing system may be at the surface and configured to process data sent to the surface by sensor sets via a telemetry or data link system also well known in the art. Electronic information such as logic, software, or measured or processed data may be stored in memory (volatile or non-volatile), or on conventional electronic data storage devices such as are well known in the art.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alternations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
