Patent Application
20070036255
The invention relates to the field of data processing and display. More particularly, the invention relates to the field of synchronizing processed data streams.
When data acquisition processors are used to generate data consumed by an administrative processor, the data sets coming from the data acquisition processors need to be time aligned, even though they are generated from separate processors, each having their own CPU clock. Without correction, the data sets would drift apart from each other, because the crystals used to generate the CPU clock for each processor are not exactly the same frequency.
Current solutions of compensating for this drift include dropping a sample from one of the data streams every so often. However, this type of approach results in large data discontinuities at the point of adjustment, and significant amounts of drift before it is applied. Complex, downstream adjustments to the data are also required.
In understanding the present invention, it will be beneficial to note that a PLL includes a voltage- or current-driving oscillator that is constantly adjusted to match in phase (and thus lock onto) the frequency of an input signal. In addition to stabilizing a particular communications channel (keeping it set to a particular frequency), a PLL can be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.
In one of the most common applications of PLLs 10, a modulo-n counter 30 is hooked between the VCO 25 output Fout 40 and the phase detector 15, thus generating a multiple of the input reference frequency fIN 35. This is an ideal method for generating clocking pulses at a multiple of the power-line frequency for integrating A/D converters (dual-slope, charge-balancing), in order to have infinite rejection of interference at the power-line frequency and its harmonics. It also provides the basic technique of frequency synthesizers.
This invention makes use of the design principles behind PLLs 10, which is considered prior art. However, PLL 10 principles and techniques are applied in a novel way.
The present invention is a system and method of synchronizing data streams from data acquisition processors. The system and method utilizes a common signal to data acquisition processors to trigger a measuring of the data sampling signal. These measurements are averaged and compared to an expected phase, whereby either of the data acquisition processor's data delivery rate are adjusted if the compound shows a difference greater than a maximum drift rate.
The present invention includes a method of synchronizing a set of data streams, which comprises routing a common signal to a first data acquisition processor and a second data acquisition processor, wherein the common signal triggers the first and second data acquisition processors to take a plurality of phase measurements of a sampling signal, averaging the plurality of phase measurements, comparing the averaged phase measurements of each of the first and second data acquisition processors to an expected phase, and adjusting a digital control signal of either one of the first and second data acquisition processors when the difference between the average phase measurement of either data acquisition processor and the expected phase exceeds a maximum drift rate, wherein the common signal is generated by an administrative processor.
The present invention includes a system for synchronizing a set of data streams, which comprises a first data acquisition processor and a second data acquisition processor, the first and second data acquisition processors configured to receive a common signal, and an administrative processor configured to receive a data signal from each of the data acquisition processors and to generate the common signal, wherein the first and second data acquisition processors take a plurality of phase measurements of a sampling signal and average the phase measurements when the common signal is received, and further wherein the first and second data acquisition processors compare the average phase measurements to an expected phase, such that a digital control signal of either one of the first and second data acquisition processors is adjusted when the difference between the average phase measurements and the expected phase exceeds a maximum drift rate.
The present invention includes a method of synchronizing a set of data streams, which comprises generating a common signal with an administrative processor, routing the common signal to a first data acquisition processor and a second data acquisition processor, wherein the common signal triggers the first and second data acquisition processors to take a plurality of phase measurements of a sampling signal, averaging the plurality of phase measurements, comparing the averaged phase measurements of each of the first and second data acquisition processors to an expected phase, and adjusting a digital control signal of either one of the first and second data acquisition processors when the difference between the average phase measurement of either data acquisition processor and the expected phase exceeds a maximum drift rate.
As shown in
171 The data delivery rate of each data acquisition processor 120, 135 is a function of the rate at which it samples data. For each data acquisition processor 120, 135, this sample rate is performed using on-chip timers, set to sample the data at a predefined period. Specifically, the timers will repeatedly count from 0 to a predefined value, with a new sample collected at each timer restart. Synchronization will be implemented by adjusting this mechanism directly, either by moving the timer count ahead or behind, depending on the direction of the synchronization required. The effect is that the sampling is adjusted in phase, and aligned with that of the common signal. This will occur each time phase misalignment between the data acquisition processors 120, 135 sampling timers and the common signal exceeds the adjustment threshold.
181 An additional component of this invention is enhanced noise-immunity. Under normal circumstances, the common signal 180 provided to each data acquisition processor 120, 135 will be uncorrupted. However, synchronization will still occur under noisy conditions, and with the resulting, associated corrupted common signal 180 arriving at the processors. This is done by monitoring for, and rejecting, “outlier” samples that occur under these conditions, and that exceed the known range of valid readings. Rejected samples will be replaced with the last valid sample, for designated duration of continuously occurring noise and corrupted signal.
In the medical field, this invention will result in more accurate data presentation to medical personnel, with a likely associated increase in customer satisfaction, and enhanced marketing appeal. The most common method of synchronizing data streams from multiple processors is for them to use a shared CPU clock. However, the present invention was designed in a system that would not easily allow for this type of approach, primarily as a result of a requirement that the data acquisition processors 120, 135 systems be electrically isolated from each other. In this environment, it is easier to deliver the lower frequency common signal 180 of this invention, and use it to adjust the phase of the sampling on the data acquisition processors 120, 135, resulting in a more robust solution and reduced technical risk. Furthermore, this phase compensation is performed on each data acquisition processor 120, 135 separately, resulting in the data streams 175 from both being synchronized to the common signal 180, and to each other. Without such a common signal, data delivered 175 from the data acquisition processors 120, 135 would drift apart, making diagnosis derived from comparison of the associated data sets difficult and inaccurate. Other cruder methods of compensating for this drift are possible, like dropping a sample from the data streams every so often. But these types of approaches result in large data discontinuities at the point of adjustment, and significant amounts of drift before it is applied. Complex, downstream adjustments to the data are also required, whereas the present invention performs the compensation at the optimal, earliest stage of its collection. A novel approach to noise immunity is provided by this invention as well, by allowing synchronization of the data acquisition processors 120, 135 in the presence of noise. It will overcome reasonable and expected levels of noise corruption, by rejecting and compensating for “outlying” samples of the common signal, and without negative effect on the overall synchronization.
201 Referring now to
The synchronizing method 300 of the present invention is further depicted in
The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention.
