Video display apparatus, such as television and monitor equipment, includes complex video processing circuitry and software to process the video component of a video signal. This processing generally imposes delays in the transmission of the video component that are substantially longer than any delays imposed on the audio component of the video signal and can adversely affect the synchronism between the audio and video presented to the viewer.
When the audio and video components both pass through a common apparatus, it is possible to maintain synchronism by adding a compensating transmission delay to the audio component. However, in cases where both of these components do not pass through a common apparatus, such compensation is not easily achieved. For example, if a DVD player is the source of the video signal, the video and audio components might pass through different audio and video equipments, where the manufacturer of the audio equipment does not know the duration of the processing delay in the video component.
In accordance with the invention, compensation for loss of synchronization between video and audio, because of a video signal processing delay, is achieved by transmitting a video test signal representing a test image to be presented by a display device. The video test signal is subjected to the processing delay, before the test image is presented. A light detector receives light from the test image and produces a received test signal representative of the test image. A delay of the audio to compensate for the video processing delay is effected by means of a controller. The controller determines the delay needed by correlating the received test signal with the transmitted test signal.
The video system of
The video source VS includes a video generator 12, e.g. an MPEG decoder, for supplying a video signal having a video component, provided at an output 12v, and an audio component, provided at an output 12a. These components may be provided in the form of either digital or analog signals, as is well known in the art.
The video component provided at output 12v is transmitted over a line 11 to the display device VID, where a video processing delay occurs before the image represented by the video component is displayed to the viewer. This delay typically includes a number of smaller cumulative delays including, for example, processing for noise reduction, complex (e.g., three-dimensional) scaling, application of natural-motion algorithms, and varies with the type of display device (e.g., Plasma, LCD, DMD, CRT). The duration of the delay in the display device may be unknown to the manufacturer of the video source VS, particularly if these equipments are from different manufacturers.
The audio component provided at output 12a of the video generator 12 is transmitted through an audio delay device 18 having a controllable variable delay, and then over a line 13 to the audio device AUD.
The video source VS further includes a controller 14 (e.g., a micro-controller), a light detector 16, and a test signal generator (which is advantageously incorporated in the video generator 12) for collectively determining the duration of the delay imposed on the video component. The controller 14 is coupled to the video generator 12, via a line 15, for receiving a test signal produced by the test signal generator.
When activated, the test signal generator simultaneously transmits a video test signal over the lines 11 and 15 to the display device VID and to the controller 14, respectively. If the video source includes an MPEG decoder, it can be set to produce video test signals representing one or more desired test patterns for display by the display device. In an exemplary embodiment, the test generator produces a video test signal representing a sequence of alternating darker and lighter images, such as solid black and white screens, to be produced by the display device.
The light detector 16 is located to receive the ambient room light including light from the test pattern produced by the display device VID. The light detector converts the received light to a detection signal, which is influenced by light from the displayed test pattern. Specifically, the detection signal includes a test signal component (the “received test signal”) representing the test pattern and transmits it via a line 17 to the controller 14.
The controller 14 operates to determine the delay that must be provided by the audio delay device 18 to place the audio from the speaker system in synchronism with the image displayed by the device VID. In order to do this, controller 14 measures the delay between the transmission of the video test signal and the reception of the test signal, representing the test pattern produced by the display device VID. The controller then transmits a delay signal representing the measured delay over a line 19 to audio delay device 18, which effects a corresponding delay of the audio signal transmitted to the audio device AUD. Note that the audio delay device 18 need not be a separate apparatus. For example, if the video generator 12 incorporates an MPEG decoder, the desired delay can be effected by, for example, manipulating timestamps in the MPEG program stream.
Referring to
The photo-diode P is disposed where it will sense the ambient light in the area where the display device VID is operative. Conveniently it will be incorporated in a housing of the video source VS or other component containing the light detector, but it may also be remotely located. The current passing through the photodiode varies as a function of the incident light. The first amplifier circuit primarily functions to convert the photodiode current to an amplified voltage representative of the incident light intensity. The second amplifier circuit functions as both a comparator and an integrator. It cooperates with the first amplifier circuit to keep the first amplifier in its linear operating range. An inexpensive low-conversion speed A/D converter may be utilized because both resolution and conversion speed may be low. The A/D converter in this exemplary light detector operates at a conversion clock rate of 1 kHz.
Although this invention has been described with reference to particular embodiments, it will be appreciated that many variations will be resorted to without departing from the spirit and scope of this invention as set forth in the appended claims. The specification and drawings are accordingly to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.
In interpreting the appended claims, it should be understood that:
a) the word “comprising” does not exclude the presence of other elements or acts than those listed in a given claim;
b) the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements;
c) any reference signs in the claims do not limit their scope;
d) several “means” may be represented by the same item or hardware or software implemented structure or function;
e) any of the disclosed elements may be comprised of hardware portions (e.g., including discrete and integrated electronic circuitry), software portions (e.g., computer programming), and any combination thereof;
f) hardware portions may be comprised of one or both of analog and digital portions;
g) any of the disclosed devices or portions thereof may be combined together or separated into further portions unless specifically stated otherwise; and
h) no specific sequence of acts is intended to be required unless specifically indicated.
Number | Date | Country | |
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60636366 | Dec 2004 | US |