Patent Application
20190131866
The present description relates generally to integrated circuits, and more particularly, to synchronizing hiccup over-current protection of multiphase switching converters.
More and more high current loads are emerging in the industrial applications such as automotive and telecom applications. In this regard, multi-phase switching power converters are gaining popularity in providing the high current for these applications. In the multiphase approach, the focus of the design can be directed to optimization of a single phase design, including the power stage and control and/or protection scheme. Each phase can run stand alone, or can he paralleled as a high current converter.
One example is a power module, in which the converter unit has been optimized and modularized, such that the end user can benefit from the modularity and easily scale the power supply in a short time with the fully verified building blocks. This reduces the time-to-market. Another benefit of a multiphase configuration is redundancy. For example, in case a phase of a multiphase converter fails, the next phase can seamlessly take over without interrupting the output.
When the output of a power converter is loaded beyond its preset current limit, a controller should take action to protect the load. One robust solution is hiccup mode protection. After the controller detects an overcurrent condition, it immediately clamps the current sharing signal and limits its output current. If the overcurrent fault exists for longer than a predetermined time, the converter turns off for a preset long period of time and retry to start-up after the time period expires. In the high current applications, the hiccup protection strategy is preferable since it can minimize the heat dissipation at the load. It is challenging, however, to adopt the hiccup mode protection for multiphase converters. Unless their power stages and control loops are perfectly identical, different phases of a multiphase converter may detect the overcurrent condition at different level, and at different times. This can cause disorder of hiccup times sequencing. It might also cause the converter latch-up in a wrong state.
In a current-mode controlled dual phase high-voltage boost converter for automotive application, for example, the current-mode controlled dual phase converter shares a threshold current (ITH) signal between phases. When the overcurrent occurs, once the shared current command ITH is clamped by one controller with slightly lower threshold, the other one will not detect the overcurrent event and keep running at full power. Some converters add a dedicated communication bus to perform the detection, however, the additional bus not only requires extra cost and complication, but can also lower the overall reliability of the converters.
In one or more aspects, a multiphase switching converter includes a first switching converter circuit including a power stage coupled to a DC voltage supply and a controller. The controller includes an over-current (OC) circuit that can detect an OC event and, upon detecting the OC event, set a command signal to a preset low value and provide a first hiccup signal. A synchronization circuit can generate a second hiccup signal based on the command signal of the OC circuit satisfying a first reference threshold value, and a sampled portion of an output voltage of the power stage satisfying a second reference threshold value. A hiccup timer can be triggered by one of the first hiccup signal or the second hiccup signal to start a hiccup pulse in response to being triggered.
In one or more embodiments, a method for synchronizing hiccup over-current protection in a multiphase switching converter includes detecting, by an over-current circuit, an over-current event. The method further includes, in response to detecting the over-current event, setting, by the over-current circuit, a command signal to a preset low value and providing a first signal. A second signal is generated, by a synch circuit, in response to command signal being lower than a first reference threshold value and a sampled portion of a regulated output voltage of the multiphase switching converter is less than a second reference threshold value. A hiccup mechanism can be triggered based on one of the first signal or the second signal. The over -current circuit and the synch circuit are modules of a control circuit included in each switching converter of the multiphase switching converter.
In yet one or more other embodiments, a converter system with synchronized hiccup overcurrent protection includes two or more switching converter to operate using multiphase sequential switching pulses. Each of the two or more switching converter modules includes a power stage coupled to a DC voltage source and a control circuit, and the control circuit includes an over-current circuit and a synch circuit. Each over-current circuit of the switching converter modules can detect an over-current event and, upon detecting the over-current event, can set a command signal to a preset low value and to provide a first signal, Each respective synch circuit of the switching converter modules includes a hiccup timer and can generate a second signal in response to the command signal being lower than a first reference threshold value and the regulated output voltage being less than a second reference threshold value. The hiccup timer can be started by one of the first signal or the second signal.
Certain features of the subject technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the subject technology are set forth in the following figures.
In one or more aspects of the subject technology, methods and configurations are described for synchronizing hiccup over-current protection of multiphase switching converters. The subject technology provides a robust hiccup protection scheme, regardless of the current sharing performance, the matching of overcurrent limit between controllers, phase number and controller number, closed loop control bandwidth and the load condition. Once one of the switching converter circuits or modules (also referred to as “phases”) detects an overcurrent event, all phases are turned off simultaneously and the load is cooled down until a preset timer expires, The power dissipation during this period is approximately zero. After the hiccup timer expires, all the phases restart together. The disclosed scheme provides a multi-controller to multi-controller duplex communication, without adding a dedicated communication bus. As no dedicated communication bus is used, the cost is reduced and the implementation is simplified. The subject technology can be implemented in a variety of architectures of multiphase converters such as current-mode, voltage mode, and masterless and master-slave architectures, as described in more detail herein.
The synchronized two-phase switching converter 100A of
The control circuits 120-1 and 120-2 can trigger a hiccup mechanism as discussed below and are substantially similar in structure and functionality. In other words, the control circuits 120-1 and 120-2 have similar modules with similar functionalities. For brevity, only the control circuit 120-1 is described herein. The control circuit 120-1 includes a number of modules including a comparator 122, an error amplifier 124, an over current (OC) circuit 126, and a synchronization (synch) circuit 125. The error amplifier 124 can be a transconductance amplifier and compares a feedback (FB) voltage, sampled from the regulated output voltage Vout at a voltage divider formed of resistors R1 and R2, with a reference voltage (REF1) and generates an output current that is proportional to the deviation of the sampled voltage from the reference voltage. The OC circuit 126 is an OC protection circuit that can detect an overcurrent and upon detection of the overcurrent, can generate an OC signal, which as described below, is a first hiccup trigger signal and can trigger the hiccup mechanism if the overcurrent event continued for a preset length of time. The output current of the OC circuit 126 is a threshold current signal (ITH) that is used as a current command signal and is shared between the control circuits 120-1 and 120-2 at a node 121 that is coupled via a compensation circuit 140 (e.g., an RC circuit) to the ground potential. The OC circuit 126 can, at the same time, limit a maximum threshold current signal ITH to restrict this current to a preset OC value and prevent the load from being damaged.
The comparator 122 compares a current sensing signal (VCS) with the shared current signal ITH to generate a duty cycle pulse (d) and provides the duty cycle signal to the power stage 110-1. The duty cycle pulse (d) can control a duty cycle of the power stage 110. The current sensing signal from the power stage 110-1 reflects the instantaneous waveform or the average value of an inductor current, an active switch current or a free-wheeling switch current of the power stage 110-1. The power stage 110-1 may include a modulator (e.g., a constant -frequency or variable frequency modulator) that can modulate the duty cycle pulse. The duty cycle pulse (d) can control a duty cycle of the power stage 110-1.
The synch circuit 125 of the subject disclosure can also be used to trigger the hiccup mechanism. The synch circuit 125 includes a first comparator 132, a second comparator 134, a logic AND gate 136, and a hiccup timer 138. The first comparator 132 compares the shared current signal ITH with a minimum value (e.g., ITH_MIN), and the second comparator 134 compares the FB voltage with the reference voltage REF2 (e.g., FB_MIN). The results of the comparisons by the first and second comparators 132 and 134 are fed to the AND gate 136, which generates a second hiccup trigger signal. Based on operational principles of the first and second comparators 132 and 134 and the AND gate 136, it is understood that the second hiccup trigger signal is generated (e.g., asserted) when the shared current signal ITH is smaller than a minimum value (ITH_MIN) and the FB voltage is lower than a reference voltage (REF2, e.g., FB_MIN), The first trigger signal (e.g., the OC signal) and the second trigger signal (e.g., the output signal from the AND gate 136) are sent to a logic OR gate 128.
The output of the logic OR gate 128 is logic high when at least one of the first or the second trigger signal are asserted. The logic high output of the logic OR gate 128 can close a switch 130 that pulls down the shared current signal to a low value (e.g., less than ITH_MIN) and at the same time start the hiccup timer 138. Pulling down the shared current signal ITH to the low value can cause the other controller circuit (120-2) to also start its hiccup timer regardless of detecting overcurrent or not. This may be referred to as a communication between phases without having a dedicated communication bus. The hiccup timer 138 includes a first current source 133 and a second current source 135. The first current source 133 is connected to a supply voltage and provides a charging current for the capacitor C1. The second current source 135 is connected to a ground potential and provides a constant discharge current for the capacitor C1, when the hiccup timer 138 is enabled. The discharge time of the capacitor C1 is a preset time that is based on a capacitance value of the capacitor C1 and a current value of the second current source, and determines the hiccup duration, discussed with respect to the overcurrent and hiccup pulses below,
The timing diagram 100B of
The timing diagram 100C of
The controller circuits of the subject technology (e.g. 120-1 and 120-2) allow multiple phases (e.g., 2 or more) of a multiple phase converter to be synchronized such that if the overcurrent was not detected by one or more phases, the phase that has first detected the overcurrent can pull down the shared threshold current ITH so that all phases start their respective hiccup timers.
The process 200 begins at an operation block 202, where the synchronized multiphase switching converter (e.g., 100A of
Either one of the two conditions checked in the control operation blocks 204 and 206 can trigger the hiccup protection mechanism. One condition is the output current Iout is higher than the maximum allowed current value Imax checked by the control operation block 204. The other condition is that output voltage is lower than the regulation voltage and in the meantime the power command signal is at the preset low level, as checked by the control operation block 206, When the output voltage is not lower than the regulation voltage or the power command signal is not at the preset low level, the control is passed to the operation block 212, where normal operation of the circuit is continued.
When either condition triggers the hiccup mode, the controller, at an operation block 208 takes the following actions simultaneously 1) initiate the off period timer, 2) turns off the power stage and 3) forces a power command signal below a preset low level (e.g., using switch 130 of
The described arrangement controlled by the process 200 is a robust hiccup protection scheme that is independent of the current sharing performance, the matching of overcurrent limit between controllers, the phase number and controller number, the closed loop control bandwidth and the load condition. Once one of the phases detects an overcurrent event, all the phases are turned off simultaneously and the load is cooled down until the preset timer expires. The power dissipation during this period is approximately zero. After the hiccup timer expires, all the phases restart together. The subject scheme, as described above, provides a multi-controller to multi-controller duplex communication, without adding a dedicated bus, which reduces the cost and simplifies the implementation. The proposed concept is applicable in a number of architectures of a multiphase converter, as described with respect to the embodiments of
As described above, the controller 320-1 allows the multiple phases of the multiphase switching converter 300 to be synchronized. For example, the ITH signal path has a limiter (e.g., 126 of
The feedback signal (FB) sampled (via a voltage divider formed by resistors R1 and R2) from the output voltage Vo is connected to inverting input of the transconductance amplifiers (gm) (e.g., 524-1) of all the controllers. The outputs of the transconductance amplifiers COMP, from which the pulse-width modulation (PWM) duty ratio command signal is derived, are tied together. The COMP signal is compared with the modulation ramp at the PWM comparator 522 to generate the duty cycle pulse (d). The duty cycle pulse (d) can control a duty cycle of the power stage 110-1 of
For current balancing purposes, the current sensing signal Vcs from every power stage (P.S.) is connected to the current sharing bus via a or-ing diode 523. The Vsh will be automatically equal to the lowest or highest Vcs in all phases of the multiphase switching converter 500. In some other implementations, Vsh can he automatically equal to the average value of Vcs of all the phases. The current sharing loop of each phase compares its own Vcs with Vsh using the subtractor 526, and incrementally adjusts the actual COMP signal applied to the PWM comparator 522, in order to make the current of the first phase phase match with the lowest or highest current among all the phases.
The comparator 530 compares the current sensing signal Vcs with a maximum current limit Vcs_max. Once the current sensing signal Vcs is above Vcs—max, an overcurrent signal (OC) is asserted. After a preset time, the controller 520-1 pulls the COMP signal to a low level using the switch 537. Once the COMP is pulled down to the low level by one or more phases, the duty cycle of all the phases are set to approximately zero by the PWM comparator 522. Because the feedback voltage FB drops below REF2 (e.g., FB_MIN), while COMP is low, all phases of the multiphase switching converter 500 enter the hiccup mode and start the hiccup timer at the same time, without requiring a communication bus. As described with respect to
The controllers 620 have similar structures and functionality and share the COMP signal and the Vsh signal, for which the respective nodes of the controllers 620 are coupled together. Further, output nodes of the error amplifiers of the controllers 620 are coupled together via a compensation circuit 640 to the ground potential.
The Vsh signal automatically equals to the lowest or highest Vcs in all phases of the multiphase switching converter 600. Once a Vcs value pf one of the power stages 610 is above the maximum current limit (VC_max), an overcurrent signal (OC) is asserted in this phase and the controller pulls down the signal Vsh to a low level. Once the signal Vsh is pulled down to the low value by at least one phase, all other phases of the multiphase switching converter 600 see that signal Vsh is low and the feedback voltage FB is low at the same time. According to the logic arrangement, all the phases of the multiphase switching converter 600 enter the hiccup mode and start the timer at the same time.
The master-slave multiphase switching converter 700 includes a master module and a number of slave modules. The master module includes a master power stage 710-M and a master controller 720-M. The slave module include a number of slave power stages such as a slave power stage 710-S, and a number of slave controllers 720 such as the slave controller 720-S. The master power stage 710-M is a low current module, whereas the slave power stages are high current modules. The master controller 720-M is similar to the controller 520-1 of
The master-slave multiphase switching converter 700 constructs the communication from the slave phases to the master phase. The feedback signal FB sampled from the output voltage Vo is connected to an inverting input of the transconductance amplifiers (gm) (e.g., 724) of the master controller. The outputs of the transconductance amplifiers are the COMP signal, which define the PWM duty ratio command signal that is shared with the slave controllers. The COMP signal is compared with the modulation ramp at the PWM comparator 722 to generate the duty cycle pulse (d).
For current balancing purpose, the current sensing signal Vcs from the master phase is set as the current command Vsh via an oval gain stage 750 with a gain equal to K. The current sharing loop of the slave phases compare its own Vcs with Vsh, and incrementally adjust its COMP signal applied to the PWM comparator, in order to make the current of the respective phase match the current of the master phase. Once the Vcs is above the maximum current limit Vcs_max, an overcurrent signal (OC) is asserted and the switch 737 of the controller 720-S pulls down the COMP signal to a low level. When the COMP signal is pulled down to the low value by any phase, the duty cycle of all the phases of the master-slave multiphase switching converter 700 are set to approximately zero. Because the feedback voltage FB drops below REF2 (e.g., FB_MTN) the COMP signal is low, the master controller 720-M enters the hiccup mode.
It is understood that the above disclosed embodiments can be extended to other switching power converters with active/passive switch current sensing or other inductor current sensing for different purposes.
The method 800 includes providing two or more switching converter modules using sequential switching pulses (810). The method 800 further includes configuring each switching converter module to include a power stage (e.g., 110 of
In some implementations, the method 800 further includes configuring the switching converter modules to operate in a current mode of operation. In the current mode of operation the over-current circuit can detect the over-current event by detecting that an output current of an error amplifier of the controller is higher than a preset value.
In one or more implementations, the command signal is a threshold current signal derived from an error amplifier of the control circuit, and the output nodes of over-current circuits of the switching converter modules are coupled via a compensation network to a ground potential.
In some implementations, the switching converter modules can operate in a voltage mode of operation. In the voltage mode of operation, the over-current circuit can detect the over -current event by detecting that a current sense voltage is greater than a preset voltage value.
In one or more implementations, the command signal is a comp voltage signal derived based on the output voltage or a signal controlling an inductor current such as ITH, and the output nodes of error amplifiers of the switching converter modules are coupled via a compensation network to a ground potential.
In one or more implementations, the command signal is a shared voltage signal derived based on a sensed current of an inductor of the power stage and is shared between the switching converter modules. Output nodes of error amplifiers can be coupled via a compensation network to a ground potential.
In summary, methods and circuits for overcurrent protection for multiphase switching converters is disclosed. The subject technology is robust to the current sharing performance, the matching of overcurrent limit between controllers, the phase number and/or the controller number, the closed loop bandwidth and the load condition. No communication bus for protection is needed.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure.
The predicate words “configured to”, “operable to”, and “programmed to” do not imply any particular tangible or intangible modification of a subject, but, rather, are intended to be used interchangeably. For example, a processor configured to monitor and control an operation or a component may also mean the processor being programmed to monitor and control the operation or the processor being operable to monitor and control the operation. Likewise, a processor configured to execute code can be construed as a processor programmed to execute code or operable to execute code.
A phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A phrase such as a configuration nay refer to one or more configurations and vice versa.
The word “example” is used herein to mean “serving as an example or illustration.” Any aspect or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs.
All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.” Furthermore, to the extent that the term “include,” “have,” or the like is used in the description or the claims, such term is intended to he inclusive in a manner similar to the term “comprise” as “comprise” is interpreted when employed as a transitional word in a claim.
