Claims
- 1. A digital processing system comprising:a digital signal processing core; a separate memory, said separate memory containing program code for operating said digital signal processing core; and a synchronous audio grade random access memory (SARAM) in communication with said digital signal processing core, wherein said SARAM contains one memory area for storing said program code to operate said digital signal processing core and for storing data generated by said digital signal processing core, and a separate area to encode or store speech.
- 2. The system of claim 1, wherein said digital signal processing core also contains an internal read-only memory.
- 3. The system of claim 1, wherein said digital signal processing core also contains internal random access memory.
- 4. The system of claim 1 wherein said separate memory comprises one or more memories selected from the group consisting of read-only memory (ROM), erasable programmable read-only memory (EPROM), and FLASH memory.
- 5. A telephone answering system comprising:a transceiver for receiving audio signals into said telephone answering system and transmitting audio signals therefrom; a digital signal processing core for processing said audio signals; a separate memory, said separate memory containing program code for operating said digital signal processing core; and an SARAM in communication with said digital signal processing core, said SARAM containing one memory area for storing said program code and for storing data generated by said digital signal processing core, and a separate area to encode for or store speech.
- 6. The system of claim 5, wherein said digital signal processing core also contains an internal read-only memory.
- 7. The system of claim 5, wherein said digital signal processing core also contains internal random access memory.
- 8. The system of claim 5, wherein said separate memory comprises one or more memories selected from the group consisting of read-only memory (ROM), erasable programmable read-only memory (EPROM), and FLASH memory.
Parent Case Info
This application claims the benefit of U.S. Provisional Application No. 60/100,854, filed on Sep. 18, 1998.
US Referenced Citations (4)
Non-Patent Literature Citations (1)
Entry |
Cosoroaba, Adrian B., “SDRAM—High Performance Memory Devices Running CPU Bus Speeds”, Proceedings of the IEEE Southeastcon '96, Apr. 1996, pp. 604-607. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/100854 |
Sep 1998 |
US |