Claims
- 1. A clocking control circuit for receiving an external start request signal for a microprocessor system including a microprocessor that is responsive to clocking pulses for processing instructions in a plurality of successive stages in each instruction cycle, said microprocessor having input/output data and address lines, said clocking control circuit comprising:
- a clock source for generating clocking pulses,
- phase tracking means coupled to said input/output data and address lines, said phase tracking means made operative by said clocking pulses for producing a phase pulse signal at a predetermined phase in each instruction cycle of said microprocessor, said predetermined phase of said phase tracking means occurrring when said input/output data and address lines of said microprocessor are operating at high impedance;
- means for generating a start signal based upon said external start request signal;
- receiving means for receiving a stop request signal from said microprocessor system, said stop request signal being generated when said microprocessor completes an instruction sequence; and
- synchronous logic means responsive to said phase pulse signal and said stop request for preventing the transfer of said clocking pulses from said clock source to said microprocessor, and responsive to said phase pulse signal and said start signal for permitting the transfer of said clocking pulses from said clock source to said microprocessor.
- 2. A clocking control circuit as recited in claim 1 wherein said microprocessor system includes peripheral devices, the clocking control circuit including means for transmitting to said peripheral devices said phase pulse signals identifying the current phase of the instruction cycle of said microprocessor and indicating access to said input/output data and address lines.
- 3. A clocking control circuit as recited in claim 2 wherein said microprocessor system includes memory means common to both said microprocessor and said peripheral devices, said phase pulse signals indicating permission for data transfers to occur between said microprocessor and said memory and between said peripheral devices and said memory when said microprocessor is being clocked and between said peripheral devices and said memory means when said microprocessor is not being clocked.
- 4. A clocking control circuit as recited in claim 1 wherein said microprocessor system includes memory means having address and data lines and said stop request signal is generated upon completion of a data transfer between said microprocesssor and memory means and said start request signal is generated in response to the initiation of a data transfer with said memory means.
Government Interests
The invention described herein was made in the performance of work under NASA Contract No. NDPR S63742-B and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958 (72 Stat. 435; 42 U.S.C. 2457).
US Referenced Citations (7)