Patent Grant
9651962
The present disclosure relates generally to an electronic device, and more particularly to a system and method for a linear voltage regulator.
Many electronic devices, such as microcontrollers, central processing units (CPU), memory devices, and the like, require a defined supply voltage. A linear voltage regulator may be used to provide such a defined supply voltage from an input voltage that is higher than the desired supply voltage. A linear voltage regulator includes a pass device, such as a transistor, connected between a supply input for receiving the input voltage and an output for providing the defined supply voltage to a load. A control circuit controls the pass device such that the supply voltage corresponds to a desired voltage.
The control circuit for a linear regulator may be implemented using analog control circuitry, digital control circuitry, or a combination of both. When digital control circuit and methods are used, the linear voltage regulator may include circuitry configured to sample the output of the power supply and convert the sampled output to the digital domain. Once the sampled output is processed in the digital domain, a control signal is applied to the pass device.
Some of the common specifications of a voltage regulator include load transient response, dropout voltage, output voltage ripple, and power supply rejection ratio. The load transient response pertains to how fast the voltage regulator responds to a changed load condition. This load transient response may be limited, for example, by stability considerations within the regulation loop. In some cases, the quantized and sampled nature of the digital controller may reduce the phase margin of the power supply.
The dropout voltage pertains to how low the regulator input voltage can approach the controlled output voltage and still maintain operation, and the voltage ripple pertains to the amplitude of a voltage disturbance is seen at the output voltage, which may be periodic in some cases. Again, the sampled and quantized nature of a digital controller may cause some voltage ripped in a digitally controlled linear voltage regulator. Lastly, the power supply rejection ratio pertains to how well the linear voltage regulator rejects changes in its supply voltage.
In accordance with an embodiment, a method of operating a power supply includes measuring an output signal of the power supply, determining a control voltage based on the measured output signal, and determining whether a supply voltage of a voltage follower circuit is greater than a first threshold. When the supply voltage of the voltage follower circuit is greater than the first threshold, the control voltage is applied to an input of the voltage follower circuit and an output of the voltage follower circuit is applied to a control node of an output transistor in a first mode. When the supply voltage of the voltage follower circuit is not greater than the first threshold, the voltage follower circuit is shut down and the control voltage is applied to the control node of the output transistor in a second mode.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present invention will be described with respect to preferred embodiments in a specific context: a system and method for a linear voltage regulator. While the example embodiments are addressed to a digitally controlled linear voltage regulator, the invention may be applied to other systems and applications including analog linear voltage regulators, power supply systems, control systems, and other electronic systems.
In embodiments of the present invention, a digitally controlled linear voltage regulator includes a pass device that is driven by a voltage follower transistor. This voltage follower transistor is driven by a resistor loaded continuous time current analog-to-digital converter (IDAC). During operation, power is supplied to the voltage follower transistor via an external power supply. However, under low supply conditions, the voltage follower transistor is bypassed and the pass device is directly driven by the output of the IDAC. The dynamic performance under these low supply conditions may be compensated by adjusting the digital control algorithm and by changing the resistive loading of the IDAC. Moreover, a low dropout voltage may be achieved by using a boosted power supply for the IDAC.
Stability of the digitally controlled linear voltage regulator is enhanced by designing the poles of associated with the voltage follower circuit and the output of the IDAC to be higher than the open loop bandwidth of the regulator, or to allow one of them to be compensated by the zero from the PID controller. In addition, low voltage ripple may be achieved by keeping a product of the IDAC LSB current and a load resistor to be less than an LSB of an analog to digital converter coupled to the input of the digital controller.
In an embodiment, ADC 110 is implemented using an 8-bit successive approximation ADC. ADC 110 operates using a 20 MHz clock and performs an analog-to-digital conversion in 13 clock cycles according to one specific example. It should be understood that, in alternative embodiments, an ADC having a different number of bits, a different clock frequency, and different specifications may be used. Moreover, ADCs of different architectures may also be used according to the particular specifications of the particular embodiment.
Digital controller 104 may be implemented using a processor that executes code, using hardwired logic, or using other digital logic known in the art. In one embodiment, digital controller 104 executes a digital control algorithm that may include, for example, a proportional-integral-differential (PID) controller. In some embodiments, digital controller 104 may also determine a loop error signal.
IDAC 108 produces an output current in response to a digital value provided by digital controller 104. In an embodiment, IDAC 108 may be implemented using a plurality of binary weighted current sources and/or thermometer coded unit current sources, or a combination thereof according to circuits and methods known in the art. Alternatively, other IDAC architectures may be used. In an embodiment, charge pump 106 provides a boosted power supply to IDAC 108 in order to increase its output compliance range. For example, in one embodiment, ADC 110 and digital controller 104 may be powered using a 1.5 V power supply, while IDAC 108 may operate using a 7.5 V power supply provided by charge pump 106. As such, ADC 110 and digital controller 104 may be implemented using, for example, fine geometry low voltage transistors, while some or all of the circuitry in IDAC 108 and charge pump 106 may be implemented using higher voltage devices. Alternatively, other power supply voltages and semiconductor technology partitioning may be used.
In some embodiments, optional DC voltage sources 132 and 134 may be placed in series with resistor 112 and transistor 114, respectively. By using voltage sources 132 and 134, the output range of IDAC 108 may be reduced, thereby decreasing the size of IDAC 108. In some embodiments, voltage source 132 and 134 may be adjustable and/or controllable.
In an embodiment, power supply voltages VDD1 that powers PMOS source follower transistor 114 and VDD2 that powers pass transistor 116 may range in voltage between about 5.5 V and about 40 V, while the controlled output voltage Vout of linear voltage regulator 100 may range in voltage between about 3.3 V and about 5 V depending on the how digital controller 104 is configured. Alternatively, other power supply voltage ranges and controlled output voltage ranges may be used.
As the voltage of VDD1 approaches 5.5 V, assuming a regulated output voltage of about 5V, bias network 122 may begin to fall out of compliance. For example, if VDD1 operates at 5.5 V, and Vout is set to be 5.0 Volts, there is very little headroom left, if any, for bias network 122 to provide current to PMOS source follower transistor 114. It should be understood that in other embodiments, bias network may begin to fall out of compliance when VDD1 reaches other voltages besides 5.5 V. The voltage at which there is a loss of compliance may depend, for example, on the regulated output voltage, the specific circuit architecture, the particular device technology used and various operating conditions.
Mode control circuit 111 is configured to sense this low voltage condition, for example, by monitoring the anode with respect to the cathode of the diode 118. If the diode is forward biased then mode control switches to a low drop mode. Otherwise, mode control circuit 111 indicates a normal mode. Alternatively, mode control circuit 111 may monitor this condition by measuring the voltage at input terminals VDD1 and/or VDD2 and/or Vout directly. For example, as shown in
Under nominal operating conditions, switch 118 is open to isolate the output of IDAC 108 from the source of PMOS voltage follower transistor 114, and switch 120 is closed to allow bias current from bias network 122 to flow though PMOS source follower transistor 114. Once the low voltage condition is detected by mode control circuit 111, switch 118 is closed and switch 120 is opened, thereby turning off PMOS source follower transistor 114 and connecting the output of IDAC 108 to the gate of pass transistor 116. The resistance of resistor 112 may be adjusted to compensate for a change in loop gain and loop dynamics due to the bypassing of PMOS source follower transistor 114, and/or to compensate for the change in bias conditions when PMOS source follower transistor 114 is bypassed. For example, as shown in
As shown, the resistance of R2 is greater than the resistance of R1. In an embodiment, by making R2 larger than R1, pass transistor 116 is controllable using a voltage IDACRANGE*R2, which permits more current to flow in the gate of pass transistor 116. The control algorithm implemented by digital controller may be adjusted to compensate for the increased resistance. In addition, the state of mode control circuit 111 may be provided to digital controller 104 in order to adjust the digital control algorithm to compensate for these changes in loop gain and/or loop dynamics due to the change in resistance and circuit configuration.
In an embodiment, IDAC 108 has a nominal output current of about 50 μA and PMOS source follower transistor 114 has a nominal bias current of about 100 μA. Pass transistor 116 may have a nominal output current of about 150 mA depending on the particular load conditions and digital controller configuration. In an embodiment, pass transistor 116 may be implemented using an n-channel DMOS transistor, however, in alternative embodiment, other transistor types such as a bipolar transistor such as a PNP, NPN a Darlington bipolar transistor, or simply an NMOS device may be used for PMOS source follower transistor 114 and/or pass transistor 116. In some embodiments, driving pass transistor 116 with a source follower improves power supply rejection performance because the gate of pass transistor 116 sees relatively low impedance. This low impedance may attenuate power supply disturbances that may be coupled to the output terminal Vout via the gate-drain capacitance of pass transistor 116.
In an embodiment, the analog circuitry of linear voltage regulator 100 has pole whose frequency is determined by load capacitor 124 and the resistance of load 126:
where ωPL is the plant pole angular frequency, RL is the load resistance, CL is the capacitance of capacitor 124, and gmOT is the transconductance of the pass transistor 116. In some embodiments, the dynamic response of the power supply is based on the closed loop response of the transfer function implemented by digital controller 104 and the pole at frequency ωPL.
The remaining system poles due to loading at the gates of PMOS source follower transistor 114 and pass transistor 116 may be configured to have a frequency that is higher than the open loop frequency fC
where ωP1 is the first pole angular frequency, R is the resistance of resistor 112 and CG-PMOS is the gate capacitance of PMOS source follower transistor 114. Likewise, a pole due to the source impedance of PMOS source follower transistor 114 and the gate capacitance of pass transistor 116 may be expressed as:
where ωP2 is the second pole angular frequency, gmSF is the transconductance of PMOS source follower transistor 114 and CG-DMOS is the gate capacitance of pass transistor 116.
In an embodiment, first and second pole frequencies ωP1 and ωP2 can be set to be at least ten times high than the open loop bandwidth of the regulator such that ωP1 & ωP2≧10·2πfC
In accordance with an embodiment, voltage ripple at of the regulated output voltage Vout may be decreased and/or eliminated by ensuring that one LSB of voltage output VDCSS of IDAC 108 is smaller than the step of one LSB of ADC 110 such that:
VDCCS=ILSBR<VADC-LSB,
where ILSB is the LSB current of IDAC 108 and VADC-LSB is the LSB voltage of ADC 110. By making one LSB of voltage output VDCSS of IDAC 108 smaller than the LSB of ADC 110, the controller is able to find a “rest point” in steady state conditions. When the controller settles to an output voltage VDCCS, which is within the zero error bin of the ADC, the error going into the controller will stay at zero in some embodiments. In some examples, the zero error bin of the ADC may be programmed to any desired value. Therefore, the controller in this condition causes a steady state where no changes occur, thus no ripple will be observed. In some embodiments, the VDCCS node is constantly being biased with a constant current, thereby compensating for leakages. Thus, a steady state condition can be found where all nodes stay biased at a specific voltage without requiring a change in current to readjust the output voltage. Once the linear regulator is operating in a same zero error bin, the output ripple is either significantly attenuated and/or eliminated.
In an embodiment, the bypassing of PMOS source follower transistor 114 is implemented using diodes 206 and 204. For example, when power supply voltage terminal VDD1 has sufficient headroom, diode 204 is forward biased to allow current flow from power supply terminal VDD1 to PMOS source follower transistor 114. In addition, the diode 206 coupled between the output of IDAC 108 and the source of PMOS source follower transistor 114 is reverse biased. When power supply terminal VDD1 experiences a low voltage condition, diode 204 becomes reverse biased and diode 206 becomes forward biased, thereby shutting off current flow to PMOS source follower transistor 114 and connecting the output of IDAC 108 to the gate of pass transistor 116. In some embodiments, the function of diodes 206 and 204 are analogous to the function of switches 118 and 120 shown in
In an embodiment, comparator 208 detects a low voltage condition of power supply input VDD1 by monitoring the gate-source voltage of PMOS source follower transistor 114. When the gate-source voltage of PMOS source follower transistor 114 becomes positive, thereby indicating that the transistor is shut off, the output Mode_Ctl of comparator 208 goes high indicating the low voltage condition. In some embodiments, output Mode_Ctl of comparator 208 is used to select the shunt resistance coupled to the output of IDAC 108. For example, when Mode_Ctl is low, the output of inverter 220 is high, and switch 216 connects the gate of transistor 214 to its gate, thereby creating a DC path from node VDCCS to ground via resistor R1. Accordingly, switch 218 connects the gate of transistor 210 to ground, thereby effectively disconnecting resistor R2. When Mode_Ctl is high, indicating a low voltage condition, switch 216 connects the gate of transistor 214 to ground, thereby disconnecting resistor R1, and switch 218 connects the gate of transistor 210 to its drain, thereby creating a DC path from node VDCCS to ground via resistor R2. In some embodiments, the output of comparator 208 is also coupled to digital controller 104 to provide an input signal for adjusting the control algorithm.
In some embodiments, optional DC voltage sources 211 and 215 may be placed in series with resistors R2 and R1, respectively. By using voltage sources 211 and 215, the output range of IDAC 108 may be reduced, thereby decreasing the size of IDAC 108. In some embodiments, voltage source 211 and 215 may be adjustable and/or controllable.
In some embodiments, transistor 212 is the same type of transistor as PMOS source follower transistor 114 and transistor 214 is the same type of transistor as pass transistor 116. By using replica transistors, the bias voltage at node VDCCS will track changes in the gate source voltages of PMOS source follower transistor 114 and pass transistor 116. Additional tracking accuracy may be obtained by thermally coupling transistor 214 with pass transistor 116. It should be understood the circuit for selecting resistors R1 and R2 is just one example of many possible selection circuits. For example, in some embodiments, the resistance coupled between node VDCCS and ground may be a switchable resistor network that couples and decouples a plurality of resistors coupled in series and or parallel. In further embodiments, the state of VDD1 may be monitored directly at terminal VDD1 and/or at other nodes within IC 202.
According to various embodiments, the output voltage Vout is divided prior to being digitized by ADC 110. As shown, a switched capacitor voltage divider that includes switch 240, capacitor C1 and capacitor C2 may be used to perform this voltage division. In one example, to perform a voltage division by n, capacitor C2 is set to a capacitance of about (1/n−1)C1. During operation, switch 240 grounds one terminal of capacitor C1 while capacitor C2 is grounded by internally circuitry within ADC 110. Next, capacitor C1 is reconnected to output voltage Vout such that the input to ADC 110 is the divided voltage. It should be understood that in alternative embodiments, other voltage divider circuits and methods known in the art, such as resistive voltage dividers, may be used.
In an embodiment, both IDAC1303 and IDAC2304 are active when VDD1 operates with excess headroom. In low voltage conditions, however, IDAC2304 is shut down and IDAC1303 alone supplies current to the gate of pass transistor 116. R2 is selected to be sufficiently larger R1 to maintain a bias for pass transistor 116 when only IDAC1303 having the smaller output current range is active. According to one embodiment, system 300 may be implemented as having two parallel control loops: one with IDAC1303 and one with IDAC2304. As such, IDAC2304 has its own controller 306 fed by summing element 308 that also implements a digital control algorithm, such as a PID control algorithm. Alternatively, other control algorithms may be used. In some implementations, the speed of both loops is approximately the same such that the coefficients for controllers 232 and 306 for both loops are proportional.
As shown, replica devices corresponding to PMOS source follower transistor 114 and pass transistor 116 are not coupled in series with resistor R1. Rather, transistor 314 is used to select resistor R1. Alternatively, replica devices may be used as shown in
where ωP1, is the first pole angular frequency, RDAC is the resistance of resistor 112 and CG-PMOS is the gate capacitance of PMOS source follower transistor 114. It should be appreciated that a similar modification may be made to other embodiment linear voltage regulators. For example, in some embodiments, IDAC 108 shown in
Advantages of embodiments of the present invention include good power supply rejection. Since the gate of the pass transistor is driven by a source follower, the low driving impedance is able to “absorb” high frequency disturbances injected into the gate though the drain-gate capacitance. As such, some embodiment circuits may achieve better EMC immunity. A further advantage includes good stability vs. dynamic performance. In embodiments where at least one of the poles associated with the voltage follower transistor and the gate of the pass transistors are selected to be, for example, ten times higher than the open loop frequency of the linear voltage regulator, more loop gain may be applied by the controller to speed up the response time of the regulator while maintaining a stable loop.
Another advantage of embodiments includes the ability to characterize the control loop as a simple, small signal AC model. For example, the programmable DC current of the IDACs may be modeled as a continuous current. A further advantage of some embodiments include low output voltage ripple. For example, in embodiments where the product of the IDAC and the load resistance has a smaller LSB than that of the ADC, ripple may be significantly attenuated and/or eliminated. A further advantage also includes good low voltage performance. In embodiments, that bypass the voltage follower transistor in low voltage conditions, control of the voltage regulator loop can be maintained.
In accordance with an embodiment, a method of operating a power supply includes measuring an output signal of the power supply, determining a control voltage based on the measured output signal, and determining whether a supply voltage of a voltage follower circuit is greater than a first threshold. When the supply voltage of the voltage follower circuit is greater than the first threshold, the control voltage is applied to an input of the voltage follower circuit and an output of the voltage follower circuit is applied to a control node of an output transistor in a first mode. When the supply voltage of the voltage follower circuit is not greater than the first threshold, the voltage follower circuit is shut down and the control voltage is applied to the control node of the output transistor in a second mode. Determining the control voltage may include using a digital-to-analog converter having a voltage output or a current output.
Determining the control voltage may include determining a continuous control current based on the measured output signal, and applying the continuous control current to a resistor to determine the control voltage. In some embodiments, the resistor has a first value during the first mode and a second value during the second mode, the first value less than the second value.
In an embodiment, determining the continuous control current includes applying a first control algorithm to the measured output signal in the first mode and applying a second control algorithm to the measured output signal in the second mode. In an some embodiments, the method further includes converting the measured output signal to the digital domain at a first resolution, performing a digital control algorithm on the converted measured output signal to determine a digital current value, and converting the digital current value into the continuous control current by performing a digital-to-analog conversion. A product of a current of a least significant bit of the continuous control current multiplied by a resistance of the resistor is less than the first resolution in some embodiments.
In accordance with an embodiment, an integrated circuit includes a power supply controller having an input coupled to a power supply output terminal of the integrated circuit, an output stage coupled to an output of the power supply controller, a follower circuit having an input coupled an output of the output stage, an output transistor having an input coupled to an output of the follower circuit and an output coupled to the power supply output terminal, and a supply selection circuit configured to provide supply current to the follower circuit from an external power supply terminal in a first mode when a voltage of the external power supply terminal is above a first threshold, and to shut off the follower circuit and provide a voltage to the input of the output transistor in a second mode when the voltage of the external power supply terminal is below the first threshold.
In accordance with a further embodiment, an integrated circuit includes a power supply controller having an input coupled to a power supply output terminal of the integrated circuit, and a boosted current output stage coupled to an output of the power supply controller, such that the boosted current output stage is configured to provide a continuous current. The integrated circuit further includes a follower circuit having an input coupled an output of the current output stage, a first shunt resistor coupled to the output of the current output stage, an output transistor having an input coupled to an output of the follower circuit and an output coupled to the power supply output terminal, and a supply selection circuit configured to provide supply current to the follower circuit from an external power supply terminal in a first mode when a voltage of the external power supply terminal is above a first threshold, and to shut off the follower circuit and provide a voltage to the input of the output transistor in a second mode when the voltage of the external power supply terminal is below the first threshold. The integrated circuit may further include a charge pump coupled to a supply input of the current output stage.
In an embodiment, the supply selection circuit includes a first diode coupled between the external power supply terminal and the output of the follower circuit, and a second diode coupled between the output of the current output stage. The integrated circuit may further include a second shunt resistor coupled to an output of the current output stage, and a resistor selection circuit configured to activate the first shunt resistor in the first mode and activate the second resistor in the second mode. The resistor selection circuit may further include a comparator having a first input coupled to the output of the current stage and the output of the follower circuit.
In an embodiment, the power supply controller includes an analog-to-digital converter (ADC) coupled to the power supply output terminal of the integrated circuit and a digital controller coupled to the output of the ADC, and the current output stage comprises a first current digital-to-analog converter (IDAC). The current output stage may further include a second IDAC configured to be active during the first mode and not during the second mode. An output range of the second IDAC is larger than an output range of the first IDAC in some embodiments. In one embodiment, the output range of the first IDAC is less 2 LSBs of the output range of the second IDAC.
In an embodiment, the digital controller may be configured to perform a first control algorithm in the first mode and a second control algorithm in the second mode. In some embodiments, the follower circuit includes a PMOS device and the output transistor includes a DMOS device.
In accordance with a further embodiment, a linear voltage regulator includes an analog-to-digital controller (ADC) having an input coupled to an output terminal of the linear voltage regulator, a digital controller coupled to an output of the analog-to-digital controller, a first current digital-to-analog converter (IDAC) having an input coupled to an output of the digital controller, and a first resistor coupled to an output of the first IDAC, such that a product of a current of a least significant bit of the IDAC multiplied by a resistance of the first resistor is less than a voltage of a least significant but of the ADC. The linear voltage regulator also includes a voltage follower circuit having a control node coupled to an output of the first IDAC; and an output transistor having a control node coupled to an output of the voltage follower circuit and an output node coupled to terminal output terminal of the linear voltage regulator. In some embodiments, the digital controller is configured to implement a digital proportional-integral-differential (PID) controller.
In an embodiment, at least one of a first open loop pole due to a resistance of the first resistor and an input impedance of the voltage circuit and a second open loop pole due to an output impedance of the voltage follower circuit and an input impedance of the output transistor is at least ten times an open loop bandwidth of the linear voltage regulator. An open loop response of the linear voltage regulator may include a first open loop pole due to a resistance of the first resistor and an input impedance of the voltage circuit, and a second open loop pole due to an output impedance. Moreover, a frequency of one of the first open loop pole and the second open loop is at least ten times an open loop bandwidth of the linear voltage regulator, and a frequency of the other one of the first open loop pole is substantially coincident with a zero implemented by the digital controller.
In an embodiment, the voltage follower circuit comprises a transistor of a first type, the output transistor includes a transistor of a second type, and the linear voltage regulator further includes a first series transistor of the first type coupled in series with the first resistor, and a second transistor of the second type coupled in series with the first resistor. In some embodiments, the first type is PMOS, and the second type is DMOS. Moreover, the output transistor and the second transistor of the second type may be thermally coupled.
In an embodiment, the linear voltage regulator further includes a first diode coupled between the output of the first IDAC and the output of the voltage follower; and a second diode coupled between a first power supply terminal and the output of the voltage follower. The linear voltage regulator may also include a comparator having a first input coupled to an input of the voltage follower circuit and a second input coupled to the output of the voltage follower circuit, and a second resistor coupled to the output of the first IDAC, such that the first resistor and the second resistor are selected according to an output state of the comparator.
In an embodiment, the digital controller includes an input node coupled to an output of the comparator, and the digital controller is configured to implement a first control algorithm when the output of the comparator is in a first state and to implement a second control algorithm when the output of the comparator is in a second state. In some embodiments, the linear voltage regulator further includes a second IDAC coupled between the digital controller and an input of the voltage follower circuit, such that the first IDAC includes an smaller output range than the second IDAC, and the second IDAC is configured to be active when the output of the comparator is in a first state and is configured to be inactive when the output of the comparator is in a second state. In some embodiments, an input of the first IDAC is coupled to a first n least significant bits of an output of the digital controller, and an input of the second IDAC is coupled to a first m most significant bits of the output of the digital controller.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, embodiment switch drivers could be used to tune oscillators by switching in and out capacitors and other tuning components. Embodiment switch driver circuits may also be applied to receive/transmit switches, attenuators, power amplifier bypass circuits, RF matching, RF filter switching in general, as well as other types of circuits and systems.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6188211 | Rincon-Mora | Feb 2001 | B1 |
| 7106032 | Chen et al. | Sep 2006 | B2 |
| 8716993 | Kadanka | May 2014 | B2 |
| 20090195234 | Arnold | Aug 2009 | A1 |
| 20100109624 | Lourens et al. | May 2010 | A1 |
| 20100207591 | Imura | Aug 2010 | A1 |
| 20120176109 | Riederer | Jul 2012 | A1 |
| 20130271095 | Jackum et al. | Oct 2013 | A1 |
| 20130285631 | Bisson et al. | Oct 2013 | A1 |
| 20130307501 | Kadanka | Nov 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 101807853 | Aug 2010 | CN |
| 102216867 | Oct 2011 | CN |
| 103376816 | Oct 2013 | CN |
| Entry |
|---|
| Bernardon, D. et al, “A high-precision low-drop linear regulator for battery charging application,” Proceedings of the 27th European Solid-State Circuits Conference, ESSCIRC 2001, Sep. 18-20, 2001, pp. 65,68. |
| Guo, J. et al., “A 6- μW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 45, No. 9, Sep. 2010, pp. 1896-1905. |
| Hazucha, P. et al., “Area-Efficient Linear Regulator With Ultra-Fast Load Regulation,” IEEE Journal of Solid-State Circuits, vol. 40, No. 4, Apr. 2005, pp. 933-940. |
| Jackum, T. et al., “A digitally controlled linear voltage regulator in a 65nm CMOS process,” 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 12-15, 2010, pp. 982,985. |
| Jackum,T. et al., “Fast Transient Response Capacitor-Free Linear Voltage Regulator in 65nm CMOS,” 2011 IEEE International Symposium on Circuits and Systems (ISCAS), May 15-18, 2011, pp. 905-908. |
| Number | Date | Country | |
|---|---|---|---|
| 20150346749 A1 | Dec 2015 | US |
