BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
FIG. 1 shows a circuit block diagram of a conventional system 10 for bandwidth sharing in a shared bus.
FIG. 2 shows a circuit block diagram of a system for bandwidth sharing in busses according to one embodiment of the present invention.
FIG. 3 shows the bus request signals REQ1 consecutively sent by the central processing unit shown in FIG. 2.
FIG. 4 shows a circuit block diagram of a system for bandwidth sharing in busses according to one alternative embodiment of the present invention.
FIG. 5 shows the bus grant signals GNT consecutively sent by the bus arbiter shown in FIG. 4.
FIG. 6 shows a circuit block diagram of a system for bandwidth sharing in busses according to another embodiment of the present invention.
FIG. 7 shows the bus request signals REQ1 consecutively sent by the central processing unit shown in FIG. 6.
FIG. 8 shows a circuit block diagram of a system for bandwidth sharing in busses according to another embodiment of the present invention.
FIG. 9 shows the bus grant signals GNT consecutively sent by the bus arbiter shown in FIG. 8.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 2 shows a circuit block diagram of a system 100 for bandwidth sharing in busses according to one embodiment of the present invention. The system 100 is preferably implemented in a system on chip (SOC) and includes a central processing unit (CPU) 102, a memory unit 104, a plurality of masters 106a, 106b and 106c, a shared bus 108, a bus arbiter 110 and a timer 112. The central processing unit 102, the memory unit 104 and the masters 106a, 106b and 106c are connected to the shared bus 108 and transmit data through the shared bus 108. The shared bus 108 is a priority-based shared bus, and the central processing unit 102 and the masters 106a, 106b and 106c have different priorities to use the shared bus 108. The bus arbiter 110 is for arbitrating the right for using the shared bus 108 among the central processing unit 102 and the masters 106a, 106b and 106c according to the ranking orders of the priorities of the central processing unit 102 and the masters 106a, 106b and 106c. The timer 112 is for counting a predetermined period of time T, and sends an enabling signal ENA to the central processing unit 102 after finishing the counting of the predetermined period of time T. The predetermined period of time T can be the time that the timer 112 spends for counting upward (or downward) from an initial value, e.g. 0 (or 99), to a predetermined value, e.g. 99 (or 0).
In this embodiment, each of the masters 106a, 106b and 106c represents a unit having the ability to access memories or peripheral devices and can complete data accessing operations by itself without the intervention of any central processing unit, e.g. the central processing unit 102. In addition, each of masters 106a, 106b and 106c can be any control circuit in peripheral devices such as DVD players, monitors, hard disks, network devices etc., and includes a direct memory access (DMA) controller respectively, for controlling its data transmission with other units, which are connected to the shared bus 108.
In the system 100 according to one embodiment of the present invention, the central processing unit 102 has the highest priority for using the shared bus 108. The master 106a is a master having real-time processing needs (hereinafter real-time master), and has a second highest priority for using the shared bus 108. The masters 106b and 106c are masters having no real-time processing needs and have the lowest priority for using the shared bus 108. When the central processing unit 102 and the masters 106a, 106b and 106c are in need of the shared bus 108 at the same time, they will send bus request signals REQ1, REQ2, REQ3 and REQ4 respectively to the bus arbiter 110. Next, the bus arbiter 110 receives the bus request signals REQ1, REQ2, REQ3 and REQ4 and grants the right of using the shared bus 108 according to the ranking orders of the priorities of the central processing unit 102 and the masters 106a, 106b and 106c, to the one having the highest priority. In this embodiment, the central processing unit 102 has the highest priority; therefore, after receiving the bus request signals REQ1, REQ2, REQ3 and REQ4, the bus arbiter 110 first sends a bus grant signal GNT to respond to the bus request signal REQ1 sent by the central processing unit 102 whereby granting the central processing unit 102 to use the shared bus 108 to transmit data first. When the central processing unit 102 finishes using the shared bus 108, the bus arbiter 110 then sends other bus grant signals GNT respectively to respond to the bus request signals REQ2, REQ3 and REQ4 whereby granting the masters 106a, 106b and 106c to use the shared bus 108 to transmit data.
As shown in FIG. 2 and FIG. 3, the timer 112 begins to count the predetermined period of time T after the central processing unit 102 sends a bus request signal REQ1, e.g. the bus request signal REQ1 sent at time t0 shown in FIG.3. When the timer 112 finishes counting the predetermined period of time T, it sends an enabling signal ENA to the central processing unit 102 for enabling the central processing unit 102 to send the next bus request signal REQ1, e.g. the bus request signal REQ1 sent at time t1 shown in FIG. 3. In this embodiment, after sending a bus request signal REQ1, the central processing unit 102 needs to wait until the timer 112 finishes counting the predetermined period of time T and receives the enabling signal ENA in order to send the next bus request signal REQ1 to the bus arbiter 110. Therefore, the time interval between two consecutive bus request signals REQ1 sent by the central processing unit 102 is limited by the predetermined period of time T; that is, the time interval between two consecutive bus request signals REQ1 is limited to be equal to or larger than the predetermined period of time T such that the probability that the central processing unit 102 uses the shared bus 108 is predictable. Take FIG. 3 for example, the central processing unit 102 can be predicted to send at most three bus request signals REQ1, i.e. the bus request signals REQ1 sent at time t0, t1 and t2 shown in FIG. 3, to the bus arbiter 110 within the period of time between time t0 and t2. In addition, when the bus arbiter 110 receives a bus request signal REQ1 every time, it sends a corresponding bus grant signal GNT to respond to the received bus request signal REQ1 whereby granting the central processing unit 102 to use the shared bus 108 to transmit data.
In this embodiment, the probability that the central processing unit 102 uses the shared bus 108 is predictable. Therefore, when the priority of the central processing unit 102 is set to be higher than that of the master 106a having real-time processing needs, the real-time master 106a can be designed or scheduled according to the probability that the shared bus 108 is used by the central processing unit 102, whereby preventing the problems of improper operations caused by not timely using the shared bus 108 to transmit data. For example, when the probability that the central processing unit 102 uses the shared bus 108 is predictable, the real-time master 106a can select a buffer having an appropriate size according to the probability that the shared bus 108 is used by the central processing unit 102, whereby preventing the problems of improper operations caused by not timely using the shared bus 108 to transmit data.
FIG. 4 shows a circuit block diagram of a system 200 for bandwidth sharing in busses according to one alternative embodiment of the present invention. The system 200 is preferably implemented in a system on chip (SOC). In FIG. 4, the elements, which are identical to those shown in FIG. 2, are indicated by the same numerals and will not be described in detail. The main difference between the system 200 and the system 100 shown in FIG. 2 is that the bus arbiter 110 can limit the time interval between two consecutive bus grant signals GNT, which are to be sent to the central processing unit 102, by a predetermined period of time T counted by a timer 212 and shown in FIG. 5; that is, the time interval between two consecutive bus grant signals GNT is limited to be equal to or larger than the predetermined period of time T such that the probability that the central processing unit 102 uses the shared bus 108 is predictable, whereby preventing the master 106a from operating improperly due to not timely using the shared bus 108 to transmit data.
FIG. 6 shows a circuit block diagram of a system 300 for bandwidth sharing in busses according to another embodiment of the present invention. The system 300 is preferably implemented in a system on chip. In FIG. 6, the elements, which are identical to those shown in FIG. 2, are indicated by the same numerals and will not be described in detail. The main difference between the system 300 and the system 100 shown in FIG. 2 is that the system 300 includes a timer 312 and a counter 314. The timer 312 is for counting a predetermined period of time T and can send a reset signal RST to the counter 314 after finishing the counting of the predetermined period of time T and then starts a re-count. The counter 314 is for counting the number of the bus request signals REQ1 sent by the central processing unit 102 during the predetermined period of time T and then re-counting it after receiving the reset signal RST.
Now referring to FIG. 6 and FIG. 7, when the timer 312 counts the predetermined period of time T (e.g. time t0 to t3), the counter 314 counts the number of the bus request signals REQ1 sent by the central processing unit 102. In the system 300 of the present invention, when the counter 314 counts to a predetermined number of bus request signals REQ1, e.g. three bus request signals REQ1 at time t0, t1 and t2 shown in FIG. 7, within the predetermined period of time T, the bus arbiter 110 may adjust the priority of the central processing unit 102 to be lower than the priority of the master 106a; therefore, the master 106a obtains the right for using the shared bus 108 after the central processing unit 102 sends three bus request signals REQ1 to the bus arbiter 110. When the timer 312 finishes counting the predetermined period of time T, it begins to re-count the next predetermined period of time T and sends the reset signal RST to the counter 314 such that the counter 314 can also begin to re-count the number of the bus request signals REQ1 sent by the central processing unit 102 during the next predetermined period of time T. Furthermore, when the timer 312 finishes counting the predetermined period of time T, the arbiter 110 may adjust the priority of the central processing unit 102 to be the highest such that the central processing unit 102 can have the right for using the shared bus 108 to transmit data first.
In this embodiment, the number of the bus request signals REQ1 sent by the central processing unit 102 within the predetermined period of time T is limited to a predetermined number (at least one); therefore, the probability that the central processing unit 102 uses the shared bus 108 is predictable such that the real-time master 106a can be designed or scheduled according to the probability that the shared bus 108 is used by the central processing unit 102, whereby preventing the problems of improper operations caused by not timely using the shared bus 108 to transmit data.
FIG. 8 shows a circuit block diagram of a system 400 for bandwidth sharing in a shared bus according to another alternative embodiment of the present invention. The system 400 is preferably implemented in a system on chip. In FIG. 8, the elements, which are identical to those shown in FIG. 2, are indicated by the same numerals and will not be described in detail. In FIG. 8, the system 400 includes a timer 412 and a counter 414. The timer 412 is for counting a predetermined period of time T, and it can send a reset signal RST to the counter 414 after finishing the counting of the predetermined period of time T and then starts a re-count. The counter 414 is for counting the number of the bus grant signals GNT sent by the bus arbiter 110 to the central processing unit 102 during the predetermined period of time T and then re-counting it after receiving the reset signal RST.
Now referring to FIG. 8 and FIG. 9, when the timer 412 counts the predetermined period of time T (e.g. time t0 to t3), the counter 414 counts the number of the bus grant signals GNT sent by the bus arbiter 110 to the central processing unit 102. In the system 400 of the present invention, when the counter 414 counts to a predetermined number of bus grant signals GNT, e.g. three bus grant signals GNT at time t0, t1 and t2 shown in FIG. 9, within the predetermined period of time T, the bus arbiter 110 may adjust the priority of the central processing unit 102 to be lower than the priority of the master 106a; therefore, the master 106a can obtain the right for using the shared bus 108 during the period from time t2 to t3 after the bus arbiter 110 sends three bus grant signals GNT to the central processing unit 102 consecutively. When the timer 412 finishes counting the predetermined period of time T, it begins to re-count the next predetermined period of time T and sends the reset signal RST to the counter 414 such that the counter 414 can also begin to re-count the number of the bus grant signals GNT sent by the bus arbiter 110 during the next predetermined period of time T. Furthermore, when the timer 412 finishes counting the predetermined period of time T, the bus arbiter 110 may adjust the priority of the central processing unit 102 to be the highest such that the central processing unit 102 can have the right for using the shared bus 108 to transmit data first.
In this embodiment, the number of the bus grant signals GNT sent by the bus arbiter 110 within the predetermined period of time T is limited to a predetermined number (at least one); therefore, the probability that the central processing unit 102 is granted to use the shared bus 108 is predictable such that the real-time master 106a can be designed or scheduled according to the probability that the shared bus 108 is used by the central processing unit 102, whereby preventing the problems of improper operations caused by not timely using the shared bus 108 to transmit data.
In the systems 100, 200, 300 and 400 according to the embodiments of the present invention, the central processing unit 102 can utilize a direct memory access (DMA) controller (not shown) to generate and send the bus request signals REQ1 to the bus arbiter 110, and also utilize it to receive the bus grant signals GNT responded by the bus arbiter 110.
In addition, the central processing unit 102 according to the embodiments of the present invention has the highest priority for using the shared bus 108; therefore, the MIPS rate of the central processing unit 102 can be effectively increased. In addition, the probability that the central processing unit 102 uses the shared bus 108 is predictable; therefore, the real-time master 106a can still timely use the shared bus 108 to transmit data and thus prevent the problems of improper operations while the MIPS rate of the central processing unit 102 is effectively increased.
According to other embodiments of the present invention, the shared bus 108 can also be prevented from staying idle. If the shared bus 108 stays idle, then the limitation described in the above embodiments, e.g. the limitation to the number of the request signals REQ or the number of the grant signals GNT and the limitation to the time interval between two consecutive request signals REQ or between two consecutive grant signals GNT, can be cancelled. For example, the limitations can be cancelled by resetting the counter such that the central processing unit 102 can execute access operations, e.g. reading or writing operations, with its highest speed.
The method for bandwidth sharing in busses according to the present invention is by setting the priority of the central processing unit 102 to be the highest and making the probability that the central processing unit 102 uses the shared bus 108 predictable whereby achieving the object of the present invention. In addition, it should be understood that, in the above embodiments, the method for bandwidth sharing in busses according to the present invention is applied to a system for bandwidth sharing in busses in which the right for using the shared bus 108 is arbitrated based on a priority scheme. However, in other embodiments, the method for bandwidth sharing in busses according to the present invention can also be applied to a system for bandwidth sharing in busses in which the right for using the shared bus 108 is arbitrated based on a round-robin scheme or a Time Division Multiple Access (TDMA) scheme.
Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Patent Application
20070245052
