Patent Application
20110142263
The present disclosure relates generally to power supplying systems, and more specifically, to a system and method for generating a bias voltage for an active device.
The bursty nature of highly dynamic loads causes current demands on a power regulator to go, for example, from a few micro Amps (pA) to tens of milli Amps (mA) within a short period of time (e.g., in the order of 3 nanoseconds (ns) for the case of an ultra wideband (UWB) application). Moreover, the power regulator has to recover from the initial burst and be ready for the next burst within a very short period (e.g., 10-20 ns for a pulse position UWB system). Along with this rapidly changing load requirement, there are load regulation specifications that typically restrict the maximum voltage ripple across the load to values below a few tens of milli Volts (mV).
The dynamic requirements typically associated with bursty load operations generally preclude the use of conventional voltage regulation schemes, such as Low Drop Out (LDO) regulators or Switch-Mode Power Supplies (SMPS) which, due to their inherent feedback regulation schemes and relatively low bandwidth, typically cannot react fast enough to the rapid changes of the load profile. As a consequence, one of the regulation aspects is invariably compromised: the ripple voltage, the regulation capabilities, or the regulation capacitance size which may become undesirably large.
The current solutions to tackle this type of requirements are generally ineffective in solving the problem. For example, the use of an LDO regulator for regulation of such a bursty supply would be difficult for the reason that the loop is not fast enough to regulate the supply within a very short time period (e.g., 12.5 ns). Moreover, the stringent requirements on the maximum droop tolerated generally require a very large bypass capacitor. Furthermore, the loop bandwidth of the LDO is limited by the stability requirement and an LDO with a few ns response is difficult to realize.
An aspect of the disclosure relates to an apparatus for generating a bias voltage for an active circuit. The apparatus comprises a first voltage source, a capacitive element adapted to generate a charge in response to the first voltage source, and a first switching element adapted to deliver the charge to be used to generate the bias voltage for the active device. In another aspect, the apparatus comprises a controller adapted to control a capacitance of the capacitive element. In yet another aspect, the controller is adapted to control the capacitance of the capacitive element based on one or more characteristics of the active device. In still another aspect, the one or more characteristic of the active device comprise a gain of the active device.
In another aspect of the disclosure, the controller is adapted to control the capacitance of the capacitive element based on a reference voltage. In another aspect, the reference voltage is based on one or more characteristics of the active device. In yet another aspect, the apparatus comprises a second voltage source adapted to generate the reference voltage.
In another aspect of the disclosure, the apparatus further comprises a second voltage source adapted to generate a second voltage that is also used to form the bias voltage. In another aspect, the second voltage source is adapted to produce a second voltage based on one or more characteristics of the active device. In still another aspect, the apparatus comprises a second switching element adapted to selectively couple the first voltage source to the active device to enable the active device. In yet another aspect, the apparatus comprises a second switching element adapted to selectively couple the active device to ground or other potential to disable the active device.
Other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the accompanying drawings.
Various aspects of the disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein are merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein.
In one aspect, the process of generating the bias voltage VB may involve the following operations: (1) coupling the voltage source module 102 to the capacitive element module 104 for a defined time interval to generate a defined amount of charge Q; (2) once the defined amount of charge Q is generated, decoupling the voltage source module 102 from the capacitive element module 104; and (3) then activating the switching element module 106 in order to couple the capacitive element module 104 to the active device 150, so that the charge Q is delivered to generate the bias voltage VB for the active device. This process may be more suitable for the case where leakage current associated with the biasing of the active device 150 is relatively small or negligible, so that the bias voltage VB remains substantially constant (e.g., a defined constant level) during the operation of the active device.
In another aspect, the process of forming the bias voltage VB may involve the following operations: (1) coupling the voltage source module 102 to the capacitive element module 104 for a defined time interval to generate a defined amount of charge Q; and (2) then activating the switching element module 106 in order to couple both the voltage source module 102 and the capacitive element module 104 to the active device 150, so that the charge Q and source voltage VS both contribute to generating the bias voltage VB for the active device. This process may be more suitable for the case where leakage current associated with biasing the active device 150 is significant, which may result in a significant drop in the bias voltage VB. Thus, in order to maintain the bias voltage VB substantially constant (e.g., a defined constant level) during the operation of the active device 150, the voltage source module 102 is maintained coupled to the active device.
In particular, the apparatus 200 comprises a first voltage source module 202, a capacitive element module 204, a first switching element module 206, a second voltage source module 208, a second switching element module 210, and a controller 212. Both the first voltage source 202 and the capacitive element module 204 are configured to generate a defined amount of charge Q under the control of the controller 212. More specifically, the first voltage source module 202 is adapted to generate a first voltage V1. The capacitive element module 204 is adapted to generate a charge Q based on and/or in response to the first voltage V1. The controller 212 may detect one or more characteristics of the active device 250, and may control the charge Q based on the detected one or more characteristics.
The second voltage source module 208 and the second switching element module 210 are adapted to generate a reference voltage V2 used for calibrating the capacitive element module 204. Additionally, the voltage V2 may be used as a supplemental voltage which, in conjunction with the charge Q generated by the capacitive element module 204, generates the bias voltage VB for the active device 250. For example, the supplemental voltage V2 may be used when there is significant leakage current associated with the biasing of the active device 250. In such a case, without the use of the supplemental voltage V2, the bias voltage VB may drop significantly during the operation of the active device 250. On the other hand, with the supplemental voltage V2, the bias voltage VB may be maintained within a defined voltage range. More specifically, the second voltage source 208 is adapted to generate the voltage V2 under the control of the controller 212. The controller 212 may detect one or more characteristics of the active device 250, and may control the supplemental voltage V2 based on the detected one or more characteristics.
Additionally, the controller 212 may configure the second voltage source module 208 to generate a reference voltage used for calibrating the capacitance of the capacitive element module 204. For example, the controller 212 may adjust the reference voltage V2 based one or more characteristics of the active device 250. Once the reference voltage is set, the controller 212 may activate the first voltage source module 202 and capacitive element module 204 to form charge Q, and develop a voltage at the output of the capacitive element module 204. Then, the controller 212 may adjust the capacitance of the capacitive element module 204 to adjust the voltage at its output based on the reference voltage V2. Finally, the controller 212 may selectively activate the first and/or second switching element modules 206 and 210 for delivering the charge Q and/or supplemental voltage V2 in order to generate the bias voltage VB for the active device 250.
In particular, the apparatus 300 comprises resistors R1, R2, and R3, capacitors CA and CB, switches S1-S6, comparator 302, and calibration controller 304. The power supply voltage Vdd, resistors R1 and R2, and switch S1 may be configured as the second voltage source module, as discussed above, to generate a reference or supplemental voltage V2. The power supply voltage Vdd, capacitors CA and CB, and switches S4A,
The switch S5 may be configured as the second switching element module, as discussed above, for selectively applying the supplemental voltage V2 to the input of the first switching element module (e.g., S2 and R3). As a reference, the voltage V2 is applied to an input of the comparator 302 for the purpose of calibrating the capacitive element module (e.g., CA and CB). The comparator 302 generates an output that is a function of the difference between the reference voltage V2 and the voltage associated with the charge Q. The control module 304 is adapted to adjust the capacitance of capacitors CA and CB and/or resistors R1 and R2 based on one or more characteristics (e.g., signal gain, bias voltage VB, etc.) of the active device MA. The processes related to the calibration of these parameters and the forming of the bias voltage VB are discussed further below with reference to flow and timing diagrams.
In this example, the active device MA may be configured as a metal oxide semiconductor field effect transistor (MOSFET). The active device MA may have an effective input capacitance of CP, which may include the gate-source capacitance of device MA, capacitance associated with bias resistor R4, and other parasitic capacitance. The switch S6 may be configured to selectively discharge the capacitor CP. The active device MA may be associated with other devices for, e.g., biasing, fast enabling/disabling, and frequency tuning of the device. For example, as discussed above, the resistor R4 may be configured to generate a defined source voltage or gate-source voltage for the device MA. The switches S3 and
(RF) amplifier (e.g., such as a low noise amplifier (LNA)), whereupon the gate of device MA is adapted to receive the input RF signal, and the drain of the device MA is adapted to produce the output RF signal. The load inductance LL may be configured to set a defined center frequency and bandwidth for the amplifier MA. It shall be understood that such amplifier is merely one example, and other variations and/or types may utilize the biasing technique described herein. For example, the amplifier could be a common source amplifier without degeneration resistor R4. Other types of amplifiers or devices that may need a bias voltage to settle in a relatively short period may utilize the techniques described herein.
With further reference to
The controller 304 then determines whether the one or more detected characteristics of the active device MA are within specification (block 612). If the one or more characteristics of the active device MA are not within specification, the controller 304 changes the voltage V2 by adjusting resistors R1 and/or R2 based on the one or more characteristics (block 614). As an example, if the gain of the active device MA is below specification, the controller 304 may adjust resistors R1 and/or R2 to increase the voltage V2 so as to increase the gain of the active device MA. On the other hand, if the gain of the active device MA is above specification, the controller 304 may adjust resistors R1 and/or R2 to decrease the voltage V2 so as to reduce the gain of the active device MA. The controller 304 repeats some or all of the operations of blocks 604 to 614 until the one or more characteristics of the active device MA are within specification.
If, in block 612, the controller 304 determines that the one or more characteristics of the active device MA is within specification, the controller 304 turns OFF switches S2 and S5 as well as the device bias (block 616). The controller 304 may then set an iteration count i to n, the number of binary-weighted capacitors in each capacitor bank (block 618). The controller 304 then turns ON switches S4Ai and S4Bi of the capacitor banks (the remaining capacitors in the banks may be turned OFF) (block 620). The controller 304 then compares the voltage at the output of the capacitive element module with the calibrated voltage V2 (block 622). The controller 304 then turns off either one of switches S4Ai and S4Bi based on the comparison (block 624). The controller 304 then decrements the iteration count i by one (block 626), and determines whether the iteration count i is equal to zero (block 628). If the iteration count i is not equal to zero, then the controller 304 repeats the operations specified in blocks 620 to 628. Otherwise, the controller 304 terminates the calibration procedure (block 630).
As a source communication device, data to be transmitted to a destination communication device is sent to the transmitter baseband processing module 816. The transmitter baseband processing module 816 processes the transmit data to generate an outbound baseband signal. The pulse modulator 818 generates pulses (e.g., ultra wideband (UWB) pulses) based on the outbound baseband signal. The second voltage regulator 820 supplies the charge at the proper time to the pulse modulator 818 in order for the pulse to be generated. The PA 822 amplifies the UWB pulses signal and provides it to the antenna 802 via the Tx/Rx isolation device 804 for transmission into a wireless medium. The second voltage regulator 820 also supplies charge at the proper time to the PA 822 in order for the pulse to be amplified. The transmit data may be generated by a sensor, a microprocessor, a microcontroller, a RISC processor, a keyboard, a pointing device such as a mouse or a track ball, an audio device, such as a headset, including a transducer such as a microphone, a medical device, a shoe, a robotic or mechanical device that generates data, a user interface, such as a touch-sensitive display, etc.
As a destination communication device, a received RF signal (e.g., inbound UWB pulses) is picked up by the antenna 802 and applied to the LNA 804, which amplifies the received RF signal. The first voltage regulator 808 supplies the charge at the proper time to the LNA 804 in order for the received signal to be amplified. The pulse demodulator 806 generates an inbound baseband signal based on the received UWB pulses. The first voltage regulator 808 also supplies the charge at the proper time to the pulse demodulator 808 in order to properly process the pulses. The receiver baseband processing 810 processes the incoming baseband signal to generate the received data. A data processor (not shown) may then perform one or more defined operations based on the received data. For example, the data processor may include a microprocessor, a microcontroller, a reduced instruction set computer (RISC) processor, a display, an audio device, such as a headset, including a transducer such as speakers, a medical device, a shoe, a watch, a robotic or mechanical device responsive to the data, a user interface, such as a display, one or more light emitting diodes (LED), etc.
The pulse repetition frequency (PRF) defined for a given channel may depend on the data rate or rates supported by that channel. For example, a channel supporting very low data rates (e.g., on the order of a few kilobits per second or Kbps) may employ a corresponding low pulse repetition frequency (PRF)). Conversely, a channel supporting relatively high data rates (e.g., on the order of a several megabits per second or Mbps) may employ a correspondingly higher pulse repetition frequency (PRF).
It should be appreciated that other techniques may be used to define channels in accordance with a pulse modulation schemes. For example, a channel may be defined based on different spreading pseudo-random number sequences, or some other suitable parameter or parameters. Moreover, a channel may be defined based on a combination of two or more parameters.
Any of the above aspects of the disclosure may be implemented in many different devices. For example, in addition to medical applications as discussed above, the aspects of the disclosure may be applied to health and fitness applications. Additionally, the aspects of the disclosure may be implemented in shoes for different types of applications. There are other multitudes of applications that may incorporate any aspect of the disclosure as described herein.
Various aspects of the disclosure have been described above. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein is merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. As an example of some of the above concepts, in some aspects concurrent channels may be established based on pulse repetition frequencies. In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two, which may be designed using source coding or some other technique), various forms of program or design code incorporating instructions (which may be referred to herein, for convenience, as “software” or a “software module”), or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented within or performed by an integrated circuit (“IC”), an access terminal, or an access point. The IC may comprise a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, electrical components, optical components, mechanical components, or any combination thereof designed to perform the functions described herein, and may execute codes or instructions that reside within the IC, outside of the IC, or both. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
It is understood that any specific order or hierarchy of steps in any disclosed process is an example of a sample approach. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The steps of a method or algorithm described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (e.g., including executable instructions and related data) and other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a “processor”) such the processor can read information (e.g., code) from and write information to the storage medium. A sample storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in user equipment. In the alternative, the processor and the storage medium may reside as discrete components in user equipment. Moreover, in some aspects any suitable computer-program product may comprise a computer-readable medium comprising codes relating to one or more of the aspects of the disclosure. In some aspects a computer program product may comprise packaging materials.
While the invention has been described in connection with various aspects, it will be understood that the invention is capable of further modifications. This application is intended to cover any variations, uses or adaptation of the invention following, in general, the principles of the invention, and including such departures from the present disclosure as come within the known and customary practice within the art to which the invention pertains.
