Patent Application
20150347151
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
The present disclosure relates in general to a technique for loading a driver for a computer system from a memory module, more particularly to a technique for loading the driver from a non-volatile memory of a dual in-line memory module (NVDIMM) or a co-processor input/output (CPIO) device. The present disclosure further relates to a technique to allow an operating system of the computer system to be booted from an NVDIMM or a CPIO device.
Computer systems have different hardware configurations depending on their hardware specification and computing environment. A computer system can boot its operating system (OS) from a variety of hardware components such as a hard disk drive, a USB thumb drive, a solid-state device (SSD), and a network card. A computer system may have a dedicated memory controller that is optimized for a specific type of memory; for example, double data-rate (DDR) dynamic random access memory (DRAM). While the computer system is booting, a firmware of the computer system (e.g., basic input/output system (BIOS)/unified extensible firmware interface (UEFI)) gains an access to a device connected to the computer system using a device driver.
A non-volatile dual in-line memory module (NVDIMM) is a computer memory module that retains data even when electrical power is removed either from an unexpected power loss, system crash or from a normal system shutdown. NVDIMMs may or may not include a DRAM that is accessible by the system and may require a driver to access a non-volatile memory. NVDIMMs improve application performance, data security, recovery time from a system crash and enhanced SSD endurance and reliability. There is a need for booting a computer system from a non-volatile memory of an NVDIMM that resides in a memory channel of the computer system.
A method of loading a driver and booting a computer system using a non-volatile memory of a memory module of the computer system is disclosed. According to one embodiment, a memory controller driver of a memory module of the computer system is stored in a non-volatile memory of the memory module. A memory controller of the memory module has a register that is set to indicate a location of the memory controller driver in the non-volatile memory of the memory module. The memory controller runs a state machine during a booting sequence of the computer system and determines the location of the memory controller driver of the memory module using the register. The memory controller driver is transferred from the non-volatile memory to a buffer of the memory controller and subsequently from the buffer of the memory controller into a main memory of the computer system. The computer system initializes the memory module using the memory controller driver. In one embodiment, the computer system uses the memory controller driver to access a non-volatile memory as a part of a normal boot process. In another embodiment, the computer system uses additional registers in the memory controller to boot the computer system using the same path as the memory controller driver is downloaded. Since the memory module driver may access the memory module using the main memory data-path, it is possible to access the memory module in an optimized manner.
According to another embodiment, a computer system comprises a memory module comprising a memory controller and a non-volatile memory, and an interface to access the non-volatile memory. The non-volatile memory of the memory module stores a memory controller driver of the memory module. The memory controller of the memory module comprises a register indicating a location of the memory controller driver and a buffer. The memory controller is configured to determine the location of the memory controller driver of the memory module using the register, and transfer the memory controller driver from the non-volatile memory to the buffer. A firmware of the computer system transfers the memory controller driver from the buffer of the memory controller to a main system memory and initializes the memory module using the memory controller driver.
The above and other preferred features, including various novel details of implementation and combination of events, will now be more particularly described with reference to the accompanying figures and pointed out in the claims. It will be understood that the particular systems and methods described herein are shown by way of illustration only and not as limitations. As will be understood by those skilled in the art, the principles and features described herein may be employed in various and numerous embodiments without departing from the scope of the present disclosure.
The accompanying drawings, which are included as part of the present specification, illustrate various embodiments and together with the general description given above and the detailed description of the various embodiments given below serve to explain and teach the principles described herein.
The figures are not necessarily drawn to scale and elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. The figures show examples of possible implementations of an NVDIMM or CPIO; however the teachings are applicable to other implementations without deviating from the present disclosure. The figures are only intended to facilitate the description of the various embodiments described herein. The figures do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims.
Each of the features and teachings disclosed herein can be utilized separately or in conjunction with other features and teachings to provide a system and method of booting a computer system from a non-volatile dual in-line memory module (NVDIMM) or a co-processor input/output (CPIO) device. Representative examples utilizing many of these additional features and teachings, both separately and in combination, are described in further detail with reference to the attached figures. This detailed description is merely intended to teach a person of skill in the art further details for practicing aspects of the present teachings and is not intended to limit the scope of the claims. Therefore, combinations of features disclosed above in the detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.
In the description below, for purposes of explanation only, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required to practice the teachings of the present disclosure.
Some portions of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are used by those skilled in the data processing arts to effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the below discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” “displaying,” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.
The algorithms presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems, computer servers, or personal computers may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.
Moreover, the various features of the representative examples and the dependent claims may be combined in ways that are not specifically and explicitly enumerated in order to provide additional useful embodiments of the present teachings. It is also expressly noted that all value ranges or indications of groups of entities disclose every possible intermediate value or intermediate entity for the purpose of an original disclosure, as well as for the purpose of restricting the claimed subject matter. It is also expressly noted that the dimensions and the shapes of the components shown in the figures are designed to help to understand how the present teachings are practiced, but are not intended to limit the dimensions and the shapes shown in the examples.
The present disclosure describes a system and method of accessing and controlling an NVDIMM or a CPIO in order to enable the booting of the computer from the NVDIMM or the CPIO device by downloading a driver from the NVDIMM or the CPIO device itself.
The present disclosure relates in general to techniques for accessing an NVDIMM or a CPIO device on a computer system such that the computer can boot from the NVDIMM or the CPIO device. NVDIMMs may be constructed with a combination of dynamic random access memory (DRAM) and a non-volatile memory, or a non-volatile memory alone. The term NVDIMM herein is used to refer to an NVDIMM, a CPIO device, or a combination thereof.
According to one embodiment, a computer system uses the system management bus (SMBUS) or inter-integrated circuit (I2C) bus to access a primary module driver via a basic input/output system (BIOS)/unified extensible firmware interface (UEFI). It is noted that the terms SMBUS and I2C are herein interchangeably used to designate a bus that is used to access a primary module driver. Depending on the system configuration, either SMBUS or I2C, or both SMBUS and I2C may be used to access the primary module driver. The primary module driver is a minimized driver that allows the BIOS/UEFI to configure the NVDIMM and accesses a non-volatile memory of the NVDIMM such that the operating system image can be retrieved through the DRAM channel. According to another embodiment, the primary module driver accesses the operating system image through the SMBUS. According to yet another embodiment, the primary module driver is located in a serial presence detect (SPD) EEPROM. According to yet another embodiment, a field in the SPD directs the BIOS/UEFI to access an application-specific integrated circuit (ASIC) that is located on the NVDIMM and provides a set of control and data registers that allows the BIOS/UEFI to access the primary module driver from another non-volatile memory on the NVDIMM. Multiple primary module driver images may be stored to provide different processor instruction sets or to provide in-field upgrade and downgrade of the boot loader. When multiple images are available, another set of registers in the memory controller provides a table of the images available.
Slower buses, including the PCI bus 114, a universal serial bus (USB) 115, and a serial advanced technology attachment (SATA) bus 116 are usually connected to a southbridge 107. The southbridge 107 generally refers to another chip in the chipset that is connected to the northbridge 106 via a direct media interface (DMI) bus 117. The southbridge 107 manages the information traffic between CPIO devices that are connected via a low-speed bus. For example, the sound card 104 typically connects to the computer system 100 via the PCI bus 114. Storage drives, such as the hard drive 108, typically connect to the computer system 100 via the SATA bus 116. A variety of other devices 109, ranging from a keyboard to an mp3 music player, may connect to the system 100 via the USB 115.
Similar to the main memory unit 102 (e.g., DRAM), the generic CPIO device 105 connects to a memory controller in the northbridge 106 via the main memory bus 112. For example, the generic CPIO device 105 may be inserted into a dual in-line memory module (DIMM) memory slot. Because the main memory bus 112 generally supports higher bandwidths (e.g., compared to the SATA bus 116), the exemplary computer system of
Although each of the block components is shown in
An NVDIMM or a CPIO device may include various components to be compatible with an unbuffered DIMM (UDIMM), a registered DIMM (RDIMM), or a load-reduced DIMM (LRDIMM).
Although DIMMs shown in
The NVDIMM/CPIO controller 201 provides a memory-mapped interface so that a software driver can control the NVDIMM/CPIO storage device 200. The NVDIMM/CPIO controller 201 also includes control circuitry for the re-timers 202 and an interface (e.g., SATA, SAS and PCIe) to the SSD controller 204. The SPD 205 stores information about the NVDIMM/CPIO storage device 200, such as its size (e.g., number of ranks of memory), data width, manufacturer, speed, and voltage and may be accessed via a system management bus (SMBus) 213. The SSD controller 204 manages the operations of the NVM devices 203, such as accessing (e.g., reading, writing, erasing) the data in the NVM devices 203. The NVDIMM/CPIO storage device 200 connects to the computer system's address/control bus 211 and main memory bus 212 via the NVDIMM/CPIO controller 201.
In this embodiment, the data buffer devices 203 buffer the connection between the CPIO storage device's (200) on-DIMM memory bus and the main memory bus 212. According to one embodiment, such as the embodiment illustrated by
The BIOS is a set of firmware instructions that is run by the computer system to set up the hardware and to boot into an operating system when it first powers on. After the computer system powers on, the BIOS accesses the SPD 205 via the SMBus 213 to determine the memory organization in the NVDIMM/CPIO storage device 200. Using this memory organization information, BIOS trains the DDR memory channel to enable communications with the DIMM(s). In cases when having access to the memory in the NVDIMM/CPIO ASIC is insufficient, a primary module driver is used to properly control the memory module.
An NVDIMM or a CPIO device may require a software driver to configure the NVDIMM/CPIO and access a non-volatile memory (e.g., SPD 205, 305, 405, 505, NVM 203, 303, 404, and 504) of
According to one embodiment, the computer system reads data stored in the SPD via the SMBUS. Traditionally, 256 or 512 bytes of data (which are contained in an SPD) are used by the BIOS/UEFI to identify configuration information about the DIMM. A size of a typical operating system is typically far too large to fit into the SPD. A primary driver may be too large to fit into the SPD, although a much larger SPD could be sufficient.
In cases when the primary driver is too large to fit into the SPD, the SMBUS provides an access method to the memory controller of the NVDIMM that does not require a DDR channel path that is operational. Referring to
In one embodiment, the non-volatile memory device is a bulk non-volatile storage. In another embodiment, the non-volatile memory device is a separate non-volatile chip (i.e., a serial NOR flash). The SMBUS interface provides read and/or write data in various sizes (e.g., 8-bit, 16-bit, and 32-bit). A single register write may provide sufficient information to instruct the NVDIMM ASIC to begin to transfer the primary driver from the non-volatile memory to a buffer in the NVDIMM ASIC. The BIOS/UEFI reads the buffer of the NVDIMM ASIC. After reading the primary driver, BIOS/UEFI initializes the NVDIMMs and begins to access the “boot” NVDIMM to get the operating system boot loader.
In one embodiment, an I2C interface (similar to the SPD) is used to connect to the NVDIMM ASIC. In the following examples with reference to
In step 0, the memory controller polls register 2 (status register) and waits for device ready for commands (bit 7==1). The memory controller writes 1 to register 1 (command register) to load a primary driver list, and waits for status complete by polling registers 2 and 3 (status register 2 bit 0==1 and command status register==0). Once the primary driver list is loaded, the memory controller reads the primary driver list from offset 128 (optionally computing CRC32 and checking against registers 20 to 23) and selects an appropriate driver.
In step 1, the memory controller writes 1 to register 4 (driver index) and writes 0 to registers 6 and 7 (in order to access the first 128 bytes of the driver) and writes 2 to register 1 (command register) to begin operation. After waiting for status complete by polling registers 2 and 3 (status registers), the memory controller reads the first 128 bytes of the primary driver from registers 128 to 255, and optionally computes CRC32 and checks against registers 20 to 23.
In step 2, the memory controller loops until all driver bytes are read by a) writing the next offset to registers 6 and 7 (incrementing the offset by 128), b) writing 2 to register 1 (command register), c) polling registers 2 and 3 (status registers) to wait for status complete and read the next 128 bytes of the primary driver from registers 128 to 255, and d) optionally computing CRC32 and check against registers 20 and 23.
In step 3, the memory controller executes the primary driver for each NVDIMM instance to initialize the NVDIMM operation. In step 4, the memory controller reads LBA size from register 3, writes starting LBA to registers 8 to 13, writes starting memory offset to registers 16 to 19, writes a length (in LBA size units) to registers 14 and 15, and executes a command to run the primary driver by writing 3 to register 1 (command register). After waiting for status complete by polling register 2 (status register), the memory controller copies data from the memory offset using a DDR channel. In step 6, the memory controller continues to read LBAs as required. It should be obvious to one ordinarily skilled in the art that the same control mechanism can be used for causing a write operation from the memory buffer to the non-volatile memory.
The access to the operating system boot loader via the SMBUS/I2C may be too slow. According to one embodiment, the present system uses a DDR channel to access the operating system boot loader. Access to the operating system boot loader via a DDR channel achieves a faster booting time. According to one embodiment, the present system provides multiple primary driver images including a number of different processor instructions sets that are programmed into the NVDIMM ASIC. Controller registers of the NVDIMM ASIC are used to select an appropriate primary driver image.
The above example embodiments have been described hereinabove to illustrate various embodiments of implementing a system and method of booting a computer system from a non-volatile memory. Various modifications and departures from the disclosed example embodiments will occur to those having ordinary skill in the art. The subject matter that is intended to be within the scope of the present disclosure is set forth in the following claims.
