BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of parasitic elements of a filter capacitor;
FIG. 2 is a schematic graph of a voltage spike brought by the filter capacitor of FIG. 1;
FIG. 3 is a schematic diagram of a hardware configuration of a system for calculating a voltage spike value in accordance with a preferred embodiment;
FIG. 4 is a schematic diagram of a voltage spike analyzing circuit simulated by a data processing unit of the system of FIG. 3; and
FIG. 5 is a flowchart of a method for calculating a voltage spike value in accordance with a preferred embodiment.