Patent Application
20110285683
This disclosure relates to modes of updating a display apparatus.
Electromechanical systems include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (e.g., mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in a display including a display element and a processor. In some implementations, the processor is configured to obtain images to be displayed. In some implementations, the processor is configured to select a line time addressing mode based at least in part on an update rate of images to be displayed. In some implementations, the line time addressing mode determines the amount of time that each display element is addressed by a common line. In some implementations, the processor is configured to update the display according to the line time addressing mode. In some implementations, the display can include an interferometric modulator (IMOD).
Another innovative aspect of the subject matter described in this disclosure can be implemented in a method of updating a display having a frame update rate and including display elements corresponding to common lines. In some implementations, the method includes obtaining images to be displayed. In some implementations, the method includes selecting a line time addressing mode based at least in part on an update rate of images to be displayed. In some implementations, the line time addressing mode determines the amount of time that each display element is addressed by a common line. In some implementation, the method includes updating the display according to the line time addressing mode. In some implementations, updating the display according to the line time addressing mode can include applying a waveform across a common line corresponding to display elements, the waveform having a front porch, write time, and back porch. In some implementations, the front porch can be approximately 12 microseconds, the write time can be approximately 70 microseconds, and the back porch can be approximately 47 microseconds. In some implementations, the line time addressing mode can correspond to the display having a frame rate of about 6.7 Hz. In some implementations, the front porch can be approximately 8 microseconds, the write time can be approximately 40 microseconds, and the back porch can be approximately 8 microseconds. In some implementations, the line time addressing mode can correspond to the display having a frame rate of about 15 Hz.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a system for driving a display having a frame update rate and including display elements corresponding to common lines. In some implementations, the system includes means for obtaining images to be displayed. In some implementations, the system includes means for selecting a line time addressing mode based at least in part on an update rate of images to be displayed. In some implementations, the line time addressing mode determines the amount of time that each display element is addressed by a common line. In some implementations, the system includes means for updating the display according to the line time addressing mode. In some implementations, the means for obtaining data to be displayed can include an input device. In some implementations, the means for selecting a line time addressing mode based at least in part on the update rate of images to be displayed can include a processor. In some implementations, the means for updating the display according to the line time addressing mode can include a common driver.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a computer program product for processing data for a program configured to drive a display having a frame update rate and including a display elements corresponding to common lines. In some implementations, the computer program product includes a non-transitory computer-readable medium having stored thereon code for causing processing circuitry to obtain images to be displayed. In some implementations, the computer program product includes a non-transitory computer-readable medium having stored thereon code for causing processing circuitry to select a line time addressing mode based at least in part on an update rate of images to be displayed. In some implementations, the line time addressing mode determines the amount of time that each display element is addressed by a common line. In some implementations, the computer program product includes a non-transitory computer-readable medium having stored thereon code for causing processing circuitry to update the display according to the line time addressing mode.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following detailed description is directed to certain implementations for the purposes of describing the innovative aspects. However, the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the implementations may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, bluetooth devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (e.g., MEMS and non-MEMS), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of electromechanical systems devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes, and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to a person having ordinary skill in the art.
Displaying data on MEMS display devices raises several considerations, including power consumption and user experience. MEMS devices are often used in portable electronic devices for which conserving battery power is important. Likewise, MEMS devices may suffer from low refresh rates which degrades user experience when displaying some types of data (e.g., video). Systems and methods are described herein which are configured to determine how to update a display based on the data to be displayed, resulting in increased power efficiency, maintenance of user experience, or both. In particular, systems and methods for determining when to update a display according to different line time modes are presented.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. First, power consumption by displays may be reduced. Second, the line time that corresponds to a desirable user experience may be selected and used to update the display.
An example of a suitable MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be on the order of 1-1000 um, while the gap 19 may be on the order of <10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which always produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example, FIGS. 6A-6E show examples of cross-sections of varying implementations of interferometric modulators, including the movable reflective layer 14 and its supporting structures.
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
Still with reference to
In certain displays, the time required to write data to the display elements will place constraints on the overall rate at which the display can be written to. If each common line is separately addressed, the write time necessary for each line will determine the overall frame write time. In certain implementations, an increased refresh rate or frame rate of the display may be desired, and may be more important than the resolution or color range of the display for a good visual appearance to a user. In particular implementations, driver circuitry and display arrays which are capable of presenting high resolution images with a wide color range may be utilized in a variety of different “modes” of strobing the common lines of the array. These modes may be designed to reduce one or both of the resolution and the color range and in turn increase the potential refresh rate of the display and/or reduce power consumption by strobing multiple lines of the array at the same time. These modes are explained further below, and are referred to herein as “multi-line addressing modes” of display controller operation. First, the operation of these modes will be explained, followed by novel methods of mode control.
In particular implementations, the resolution can be effectively reduced by simultaneously applying the same waveforms across common lines corresponding to display elements of the same color. For example, if a write waveform is simultaneously applied across red common lines 112a and 112b to address those common lines, the data pattern written to the interferometric modulators along common line 112a will be identical to the data pattern written to the interferometric modulators along common line 112b. If write waveforms are simultaneously applied across green common lines 114a and 114b, and then across blue common lines 116a and 116b, the data pattern written to pixel 130a will be identical to the data pattern written to pixel 130b, causing pixel 130a to display the same color as pixel 130b. Although the term “simultaneously” is used throughout this discussion for the purposes of conciseness, the voltage waveforms need not be perfectly synchronized. As discussed above with respect to
In comparison to a write process in which each common line is individually addressed, data has been written to pixels 130a and 130b in as little as half the time it would have taken to write separate data to pixels 130a and 130b, at the cost of decreased resolution. If this line multiplying process is applied to the remainder of the common lines in the display, the frame write time is considerably reduced.
In block 204, a plurality of data signals are applied along segment lines. Simultaneously, in block 206 a first write waveform is simultaneously applied to at least two common lines in the array to address the waveforms. Such a write waveform may include, for example, a positive or negative overdrive or address voltage appropriate for the common lines being addressed, as described with respect to
Although the flowchart of
In block 208, a determination is made as to whether any additional pairs or groups of common lines are to be simultaneously addressed. If so, the process returns to block 202 to select an appropriate pair or group of common lines to simultaneously address. If not, the process moves to further blocks which could include a termination of the frame write process if all necessary common lines have been addressed, or could include individual addressing of certain common lines. In addition, simultaneous addressing of pairs or groups of common lines may be interspersed with individual addressing of common lines, depending on the nature of the data to be written. For example, if a portion of the image data written to a display includes text or another still image, and another portion of the data includes a video which can be displayed at a lower resolution and which is located vertically between sections of text or still image, the portions of the display located above the video can be written by individually addressing those common lines, the portions of the display including the video can be written at a lower resolution by utilizing a line multiplying write process, and the write process may return to individual addressing of the common lines of the display for the portion of the display located below the video.
The particular method of line multiplication discussed above advantageously applies identical write waveforms to common lines in adjacent pixels, although other pairs of common lines may be simultaneously addressed in other implementations. Furthermore, even if the line multiplying method is used to simultaneously apply write waveforms to common lines in adjacent pixels, all of the lines in a given pair or group of pixels need not be written before writing lines in other groups of pixels. In particular, in certain implementations it may be advantageous to address multiple pairs or groups of common lines of the same color before addressing common lines of another color. For example, red common lines 112a and 112b may be simultaneously addressed, followed by a subsequent write process which simultaneously addresses red common lines 112c and 112d. Because different voltage waveforms may be used to address common lines of different color display elements, it may be advantageous to utilize the write waveform appropriate for a particular color for multiple pairs or groups of common lines before addressing common lines of another color. In particular implementations, any number of pairs or groups of common lines of a given color may be sequentially addressed before addressing common lines of another color. For example, in certain implementations, five pairs or groups of common lines of a given color may be addressed before common lines of another color are addressed, although larger or smaller numbers of pairs or groups may be used, as well.
In addition, although the simultaneous application of substantially identical waveforms to two common lines is discussed herein, further increases in refresh rate or frame write or reductions in power usage may be achieved by simultaneously applying substantially identical waveforms to more than two common lines.
In some methods of updating data on a display, charge buildup on particular display elements may be reduced by altering the polarity of the write waveforms applied to the common line. In one implementation, which may be referred to as frame inversion, a given frame is fully addressed using write waveforms of a particular polarity, and a subsequent frame is fully addressed using write waveforms of the opposite polarity. In further implementations, however, the polarity of write waveforms may be altered during a single frame write. In a particular implementation, which may be referred to as line inversion, the polarity of the write may be altered after addressing each line, and the polarity used to address a particular line will be changed in subsequent frames. If the display is being updated in a substantially linear fashion, this may result in adjacent lines being addressed by write voltages having opposite polarities. Thus, in certain implementations, it may be advantageous to utilize a given write waveform having a given polarity to write to, for example, every other red common line with a positive polarity for some number of common lines, before writing to the skipped red common lines with a negative polarity.
Polarity inversion within a frame can be applied to a write process in which line multiplying is used as well. In one implementation, red lines 112c and 112d may be addressed using the opposite polarity of that used to address red lines 112a and 112b within a given frame write. In an implementation such as the one described above where a write waveform with a given polarity is used for multiple sequential addressing operations, red lines 112a and 112b may be addressed using a first polarity, and red lines 112c and 112d may be skipped while some number of additional pairs or groups of red lines are written using the first polarity. After some number of pairs or groups have been addressed using the first polarity, red lines 112c and 112d may be addressed using the opposite polarity.
If polarity inversion is utilized, addressing a certain number of lines of one color using a first polarity need not be followed by addressing a certain number of lines in the same color using the opposite polarity. In other implementations, positive red write processes may be followed by, for example, negative blue write processes, or positive green write processes.
In another implementation, a color display may be driven in a monochrome mode or other mode which reduces the available color range. The process of updating a display in this manner can reduce the necessary time to refresh the display without decreasing the resolution of the display. In one implementation, the display can be driven in a monochrome manner by simultaneously applying write waveforms to adjacent common lines. For example, in an RGB display such as the one depicted in
In other implementations, the range of possible colors can be reduced to increase the potential refresh rate without reducing the display to a monochrome display. For example, in a display having display elements of three distinct colors, two of the colors in a given pixel may be simultaneously addressed while the other color is independently addressed, yielding a color range which is more robust than monochrome but less robust than that possible if all three colors were independently addressed. In alternate implementations, one or more color could be left unaddressed.
At block 302, a group of common lines to be addressed is selected. In a display having three different colors of display elements, such as an RGB display, the group of selected colors may include the adjacent common lines of each color extending through a given pixel. At block 304, data signals are simultaneously applied across a plurality of segment lines. At block 306, write waveforms are simultaneously applied across each of the selected common lines. As discussed above, because this process includes simultaneous addressing of display elements of different colors, different write waveforms specific to the color of the common lines may be used for each of the colors being addressed, although a single write waveform appropriate for all colors being addressed may also be used in alternate implementations. Given sufficient overlap between blocks 304 and 306, the data signals result in the writing of image data to the addressed common lines.
At block 308, a determination is made as to whether or not the next line write will be a monochrome line write which will simultaneously address multiple common lines. If yes, the process returns to block 302 to select the common lines to be simultaneously addressed. If not, the process may move on to other steps, including color line writes which address only a single common line, or the frame write may be complete.
In further implementations, line multiplying of the type discussed above may be used in only certain sections of a display, depending on the particular information to be displayed. Many implementations of display devices frequently display information such that large portions of the data is identical (or nearly identical) on different common lines. For example, space between lines of text on an eBook or other text display device may be solid white, or another color. In such an implementation, where the data to be written to pixels along multiple common lines remains constant for multiple common lines, the column lines sharing identical segment data may be written to or addressed simultaneously. When a write waveform is simultaneously applied to each of these common lines, the data on the segment lines will be written to each of the common lines being addressed. In addition to reducing the overall time required to complete a frame write, additional power can be saved by minimizing segment voltage switches.
Although the above implementations have described the use of 3×3 pixels, it will be understood that pixels and display elements of any desired size and shape may be used in conjunction with the methods and devices discussed herein. For example, if a pixel covers more than three segment lines, or if each of the segment lines are independent of one another, an increased color or grayscale range can be provided.
The above drive schemes and other techniques need not be used in conjunction with an increase in the refresh rate of a display. For example, many of the above methods can result in significant reductions in power consumption, and may be applied in order to reduce the power utilized by a display. A reduction in power usage may be of particular interest in battery-powered or other mobile devices where a reduction in power usage can result in longer battery life.
Sometimes, such as in the display of video or other animation, high refresh rate or frame rate may be more important to good visual appearance than the resolution of the display. For example, a low-resolution preview image may be shown and then replaced with a full-resolution image, or a GUI including a zooming animation may display the zooming animation at a lower resolution and then return to a higher resolution when the zooming animation is complete. In some implementations, resolution is sacrificed for higher frame rate by simultaneously applying identical voltage waveforms across multiple common lines.
In further implementations, when the resolution of the display is greater than the resolution of the source data, simultaneously writing identical data to multiple display elements can reduce the frame write time without having any negative visual effect on the resulting image, as identical data would already have been written to certain adjacent display elements. Video data, for example, is frequently viewed on displays which have a higher resolution than the video data itself, although many other types of image source data may be lower resolution than the display to which the image data will be written. The use of line multiplication to write the same data to multiple lines advantageously decreases the frame write time, increasing the possible refresh rate without a detrimental impact on the final display image.
It is one aspect of some implementations that these “multi-line addressing” modes can be entered and exited by the display controller under the control of host software. The host software has a large amount of information concerning the nature of the data that the host software wants to be displayed. Based on this information, the host can put the display controller into a mode that is optimal for the nature of the display data. For example, the host software may know that it is decoding a H.264 video stream that has a frame rate faster than the update rate for the display if the display had to update each line separately. In this case, the host may put the display controller into a multi-line addressing mode (with, for example, half the maximum display resolution) so that the display can keep up with the frame rate. This mode control could be provided, for example, by a register in the display controller that can be written to by the host, where the stored register value is read by the controller to determine its operational mode.
As another example, the host may determine whether the images to be displayed are changing. If the images are changing (e.g., video is being displayed), then the host may select a multi-line addressing mode corresponding to a higher frame rate. To determine whether an image or a portion of an image has changed, the host may compare one image to a subsequent image. The determination of whether an image has changed may include comparing an entire first image (or a portion thereof) to an entire second image (or a portion thereof). In some implementations, however, the host may instead compare the outputs of an algorithm that has been run on the image data. For example, the host may compare a cyclic redundancy check (CRC) value for the first image (or a portion thereof) to a CRC value of the second image (or a portion thereof).
As another example, the host may be sending QVGA data (320×240) to the display. As this is very low resolution image data compared with a typical pixel resolution of the display, the host could put the display controller in a 320×240 resolution multi-line addressing mode (for example, one quarter native resolution) to increase refresh rates and/or conserve power.
Another example is a host program receiving touch screen inputs such as a pinch for zooming that cause rapid display changes. The host could sense these inputs, and put the display into a low resolution, fast update mode during these updates, and then switch the display controller back to full resolution mode when the display data is no longer changing quickly. In some implementations, the host may automatically select a multi-line addressing mode in response to other user inputs, including but not limited to, input from a pointing device (e.g., mouse, touchpad, pointing stick, trackball, or stylus), an accelerometer, a keyboard, a gyroscope, a voice command, a camera, or any other tactile or non-tactile user input device.
In some cases, these modes could be entered and exited during writes of a single frame. If there is a mode register in the display controller, this could be checked between each line strobe (or between completion of each line of pixels) so that a multi-line addressing mode could be implemented for portions of a frame. This would be useful if the image data had significant regions of identical lines, where these regions could be addressed in a multi-line addressing mode as described above, but the rest of the frame is strobed a line at a time. In other cases, the controller can be configured to prevent mode changes from occurring too quickly when such changes detrimentally affect visual appearance of the display. If, for example, the controller is instructed to change modes, it could ensure that a certain number of lines or frames have been written using the current mode before making the switch.
If the host is running a web browser, for example, and a user is accessing web pages, the host may set the display controller to full resolution mode since frame updates with new images will occur infrequently. If a Flash® window with video is opened, a multi-line addressing mode can be set for those lines of the display that contain the window. These modes can also be selected by the host based on the status of a video window. Full resolution mode can be used if the video is paused or stopped, for example. In one implementation, where the mode selection is made by the host, the host may refrain from writing display data to the frame buffer that would be ignored in the line doubling mode. In this manner, the energy expended in writing data to the frame buffer could be saved.
In some implementations, the host and/or controller can use information about which lines of an image have changed in order to selectively update only lines that have changed more than some threshold amount. Using the video window display as an example, if the window is in one portion of the image, and the remainder of the image is not changing, then only the lines containing the window are updated. This can be combined with the multi-line addressing described above such that only the lines with the window are updated, and those lines are updated in a multi-line addressing mode.
With further reference to the example shown in
As noted above, in some displays, the time required to write data to the display elements will place constraints on the overall rate at which the display can be written to. If each common line is separately addressed, the write time necessary for each line will determine the overall frame write time. In some implementations, an increased refresh rate or frame rate of the display may be desired, and may be more important than the image quality or fidelity of the display for a good visual appearance to a user. In particular implementations, driver circuitry and display arrays may be utilized in a variety of different “modes” of strobing the common lines of the array. These modes may be designed to increase the potential refresh rate of the display or reduce power consumption by adjusting the time spent addressing each display element.
Modes that the host can control include modes that provide different amounts of time that a common line uses to address a display element during the writing of a frame. These modes are referred to here as “line time addressing modes.”
Thus, a trade off exists between line time (and thus the ultimate frame rate achievable) and display accuracy (image quality). Display processing techniques may exploit this trade off when optimizing for the display of particular data. For example, in an implementation optimized for still images, a line time corresponding to T2 may be utilized. This results in a very low level of pixel errors and higher image quality. Because the time required to perform each write is necessarily longer, a high frame rate is not achievable. However, because this implementation is optimized for still images, a high frame rate is also not necessary. It is also possible to reduce the segment voltage when longer line times are used. This can result in power savings as the power consumption of the display is a quadratic function of the segment voltage swings. However, if lower segment voltages are used, this must be balanced against the fact that longer write times result in longer delays before the display can go into its low power “hold” or “sleep” mode. Therefore, there is a point at which power savings from longer line times are less than if the display is allowed to go into hold/sleep mode more quickly.
In another implementation optimized for moving images, a faster frame rate is necessary. To achieve the faster frame rate, it is desirable to reduce the time required to write each frame. Shorter write cycles can help achieve this, and thus a write time corresponding to T1 may be utilized in these implementations. When a faster frame rate utilizes the short write times, the number of display errors will increase, per the error rate curve of
In implementations utilizing a shorter line time for displaying moving images, an additional implementation includes display processing algorithms that switch line time modes to perform a “clean up” frame write after detection of a stable image. The “clean up” frame write process utilizes a slower write cycle, at a reduced frame rate, in order to improve the quality of the stable image now being displayed. If the image begins changing again, the display processing algorithms can revert back to the short write cycles and fast frame rate needed to optimize the display for that imaging task.
In some embodiments, still image modes can also take advantage of short line time frame updates. For example, if a still image has been displayed for a period of time, and then a new still image is received for display (e.g. the next slide of a presentation or slide show), a short line time fast frame update can be performed first, followed by a long line time slow frame update to correct any errors left behind during the fast frame update. This makes the new image appear quickly, and also produces an accurate image.
When the line time is varied as described above, the length of time the addressing voltage is asserted is varied, and it may also be desirable to alter the length of the “front porch” and “back porch” portions of the waveform. Table 1 describes one implementation of different timing for each portion of the waveform for two display frame rates. A 6.7 Hz frame rate has been found adequate for a display consisting of fixed images, while a frame rate of at least 15 Hz may be used for moving images, video, etc. The “Total Line Time” of Table 1 is the total of the “front porch”, “write time”, and “back porch” timing, where all values are in microseconds. Hold time in Table 1 and
When a frame rate above 15 Hz is desirable, another implementation can achieve a frame rate of up to about 30 Hz by utilizing the shorter write timing corresponding to the 15 Hz mode as described in Table 1, along with the line doubled addressing modes described earlier. Because these multi-line addressing modes apply an addressing voltage to at least two common lines during one write cycle, extra current may be sourced by the power supply during each write cycle. As such, some implementations may extend the length of time the addressing voltage is applied to the common lines relative to the 15 Hz settings of Table 1. This ensures adequate power is applied to all attached display elements. Additionally, the length of time a release voltage 70 is applied to those common lines may also be extended slightly for optimal results.
The timing of
Thus, display processing may utilize variable frame rates and variable display element write timing. Depending on the incoming data, a 15 Hz update rate short line time full resolution mode can be selected, a 30 Hz line doubled reduced resolution mode can be selected, or a 6.7 Hz longer line time update mode can be selected. By varying the frame rate and write cycle timing, the displayed image can be optimized for the particular task of the display at a particular time.
In some implementations, a third line time mode can be used for those situations where a still image is displayed for a relatively long period. In this implementation, as the still image is displayed, every few seconds or minutes the frame can be re-written with the opposite polarity from the last frame update. Since there is so long between the updates in this case, and the image is not changed by the update, the line time can be even longer than the 6.7 Hz line time described above without any visible artifacts. How long a line time is used in this implementation will affect how long before the display apparatus can be put back into a hold/sleep mode at a reduced power consumption.
In some implementations, a host may automatically select a line time addressing mode based, at least in part, on the data to be displayed. In one implementation, the host may determine whether the images to be displayed are changing. If the images are changing (e.g., video is being displayed), then the host may select a line time addressing mode corresponding to a higher frame rate. To determine whether an image or a portion of an image has changed, the host may compare one image to a subsequent image. The determination of whether an image has changed may include comparing an entire first image (or a portion thereof) to an entire second image (or a portion thereof). In some implementations, the host may instead compare the outputs of an algorithm that has been run on the image data. For example, the host may compare the cyclic redundancy check (CRC) value for the first image (or a portion thereof) to the CRC value of the second image (or portion thereof). For example, if the image to be displayed has the same CRC value as the preceding image data, the host may select a line time addressing mode corresponding to a 6.7 Hz frame rate. Then, if a subsequent image to be displayed has a different CRC value from the preceding image data, the host may switch to a line time addressing mode that corresponds to a 15 Hz frame rate. Additionally, in response to a user input, the host may select both a line time addressing mode and a multi-line addressing mode that collectively correspond to a 30 Hz frame rate. For example, in response to a pinch-to-zoom user input, the host may select a line time addressing mode corresponding to a 15 Hz frame rate, as well as a multi-line addressing mode that provides line doubling, resulting in an overall frame rate of 30 Hz.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber, and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, e.g., data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g or n. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), NEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (e.g., an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (e.g., an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (e.g., a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation is common in highly integrated systems such as cellular phones, watches and other small-area displays.
In some implementations, the input device 48 can be configured to allow, e.g., a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices as are well known in the art. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
This disclosure claims priority to U.S. Provisional Patent Application No. 61/345,954, filed May 18, 2010, entitled “System and Method for Choosing Display Modes,” U.S. Provisional Patent Application No. 61/346,994, filed May 21, 2010, entitled “System and Method for Choosing Display Modes,” and U.S. Provisional Patent Application No. 61/405,610, filed Oct. 21, 2010, entitled “System and Method for Choosing Display Modes,” all of which are assigned to the assignee hereof. The disclosure of the prior applications are considered part of, and are incorporated by reference in, this disclosure.
| Number | Date | Country | |
|---|---|---|---|
| 61345954 | May 2010 | US | |
| 61346994 | May 2010 | US | |
| 61405610 | Oct 2010 | US |
