When producing hardcopy images using a laser printer, a latent image is first created on the surface of an insulating, photo-conducting material. This photo-conducting material is usually formed into a rotating drum. The insulating, photo-conducting material is made conductive when and where it is exposed to light.
Data, which defines the image to be printed, is used to modulate a laser that is scanned over the surface of the drum, line-by-line. A field of charges is applied over the surface of the drum. By selectively exposing areas on the surface of the drum with the laser, the charge in the exposed area is dissipated. This creates the latent image in the charge field on the drum that corresponds to the image represented by the data used to modulate the laser.
The latent image on the drum is then developed. A charged toner is applied to the surface of the drum. Because the toner is charged, the toner will be attracted to the latent image on the drum and repelled by other, unexposed portions of the drum surface. Thus, the latent image on the drum is developed and becomes a toner image on the drum surface.
The toner image is then transferred from the drum to a print medium, such as a sheet of paper. The toner is then fixed or fused to the print medium, typically with heat. The result is a hardcopy document bearing the image that corresponds to the data used to modulate the laser.
As used herein, the term “print engine” includes the devices used to actually produce a desired hardcopy document. Thus, a laser print engine includes, for example, a laser, a photoconductive drum, a transfer roller, laser modulation circuitry, the image data processing circuitry, etc. The speed at which a laser printer may print is limited mostly by the characteristics and physical mechanics of the print engine, i.e., the processing speed of the circuitry and the motion of the mechanical parts.
Within the data used to define the image being printed, the image is broken down into pixels. Each pixel is a small portion of the image. The pixels are arranged in successive lines to form the image. In monochromatic laser printing, each pixel is associated with a particular darkness or brightness along a grayscale. If a pixel is to be completely dark, then a maximum amount of black toner should be applied to that pixel during printing. Conversely, if the pixel is to be completely light, then no toner should be applied. In between these two extremes, varying amounts of toner are applied to produce various shades of gray.
The amount of toner applied within a pixel will be determined by how much of that pixel's area on the photo-conducting drum is exposed by the laser. By placing toner in only a varying portion of a pixel region, it is possible to create the effect of various shades of gray for each pixel and improve the resolution of the resulting image. Consequently, the laser can be pulsed for a selective amount of time within each pixel as it is scanned across each line of the image. The method of selectively pulsing the laser as described above is referred to as pulse width modulation (PWM).
To coordinate operations, complex devices, such as a laser printer, use clock signals. A laser printer can use two separate clock signals, a system clock and a video clock. The system clock regulates the operation of the data processing elements of the printer, e.g., the central processing unit (CPU) and memory. The system clock runs at a speed defined by processor performance. The video clock regulates the transfer of video data in synchronization with the operation of the print engine. The video clock may be a fixed-frequency crystal oscillator with a frequency that is selected to match the performance speed of the print engine. In other words, the period of the video clock is influenced by the physical mechanics, characteristics and limitations of the elements of the print engine. By choosing an appropriate video clock frequency, the transfer of video data is synchronized with the operation of the print engine.
However, using two unrelated clocks can cause other issues. First, delays may occur when data is transferred from the processor to the video circuitry of the print engine. Second, ASIC (Application Specific Integrated Circuit) design and testing for use in a printer is significantly hampered due to the difficulty of communicating using two different clock domains. Third, ASIC's designed for one print engine may have difficulty functioning with another print engine, thereby limiting the ability to reuse the ASIC in future laser printer development. Implementations that make use of a single clock, such as the system clock, for performing the functions of regulating the operation of the data processing elements of the printer and regulating the transfer of video data in synchronization with the operation of the print engine can encounter difficulties in dividing down the system clock for use by the video pixel generation circuitry.
In one of many possible embodiments, the present invention provides a method and system for clocking a video processing circuit by stalling a reference clock signal based on a stall signal from a clock-independent pulse width modulator.
The accompanying drawings illustrate various embodiments of the present invention and are a part of the specification. The illustrated embodiments are merely examples of the present invention and do not limit the scope of the invention.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.
Due to the issues that arise when two independent clock signals are used in a printing device, clock-independent pulse width modulation (CIPWM) was developed. See U.S. Pat. No. 6,366,307, issued on Apr. 2, 2002 to Morrison, entitled “Clock independent pulse width modulation,” and incorporated herein by reference. See also, U.S. Pat. No. 5,438,353, issued Aug. 1, 1995 to Morrison, entitled “Clock signal generator for electrophotographic printers;” and U.S. Pat. No. 5,760,816, issued Jun. 2, 1998 to Morrison, entitled “Variable phase clock generator for an electrophotographic printer,” both of which are incorporated by reference in their respective entireties. CIPWM makes it possible to use only one clock for the entire printing system, instead of two clocks.
CIPWM uses only a system clock and not a video clock. Instead of using a video clock to time data transfers, a circuit calculates when video data is needed and should be transferred. In particular, the CIPWM circuit generates a desired video signal by computing pulse edge offsets from the start of a scan line, i.e., the line through which a laser moves. In this way the CIPWM circuit determines at which system clock cycles to transmit video data from the processor to the video circuitry of the print engine and determines the placement of pixel boundaries.
In operation, CIPWM supplies video data during specific system clock cycles, and not at others instead of transferring data every clock cycle. Due to the erratic timing of the CIPWM technique, there is no practical way to slow down or divide down a system clock signal for the video pixel generation circuitry. Consequently, existing laser printer circuitry may be widely incompatible with the CIPWM technique.
Consequently, a method and system will be described herein for incorporating Clock Independent Pulse Width Modulation (CIPWM) with existing video processing circuitry used in laser printing. By clock gating, i.e., manipulating the clock signal, a system clock used for data processing in a laser printer may also function to drive the video image circuitry of the laser print engine.
As described above, laser printer technology has traditionally used two separate clocks, a system clock and a video clock, to drive the laser printer circuitry. The clock period of the video clock, the clock that runs the video image circuitry of the print engine, is determined by the operational speed of the print engine. In contrast, the system clock runs at a speed determined by the processor performance speed of the data processing elements of the printer, e.g., a central processor and memory.
Elements of the video processing circuit, including, the video data path (104), the video control block (105), and PWM (107), are driven by a video clock (102). The video clock (102), enables the video processing circuit to operate the laser at a speed synchronized with the physical movements of laser print engine.
The CIPWM modulator (211) enables the video processing circuitry of
The CIPWM control block (214) interacts with the FIFO (213) and the PWM (207) to coordinate the modulation of a laser used for laser printing. More specifically, the CIPWM control block (214) uses the reference clock (212) and the binary pulse width codes (206) being stacked in the FIFO (213) to determine a “synthesized” pixel rate at which to consume the binary pulse width codes (206).
In accordance with the synthesized pixel rate, the CIPWM modulator (211) produces a vdo_stall signal (209) which allows the video control block (205) to pace the video data path (204) such that binary pulse width codes are emitted only when the CIPWM modulator (211) needs them (as determined by the synthesized pixel rate).
The video control block (205) used with a CIPWM modulator (211) is different than the video control block (105,
In operation, the clock gating circuit (321) receives a reference clock signal (312), preferably based on a system (processor) clock, and a vdo_stall signal (309) from the CIPWM control block (314) of the CIPWM modulator (311). The output signal, video clock (302), allows the video image formatter (303) to output binary pulse width code (306) only when the CIPWM modulator (311) needs the data. The remaining operation of the video processing circuit of
By using a clock gating circuit (321) to effectively stall the clocking of the video image formatter (303) in accordance with the operation of the CIPWM modulator (311), the video control block (305) may be used without modification, i.e., existing video control ASIC's (Application Specific Integrated Circuits) may be used with CIPWM technology. This is in contrast to the video processing circuit of
The cost and design benefits of using existing video control circuitry (305,
As shown in
As shown in Table 1, the value of video clock (204) is logic “0” when both vdo_stall_smp (419) and reference clock (412) are both logic “0.” Any other combination of logic values for vdo_stall_smp (419) and reference clock (412) results in a logic “1” value for video clock (402).
During the time period T1 (531), reference clock (512) starts high and goes low, vdo_stall (509) is activated, i.e., a “high” is sent from the CIPWM modulator (311,
In time period T2 (532), reference clock (512) continues clocking at a fixed frequency, vdo_stall (509) remains in a high state, vdo_stall_smp (519) moves to a high state after a delay through a D flip-flop (422, FIG. 4), and video clock (502) switches to a high state.
In time period T3 (533), reference clock (512) continues clocking at a fixed frequency, vdo13 stall (509) is deactivated by the CIPWM modulator (311, FIG. 3), vdo_stall_smp (519) remains in a high state, and video clock (502) remains in a high state.
In time period T4, (534), reference clock (512) continues clocking at a fixed frequency, vdo_stall (509) remains in a low state, vdo_stall_smp (519) changes to a low state after a delay through a D flip-flop (422, FIG. 4), and video clock (502) begins to mirror the reference clock (512) again.
As shown in
The preceding description has been presented only to illustrate and describe embodiments of invention. It is not intended to be exhaustive or to limit the invention to any precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined by the following claims.
Number | Name | Date | Kind |
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5081477 | Gibson | Jan 1992 | A |
5546355 | Raatz et al. | Aug 1996 | A |
6014161 | Hirst et al. | Jan 2000 | A |
6191865 | Takahashi | Feb 2001 | B1 |
6366307 | Morrison | Apr 2002 | B1 |
Number | Date | Country | |
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20040145649 A1 | Jul 2004 | US |