The following relates to systems and methods for controlling string-level rapid shutdown devices for solar panel arrays.
Photovoltaic (PV) solar panels are typically constructed from a number of individual direct current (DC) PV cells connected in series and parallel. PV panels are also typically connected in series to each other to create a string of panels. Strings of PV panels are often connected in parallel in higher power systems. The strings are connected to an inverter, which converts the DC power generated by the panels into alternating current (AC) power that can be connected to an electrical grid.
Since PV panels produce power whenever they are in the presence of a source of illumination such as sunlight, the panels will continue to generate voltage even when the PV system is disconnected from the electrical grid, which can create safety hazards. For example, there are scenarios when the PV string should be isolated from the inverter when a so-called string disconnect condition occurs. Disconnect conditions can occur for various reasons, such as maintenance or repairs, equipment faults or failures, electrical grid faults, high resistance conditions, safety code requirements, and pre-installation to name a few. For example, certain safety codes have a “rapid shutdown” requirement to provide a zone outside of which the potential for shock hazards has been mitigated. Such a rapid shutdown that responds to these string disconnect conditions has been provided by rapid shutdown devices (RSDs) that disconnect a respective PV panel or the entire string from the inverter.
The cost of having an RSD for each PV panel can add significant cost to PV systems that have many panels.
It is an object of the following to address the above-noted disadvantages.
In one aspect, there is provided a method of controlling a string-level rapid shutdown device in a photovoltaic (PV) solar system comprising one or more strings of PV panels, the method comprising: while the rapid shutdown device is on, opening a pair of power switches used by the rapid shutdown device to connect the PV solar panels to an input of an inverter through a DC disconnect switch on an output side; determining a rate of voltage decay on the output side while the power switches are open; and controlling the power switches according to the rate of voltage decay.
In another aspect, there is provided a string-level rapid shutdown device for a photovoltaic (PV) solar system comprising a string of PV panels, the device comprising: an input side to connect to the PV solar system; an output side to connect to an inverter through a DC disconnect switch; a pair of power switches to connect the input side to the output side; circuitry to measure voltage decay on the output side; and a controller configured to, while the rapid shutdown device is on, open the pair of power switches to determine a rate of voltage decay on the output side while the power switches are open, and to control the power switches according to the rate of voltage decay.
In implementations of the method and device, the string-level rapid shutdown device is connected to a first string of PV panels, wherein the PV solar system further comprises another string-level shutdown device connected to a second string of PV panels connected to the first string of PV panels in parallel. The device is configured for, and the method comprises, controlling the string-level rapid shutdown device to have the power switches open for an overlapping interval with corresponding switches in the other string-level rapid shutdown device.
Embodiments will now be described by way of example only with reference to the appended drawings wherein:
Due to potential imbalances in voltage among strings containing PV panels (or two unequal strings in parallel), sensing current can be ineffective at determining whether or not an inverter is present. To address this concern, the following describes a system and method that monitors the rate of voltage decay on the inverter side of a string-level rapid shutdown device (SRSD). It has been found that the rate of voltage decay on the inverter side (i.e. at the inverter input) has a direct correlation to the impedance on that line, and thus whether the inverter capacitance is present or not, thereby sensing the presence of the inverter. In this way, the SRSD can determine when a closed DC disconnect switch is opened, and as a consequence, disconnect the PV string from the inverter.
Turning now to the figures,
The relative locations of the components shown in
In general, the SRSD 16 monitors the status of the DC disconnect switch 18 and disconnects the PV string 12 from the inverter 20 if the DC-disconnect switch 18 has been opened. After disconnecting the panel string 12 in response to a string disconnect condition, the SRSD 16 can be used to determine whether or not the string disconnect condition has been resolved and thus whether or not the panel string 12 can be reconnected to the inverter 20. This can be done by checking electrical continuity between the output of the SRSD 16 and the input of the inverter 20. If there is no electrical continuity to the input of the inverter 20, this can be considered indicative of the DC disconnect switch 18 being open.
On the other hand, if there is electrical continuity to the inverter 20, this could be indicative of the DC disconnect switch 18 being closed and that it would therefore be safe to have the SRSD 16 connect the panel string 12 to the inverter 20.
The SRSD 16 includes continuity testing circuitry that is coupled to the DC disconnect switch 18 and to the PV string 12, to enable the monitoring of the DC disconnect switch 18. The SRSD 16 also includes one or more controllers or control circuitry that can react or respond to the detection of a disconnect condition.
An example of a circuit topology for the SRSD 16 is shown in
When the SRSD 16 is in the “OFF” state, i.e. before connecting the PV string 12 to the inverter 20, the controller 42 implements computer executable instructions such as those shown in
Turning now to
At step 200, the SRSD 16 is in the ON state. The controller 142 uses the current sensing circuitry 144 at step 202 to measure the current flow in the SRSD 16. Within certain ranges of current, the process performs certain corresponding operations as follows.
At step 204, the controller 42 determines whether or not the current is above an upper threshold of X amps, for example 7 amps has been found to be suitable. When it is determined that the SRSD 16 is delivering power at above X amps of positive current flow, the power switches 134, 136 (referred to as FETs in the example shown in
The voltage decay during this momentary time period corresponds to a voltage drop on the output side, which is determined at step 212 by measuring the voltage at node 146. If the voltage drops below a particular threshold of Y % of its value when the switches 134, 136 were opened, the controller 142 determines that the DC disconnect switch 18 is open and executes step 214 to open the power switches 134, 136 and the SRSD 16 enters the OFF state at step 216. It has been found that a suitable voltage decay threshold Y is approximately 30% of the original voltage. On the other hand, if it is determined at step 212 that the voltage drop is above Y % (e.g., above 30%) of the original value, the controller 142 determines that the DC disconnect switch 18 is closed, and the power switches 134, 136 are re-closed and stay in the on (closed) state at step 206. The process shown in
As illustrated in
When two strings 12a, 12b are operating at a low inverter input current, in order to detect the open DC disconnect switch 18, the power switches 134, 136 in both SRSDs 16a, 16b should be controlled such that they are both open for some overlapping time interval. This may be done in several implementations, for example: 1) open the switches 134, 136 for long enough to ensure partial overlap; 2) detect when the switches 134, 136 in the other SRSD 16 are open, and then open your own switches 134, 136; and 3) randomize the period between switch openings such that the probability of both being open is deterministic.
Turning now to
For two strings in parallel 12a, 12b that are in steady state, wherein the switches 134/136 are closed and current is flowing from the PV strings 12a, 12b to the inverter 20, there are two cases to consider for sensing whether or not the DC disconnect switch 18 is open. These two cases are: 1) balanced strings 12; and 2) unbalanced strings 12.
In the first case, with balanced strings 12a, 12b, the SRSDs 16a, 16b would have positive or zero current and would open their power switches 134/136 for a certain amount of time (e.g., 5 ms), on a periodic basis, e.g., every 4.5 to 5 seconds at steps 306 and 308, to determine the voltage on the output side. If the total current is positive, a first of the SRSDs 16a opens its switches 134/136 for a certain amount of time (e.g., 5 ms), and when it is determined that the voltage drops below 30% at step 310, indicating that the inverter 20 is not present, the power switches 134/136 are kept open. The second of the SRSDs 16b then opens its switches 134/136 for the certain amount of time, thus providing an overlapping time when the switches 134/136 are open in both units 16a, 16b.
In this first case, if the total current is zero, or very low, e.g., less than 150 mA, the first SRSD 16a opens its switches 134/136 for a longer period of time, e.g., 150 ms. and if the voltage drop is less than 1V, the first of the SRSDs 16a keeps its switches 134/136 opened for a period of time, e.g., 6 seconds. The second SRSD 16b opens it switches 134/136 for the certain amount of time, every 4.5 to 5 seconds per the above example and, since the first SRSD 16a already has its switches 134/136 opened, both units 16a, 16b would have their switches 134/136 opened for an overlapping interval, in this example, of about 1 to 1.5 seconds.
In the second case, with unbalanced strings 12, a negative current would be flowing from the higher voltage string into the lower voltage string. The SRSD 16a that senses a positive current opens its switches 134/136 for a certain amount of time (e.g., 150 ms for 0 A, or 5 ms for between 0 A and 7 A). At this time, the current in the other SRSD 16b would change from negative to 0 A or otherwise positive. This event would trigger the second SRSD 16b to open its switches 134/136 for 6 seconds. It can be appreciated that at the next iteration when the first SRSD 16a opens its switches 134/136 for the certain amount of time, i.e. after 4.5 to 5 seconds, since the second SRSD 16b has already opened its switches 134/136 both units 16a, 16b would have their switches 134/136 opened for an overlapping interval, for example, 1 to 1.5 seconds.
As also shown in
For simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by those of ordinary skill in the art that the examples described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the examples described herein. Also, the description is not to be considered as limiting the scope of the examples described herein.
It will be appreciated that the examples and corresponding diagrams used herein are for illustrative purposes only. Different configurations and terminology can be used without departing from the principles expressed herein. For instance, components and modules can be added, deleted, modified, or arranged with differing connections without departing from these principles.
It will also be appreciated that any module or component exemplified herein that executes instructions may include or otherwise have access to computer readable media such as storage media, computer storage media, or data storage devices (removable and/or non-removable) such as, for example, magnetic disks, optical disks, or tape. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. Examples of computer storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by an application, module, or both. Any such computer storage media may be part of the SRSD 16, any controller 142 or other component thereof or related thereto, or accessible or connectable thereto. Any application or module herein described may be implemented using computer readable/executable instructions that may be stored or otherwise held by such computer readable media.
The steps or operations in the flow charts and diagrams described herein are just for example. There may be many variations to these steps or operations without departing from the principles discussed above. For instance, the steps may be performed in a differing order, or steps may be added, deleted, or modified.
Although the above principles have been described with reference to certain specific examples, various modifications thereof will be apparent to those skilled in the art as outlined in the appended claims.
This application is a continuation of PCT Application No. PCT/CA2017/050649 filed on May 29, 2017, which claims priority to U.S. Provisional Patent Application No. 62/351,767 filed on Jun. 17, 2016, both incorporated herein by reference.
Number | Date | Country | |
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62351767 | Jun 2016 | US |
Number | Date | Country | |
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Parent | PCT/CA2017/050649 | May 2017 | US |
Child | 16180963 | US |