For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:
Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of current sense amplifier are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.
Referring now to the drawings, and more particularly to
Referring now to
The high switching transistor 210 is driven by a control signal SW_HS provided from driver circuitry 211. The driver circuitry 211 additionally provides the SW_LS control signal for driving the low side switching transistor 208. The driver circuitry 211 generates the driver control signal responsive to a PWM control signal from a PWM controller 213. The PWM controller 213 generates the PWM control signal responsive to an error voltage signal received from an error amplifier 215 and a ramp voltage signal VRAMP. The error amplifier 215 generates the error voltage responsive to a reference voltage VREF and the output voltage VOUT with the voltage VLD provided from node 232 of the high side current sense amplifier 204 as will be more fully described hereinbelow.
The high side current sense amplifier 204 is connected to the buck regulator 202 at node 212 and node 214. A switch 222 is connected between the input voltage node 212 and node 224. A sense transistor 226 has its source/drain path connected between node 224 and node 228. Switch 222 is turned on and off responsive to a control signal SW_HS. The switch 222 eliminates the effect of the ringing on the PVIN node 212 when high side switching transistor 210 is turned on. When high side switching transistor 210 turns “on”, switch 222 is turned “on” with an appropriate delay responsive to control signal SW_HS. Switch 222 is turned “on” during the “off” time of switch 210 (i.e. during the on-time of switch 208), to prevent the high side current sense circuitry from being de-powered during the low side current sense time (causing the low side current sense circuit to be non-functional). Thus, the switch 222 is “on” during most of the switching cycle aside from a very short time in each switching cycle around the turn-on instant of high side switch 210. The gate of transistor 226 is connected to ground. A transistor 230 has its source/drain path connected between node 228 and node 232. Node 232 comprises the VLD node which provides the output of the high side current sense amplifier 204.
VLD is the measurement of inductor current used in the peak current mode control. A resistor 234 is connected between node 232 and ground. A capacitor 236 is in parallel with resistor 234 between node 232 and ground. An error amplifier 238 has its output connected to the gate of transistor 230. The inverting input of error amplifier 238 is connected to node 228 and the non-inverting input is connected to node 240. A switch 242 is connected between node 240 and node 244. Switch 242 is responsive to a control signal SW_HS. Switch 242 is closed when high side switching transistor 210 is turned on connecting node 240 to node 244. When the high side switching transistor 210 is turned off, switch 242 is open. When node 240 is connected to node 244, the high side offset voltage VOFF
The low side current sense amplifier 206 is connected to the buck regulator at the phase node 214 and VDD node 250. The low side current sense amplifier 206 is connected to the buck regulator 202 and high side current sense amplifier 204 through three separate switches. These include switch 252 connecting node 250 with node 224. Switch 252 is responsive to the SW_LS signal and is closed when the low side switching transistor 208 is turned on and opened when the low side switching transistor 208 is turned off. Switch 254 is connected between node 240 of the high side current sense amplifier 204 and node 256 of the low side current sense amplifier 206. Finally, a switch 258 connects node 260 of the low side current sense amplifier 206 to the phase node 214. A transistor 262 has its gate connected to ground and its source/drain path connected between node 250 (VDD) and node 256. A current mirror consisting of transistor 264 and 266 has a drain/source path of transistor 264 connected between node 250 and node 256 and its gate connected to transistor 266. The source/drain path of transistor 266 is connected between node 250 and node 268. A transistor 270 has its source/drain path connected between node 268 and node 272. A transistor 274 has its source/drain path connected between node 272 and ground. The gate of transistor 274 is connected to VIN since it is the sense MOSFET of LG. An offset voltage source IOFF
An error amplifier 278 has the output connected to the gate of transistor 270. Inverting input of error amplifier 278 is connected to node 272 and its non-inverting input is connected to node 280. A voltage source 282 is connected between the non-inverting input of the error amplifier 278 at node 280 and node 260. The positive terminal of voltage source VOFF
When the high side switch 210 turns off, switches 242 and 222 are opened and instead of pulling VLD to ground, switches 252, 254 and 258 are closed causing the low side current sense amplifier 206 to provide current information in concert with the high side current sense amplifier 204 at node VLD 232. Amplifier 278 within the low side current sense amplifier 206 forces the voltage drop across switching transistor 274 to equal the voltage drop across the lower transistor 208 plus the offset voltage VOFF
Referring now to
The ideal VLD signal 308 is provided at node 232 of the high side current sense amplifier 304. The high side current sense amplifier output VLD signal 308 increases and decreases in a similar fashion as the inductor current 306. The operation of the real VLD 310 signal is provided from the output of the high side current sense amplifier 304 in the real mode of operation. In the real mode of the operation, the real VLD signal 310 is pulled slightly lower at point 312 when the SW_HS signal goes low and the SW_LS signal goes high turning on the low side switching transistor and off the high side switching transistor.
The real VLD signal 310 will drop slightly from 312 to 314 as the circuit transitions from monitoring the inductor current using the high side current sense amplifier 204 to using the low side current sense amplifier 206. The real VLD signal 310 from point 314 to point 316 is generated responsive to the low side current sense amplifier 206 output that is provided to the high side current sense amplifier 204 such that a more accurate representation of the sensed inductor current is provided. Without the input from the low side current sense amplifier 206, the real VLD signal 310 would drop to zero when the high side switching transistor 210 is turned off and the low side switching transistor 208 is turned on. Thus, providing a more accurate representation of the sensed inductor current is provided via the VLD signal 310.
Voltage regulators and associated circuitry according to the embodiments of the present disclosure can be embodied as a variety of different types of electronic devices and systems, such as computers, cellular telephone, personal digital assistants, and industrial systems and devices. More specifically, some applications include, but are not limited to, CPU power regulators, chip regulators, point of load power regulators and memory regulators.
It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.
This application claims priority of U.S. Provisional Application No. 61/451,704, filed Mar. 11, 2011, entitled CURRENT SENSE AMPLIFIER (Atty. Dkt. No. INTS-30,672), the specification of which is incorporated herein by reference.
Number | Date | Country | |
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61451704 | Mar 2011 | US |