Patent Application
20140181334
Embodiments described herein generally relate to determining a latency tolerance in a processor environment.
As electronic apparatuses become more complex and ubiquitous in the everyday lives of users, more and more diverse requirements are placed upon them. For example, many electronic apparatuses can operate on battery power, thus allowing users to operate these devices in many different circumstances. In addition, as capabilities of electronic apparatuses become more extensive, many users have become reliant on the enhanced performance such capabilities provide. As these aspects of electronic apparatuses have evolved, there has become an increasing need for reducing power consumption. However, under many circumstances, reducing power consumption may sacrifice performance. Therefore, it will be highly beneficial for a user to be able to have the desired performance when it matters the most to them, and optimizing power performance during circumstances where performance may be less important to them. One possible area that may be advantageous for such improvements may pertain to the communication of latency concerns regarding devices of an electronic apparatus.
Embodiments are illustrated by way of example and not by way of limitation in the FIGURES of the accompanying drawings, in which like references indicate similar elements and in which:
The FIGURES of the drawings are not necessarily drawn to scale or proportion, as their dimensions, arrangements, and specifications can be varied considerably without departing from the scope of the present disclosure.
The following detailed description sets forth example embodiments of apparatuses, methods, and systems relating to providing a power savings in a processor environment. Features such as structure(s), function(s), and/or characteristic(s), for example, are described with reference to one embodiment as a matter of convenience; various embodiments may be implemented with any suitable one or more of the described features. It should be understood that terms such as “first”, “second”, etc. are merely used for differentiation purposes, and do not denote any sequential relationship, chronological relationship, and/or the like.
In electronic devices, there is often a tradeoff between power saving and performance. For example, lesser power saving states may have longer associated latency times than higher power saving states. In some circumstances, it may be desirable to avoid performance degradation associated with power saving. For example, if a device performs an operation that would benefit from the use of another device within a certain period of time, it may be desirable to influence power saving measures such that the power saving still allows the device to use the other device without undue delay. For example, a hard drive may benefit from avoiding circumstances where a processor is unable to receive information associated with a read operation due to power saving recovery. The amount of time in which a power saving feature should avoid interference with a device may be referred to as a latency tolerance. For example, if a device benefits from avoiding unavailability of another device after a specified period of time, the latency tolerance for the device may indicate a value of the specified period of time.
The example of
In at least one example embodiment, a device, such as device 164, sends information indicating a latency tolerance to a controller, such as USB controller 164. In such embodiments, the controller may receive information indicating the latency tolerance. In at least one embodiment, a controller, such as SATA/AHCI controller 106, sends information indicating a latency tolerance to power management controller 104. In at least one embodiment, a device, such as device 158, may send information indicating latency tolerance associated with the device to power management controller 104. Therefore, power management controller 104 may receive information indicating the latency tolerance.
Latency tolerance information provided to another component may be referred to as an upward latency tolerance. An upward latency tolerance may be provided to a component so that a device, a set of devices, a controller, a set of controllers, a platform, a set of platforms, and/or the like, may inform another component of latency tolerance associated with other components with which the component communicates. For example, a component may determine an upward latency tolerance and provide the upward latency tolerance to another component. In the example of
In at least one example embodiment, a controller, such as SATA/AHCI controller 106, is in communication with one or more devices, such as device 162. In such an embodiment, the controller may receive latency tolerance from each device with which the controller is in communication. In other words, the received latency tolerance may represent at least one device. The controller may determine a latency tolerance based on the received latency tolerance of the devices with which the controller is connected. For example, the controller may determine the latency tolerance to be the lowest value indicated by the reported latency tolerances. The controller may perform determination of the latency tolerance in response to receiving the reported latency tolerance. In other words, the device may cause the controller to determine the latency tolerance associated with the one or more devices by sending the latency tolerance to the controller. For example, if USB controller 108 is in communication with device 164 and other devices, device 164 may cause USB controller 108 to determine latency tolerance for device 164 and the other devices by sending a latency tolerance to USB controller 108.
In at least one example embodiment, power management controller 104 receives latency tolerance from each controller with which the controller, such as USB controller 108, is in communication. For at least the reason that each controller may be in communication with one or more devices, the received latency tolerance from a controller may represent one or more devices. Power management controller 104 may determine a latency tolerance based on the received latency tolerance of the controllers with which power management controller 104 is in communication. The latency tolerance determined by power management controller 104 may be referred to as the platform latency tolerance. The platform latency tolerance represents a latency tolerance associated with the collection of devices in communication with the controllers with which power management controller 104 is in communication. For example, power management controller 104 may determine the platform latency tolerance to be the lowest value indicated by the received latency tolerances of the controllers. Power management controller 104 may perform determination of the platform latency tolerance in response to receiving the latency tolerance. In other words, a controller, such as SATA/AHCI controller 106, may cause power management controller 104 to determine the platform latency tolerance associated with the one or more devices by providing an upward latency tolerance to power management controller 104. For example, USB controller 108 may cause power management controller 104 to determine the platform latency tolerance by sending an upward latency tolerance to power management controller 104.
There may be circumstances where at least one device does not send a latency tolerance to a controller. For example, the device may not support communication of a latency tolerance, a protocol used for communication between the device and the controller may not support communication of latency tolerance, and/or the like. In another example, even though the device may be capable of sending a latency tolerance, the sending may be delayed. Therefore, in such circumstances, there may be no latency tolerance received from a device. It may be desirable to determine a latency tolerance associated with such a device in the absence of a reported latency tolerance.
In the absence of receiving a latency tolerance from a device, a controller may determine a latency tolerance, to associate with the device, based, at least in part, on a link state of the device. In at least one example embodiment, link state information relates to information that indicates a power management status associated with a connection between components. For example, link state information may relate to link power management information provided by a USB standard, such as the USB 2.0 Link Power Management Addendum. In another example, link state information may relate to power management interface information, such as described in the SATA 3.0 Specification. Even though USB and SATA are discussed, it should be understood that USB and SATA are merely examples of protocols that may be utilized, and therefore does not serve to limit the claims in any way. For example, link state information associated with a different protocol may be utilized.
The controller may infer latency tolerance based on link state information. For example, link state information may indicate a power savings mode that a device and/or interface has entered. Under such circumstances, there may be a recovery time associated with the power savings mode. Therefore, a latency tolerance greater than or equal to the recovery time associated with the power savings mode may be determined. In an example embodiment, deeper link power savings modes are associated with higher latency tolerance values. For example, a longer power saving recovery time may correspond to a larger latency tolerance.
The latency tolerance may be determined based, at least in part, on the link state information by way of calculation, association with a predefined value, and/or the like. For example, determination of latency tolerance may comprise performing an algorithm for determining latency tolerance based, at least in part, on link state information. In another example, determination of latency tolerance may comprise retrieving a predetermined latency tolerance value associated with a particular link state value. In another example, determination of latency tolerance may comprise retrieving a predetermined value associated with a particular link state value, performing an algorithm for determining latency tolerance based, at least in part, on the predetermined latency tolerance value. The predetermined value may be set prior to operation, during operation, and/or the like. For example, the predetermined value may be set in a non-modifiable storage and/or in a modifiable storage. The predefined value may be set by the manufacturer of the apparatus, for example a manufacturer of platform chipset 102. The predefined value may be set by a manufacturer that utilizes the apparatus, such as an original equipment manufacturer (OEM). The predefined value may be programmable by basic input/output software (BIOS). The determined latency tolerance may be utilized as an upward latency tolerance.
In the example of
Circumstances where there are no outstanding SATA commands may indicate that the device is less active. Therefore, an apparatus may determine an upward latency tolerance based, at least in part, on information indicating SATA commands associated with the device. For example, an apparatus may increase the upward latency tolerance under circumstances where the information indicating SATA commands indicates no outstanding SATA commands. Additionally or alternatively, an apparatus may decrease the upward latency tolerance under circumstances where the information indicating SATA commands indicates no outstanding SATA commands. In at least one example embodiment, a value associated with LT_Active2 is larger than a value associated with LT_Active1. In at least one example embodiment, a value associated with LT_Partial2 is larger than a value associated with LT_Partial1.
In at least one example embodiment, LT_Idle relates to a value that has been negotiated with devices. For example, a USB controller, such as USB controller 108, may poll attached devices to determine a value for LT_Idle. Such a value for LT_Idle may be based on the smallest latency tolerance value that will satisfy the operational constraints of each device attached to the USB controller.
In the example of
Circumstances where there are periodic endpoints may indicate that the device is less active than circumstances where there are bulk endpoints. Therefore, an apparatus may determine an upward latency tolerance based, at least in part, on endpoint information associated with the device. For example, an apparatus may increase the upward latency tolerance under circumstances where endpoint information indicates periodic endpoints. Additionally or alternatively, an apparatus may decrease the upward latency tolerance under circumstances where the endpoint information indicates bulk endpoints. In at least one embodiment, a value associated with LT_Active2 is larger than a value associated with LT_Active1.
At block 302, the apparatus receives link state information associated with a device. The receiving of link state information may be similar as described regarding
In at least one example embodiment, a controller may be in communication with more than one device. Under such circumstances, the controller may base the upward latency tolerance on the more than one device. The upward latency may be based on link state of one or more device, on a determined latency tolerance of one or more device, a latency tolerance communicated by one or more device (for example a USB 3.0 device), and/or the like. In such circumstances, the upward latency tolerance may indicate the smallest latency tolerance associated with a device.
At block 402, the apparatus receives first link state information associated with a first device, similar as described regarding block 302 of
At block 502, the apparatus receives SATA link state information associated with a SATA device, similar as described regarding block 302 of
At block 602, the apparatus receives USB link state information associated with a USB device, similar as described regarding block 302 of
In this example of
ARM ecosystem SOC 1000 may also include a subscriber identity module (SIM) I/F 1030, a boot read-only memory (ROM) 1035, a synchronous dynamic random access memory (SDRAM) controller 1040, a flash controller 1045, a serial peripheral interface (SPI) master 1050, a suitable power management controller 1055, a dynamic RAM (DRAM) 1060, and flash 1065. In addition, one or more example embodiment include one or more communication capabilities, interfaces, and features such as instances of Bluetooth 1070, a 3 G modem 1075, a global positioning system (GPS) 1080, and an 802.11 WiFi 1085.
In operation, the example of
System control logic 1106, in at least one embodiment, includes any suitable interface controllers to provide for any suitable interface to at least one processor 1104 and/or to any suitable device or component in communication with system control logic 1106. System control logic 1106, in at least one example embodiment, includes one or more memory controllers to provide an interface to system memory 1108. System memory 1108 may be used to load and store data and/or instructions, for example, for system 1100. System memory 1108, in at least one example embodiment, includes any suitable volatile memory, such as suitable dynamic random access memory (DRAM) for example. System control logic 1106, in at least one example embodiment, includes one or more input/output (I/O) controllers to provide an interface to a display device, touch controller 1102, and non-volatile memory and/or storage device(s) 1110.
Non-volatile memory and/or storage device(s) 1110 may be used to store data and/or instructions, for example within software 1128. Non-volatile memory and/or storage device(s) 1110 may include any suitable non-volatile memory, such as flash memory for example, and/or may include any suitable non-volatile storage device(s), such as one or more hard disc drives (HDDs), one or more compact disc (CD) drives, and/or one or more digital versatile disc (DVD) drives for example.
Power management controller 1118 may include power management logic 1130 configured to control various power management and/or power saving functions disclosed herein or any part thereof. In at least one example embodiment, power management controller 1118 is configured to reduce the power consumption of components or devices of system 1100 that may either be operated at reduced power or turned off when the electronic device is in the closed configuration. For example, in at least one example embodiment, when the electronic device is in a closed configuration, power management controller 1118 performs one or more of the following: power down the unused portion of the display and/or any backlight associated therewith; allow one or more of processor(s) 1104 to go to a lower power state if less computing power is required in the closed configuration; and shutdown any devices and/or components, such as keyboard 108, that are unused when an electronic device is in the closed configuration.
Communications interface(s) 1120 may provide an interface for system 1100 to communicate over one or more networks and/or with any other suitable device. Communications interface(s) 1120 may include any suitable hardware and/or firmware. Communications interface(s) 1120, in at least one example embodiment, may include, for example, a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.
System control logic 1106, in at least one example embodiment, includes one or more input/output (I/O) controllers to provide an interface to any suitable input/output device(s) such as, for example, an audio device to help convert sound into corresponding digital signals and/or to help convert digital signals into corresponding sound, a camera, a camcorder, a printer, and/or a scanner.
For at least one example embodiment, at least one processor 1104 may be packaged together with logic for one or more controllers of system control logic 1106. In at least one example embodiment, at least one processor 1104 may be packaged together with logic for one or more controllers of system control logic 1106 to form a System in Package (SiP). In at least one example embodiment, at least one processor 1104 may be integrated on the same die with logic for one or more controllers of system control logic 1106. For at least one example embodiment, at least one processor 1104 may be integrated on the same die with logic for one or more controllers of system control logic 1106 to form a System on Chip (SoC).
For touch control, touch controller 1102 may include touch sensor interface circuitry 1122 and touch control logic 1124. Touch sensor interface circuitry 1122 may be coupled to detect touch input over a first touch surface layer and a second touch surface layer of display 11 (i.e., display device 1110). Touch sensor interface circuitry 1122 may include any suitable circuitry that may depend, for example, at least in part, on the touch-sensitive technology used for a touch input device. Touch sensor interface circuitry 1122, in one embodiment, may support any suitable multi-touch technology. Touch sensor interface circuitry 1122, in at least one embodiment, includes any suitable circuitry to convert analog signals corresponding to a first touch surface layer and a second surface layer into any suitable digital touch input data. Suitable digital touch input data for one embodiment may include, for example, touch location or coordinate data.
Touch control logic 1124 may be coupled to help control touch sensor interface circuitry 1122 in any suitable manner to detect touch input over a first touch surface layer and a second touch surface layer. Touch control logic 1124 for at least one example embodiment may also be coupled to output in any suitable manner digital touch input data corresponding to touch input detected by touch sensor interface circuitry 1122. Touch control logic 1124 may be implemented using any suitable logic, including any suitable hardware, firmware, and/or software logic (e.g., non-transitory tangible media), that may depend, for example, at least in part on the circuitry used for touch sensor interface circuitry 1122. Touch control logic 1124 for one embodiment may support any suitable multi-touch technology.
Touch control logic 1124 may be coupled to output digital touch input data to system control logic 1106 and/or at least one processor 1104 for processing. At least one processor 1104 for one embodiment may execute any suitable software to process digital touch input data output from touch control logic 1124. Suitable software may include, for example, any suitable driver software and/or any suitable application software. As illustrated in
Note that in some example implementations, the functions outlined herein may be implemented in conjunction with logic that is encoded in one or more tangible, non-transitory media (e.g., embedded logic provided in an application-specific integrated circuit (ASIC), in digital signal processor (DSP) instructions, software [potentially inclusive of object code and source code] to be executed by a processor, or other similar machine, etc.). In some of these instances, memory elements can store data used for the operations described herein. This includes the memory elements being able to store software, logic, code, or processor instructions that are executed to carry out the activities described herein. A processor can execute any type of instructions associated with the data to achieve the operations detailed herein. In one example, the processors could transform an element or an article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software/computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (e.g., a field programmable gate array (FPGA), a DSP, an erasable programmable read only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.
Note that with the examples provided above, as well as numerous other examples provided herein, interaction may be described in terms of layers, protocols, interfaces, spaces, and environments more generally. However, this has been done for purposes of clarity and example only. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of components. It should be appreciated that the architectures discussed herein (and its teachings) are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the present disclosure, as potentially applied to a myriad of other architectures.
It is also important to note that the blocks in the flow diagrams illustrate only some of the possible signaling scenarios and patterns that may be executed by, or within, the circuits discussed herein. Some of these blocks may be deleted or removed where appropriate, or these steps may be modified or changed considerably without departing from the scope of teachings provided herein. In addition, a number of these operations have been described as being executed concurrently with, or in parallel to, one or more additional operations. However, the timing of these operations may be altered considerably. The preceding operational flows have been offered for purposes of example and discussion. Substantial flexibility is provided by the present disclosure in that any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings provided herein.
It is also imperative to note that all of the Specifications, protocols, and relationships outlined herein (e.g., specific commands, timing intervals, supporting ancillary components, etc.) have only been offered for purposes of example and teaching only. Each of these data may be varied considerably without departing from the spirit of the present disclosure, or the scope of the appended claims. The specifications apply to many varying and non-limiting examples and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims. In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke paragraph six (6) of 35 U.S.C. section 112 as it exists on the date of the filing hereof unless the words “means for” or “step for” are specifically used in the particular claims; and (b) does not intend, by any statement in the Specification, to limit this disclosure in any way that is not otherwise reflected in the appended claims.
It should be understood that, even though various embodiments may be applicable to USB 3.0 standard, released November of 2008, other versions of this standard may be applicable. It should be understood that, even though various embodiments may be applicable to SATA revision 3.1 standard, released July of 2011, other versions of this standard may be applicable. It should be understood that, even though various embodiments may be applicable to AHCI 1.3 standard, released June of 2008, other versions of this standard may be applicable.
One particular example implementation may include an apparatus that includes a means for receiving first link state information associated with a first device, a means for determining, by a processor, an upward latency tolerance based, at least in part, on the first link state information, and a means for providing the upward latency tolerance to a power management controller.
