Patent Grant
10651876
Inductors and inductive components suffer from mutual coupling and therefore frequency of oscillators can be disturbed by other nearby electromagnetic fields. This effect is called frequency pulling. As a result, frequency pulling in transmitters (and receivers) may cause such devices to transmit (or receive) signals with altered carrier frequencies. An oscillator or oscillator circuit may generate a sinusoidal signal with a particular resonance frequency and harmonics (or multiples) of that particular resonance frequency. If an oscillator generates a sinusoidal signal with a resonance frequency ω0, harmonic frequencies may include the frequencies 2*ω0, 3*ω0, 4*ω0, and other multiples of ω0.
An example method disclosed herein in accordance with some embodiments may include: receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
According to the example method, in some embodiments, an oscillation frequency of the ILRO may be tuned to be substantially-near the carrier center frequency of the phase-modulated carrier output signal.
According to the example method, in some embodiments, generating the plurality of phases may further include tuning an oscillation frequency of the ILRO to be substantially near the carrier center frequency.
According to the example method, in some embodiments, generating the plurality of phases may further include injecting, by an injection circuit coupled to the ILRO, the phase-modulate carrier output signal into the ILRO.
The example method may further include, in some embodiments, transmitting the desired phase-modulated carrier output signal having the generated carrier center frequency equal to the desired carrier center frequency.
According to the example method, in some embodiments, the carrier center frequency of the phase-modulated carrier output signal may be 1.25 times the center frequency of the decoupled fractional frequency output signal.
According to the example method, in some embodiments, receiving the phase-modulated carrier output signal may include receiving phase-modulated carrier signals with phases of 0 degrees and 180 degrees.
According to the example method, in some embodiments, generating, by the ILRO, the plurality of phases of the phase-modulated carrier output signal generates phases of 0, 90, 180, and 270 degrees.
The example method may further include, in some embodiments, aligning the plurality of phases of the phase-modulated carrier output signal into a plurality of pairs of phases.
According to the example method, in some embodiments, generating the desired phase-modulated carrier output signal based on the decoupled fractional frequency output signal may include: dividing by 2 the center frequency of the decoupled fractional frequency output signal.
Further according to the example method, in some embodiments, dividing by 2 the center frequency of the decoupled fractional frequency output signal may include: triggering a divide-by-2 output signal to go high upon a rising edge of the decoupled fractional frequency output signal; and resetting the divide-by-2 output signal to low after an adjustable period of time, wherein a center frequency of the divide-by-2 output signal may be half the center frequency of the decoupled fractional frequency output signal.
According to the example method, in some embodiments, sequentially selecting successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases may include repeating a sequential process that may include: responsive to detecting a rising edge of a current phase of the plurality of phases, selecting a portion of a next phase of the plurality of phases; setting a next portion of the decoupled fractional frequency output signal equal to the selected portion of the next phase; and setting the current phase equal to the next phase.
Further according to the example method, in some embodiments, the sequential process may further include delaying the current phase prior to detecting the rising edge of the current phase.
An example apparatus disclosed herein in accordance with some embodiments may include: a digitally-controlled oscillator (DCO) circuit configured to output a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; an injection-locked ring oscillator (ILRO) configured to generate a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; and a fractional frequency division circuit coupled to the plurality of outputs of the ILRO, the fractional frequency division circuit configured to sequentially-select, using a multiplexer (MUX), successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases to generate a decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency.
According to the example apparatus, in some embodiments, the ILRO may be configured such that an oscillation frequency of the ILRO is tuned to be substantially-near the carrier center frequency of the phase-modulated carrier output signal.
The example apparatus may further include, in some embodiments, an injection circuit coupled to the ILRO and to an output of the DCO circuit and configured to inject the phase-modulate carrier output signal into the ILRO.
The example apparatus may further include, in some embodiments, an integer frequency division circuit coupled to the fractional frequency division circuit and configured to generate, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the DCO circuit, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
Further according to the example apparatus, in some embodiments, the integer frequency division circuit may be further configured to generate the desired phase-modulated carrier output signal based on the decoupled fractional frequency output signal by dividing by 2 the center frequency of the decoupled fractional frequency output signal. In some embodiments, the integer frequency division circuit may be further configured to trigger an integer frequency division output signal to go high upon a rising edge of the decoupled fractional frequency output signal. In some embodiments, the integer frequency division circuit may be further configured to reset the integer frequency division output signal to low after an adjustable period of time. In some embodiments, a center frequency of the integer frequency division output signal may be equal to half the center frequency of the fractional frequency output signal.
Further according to the example apparatus, the example apparatus may further include, in some embodiments, an amplifier configured to amplify the desired phase-modulated carrier output signal for transmission.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may include the MUX and multiple delay flip-flops, the multiple delay flip-flops having respective outputs configured to sequentially select the successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases.
According to the example apparatus, in some embodiments, the carrier center frequency of the phase-modulated carrier output signal may be 1.25 times the center frequency of the decoupled fractional frequency output signal.
According to the example apparatus, in some embodiments, the DCO circuit may be configured to output the phase-modulated carrier output signal with phases of 0 degrees and 180 degrees.
According to the example apparatus, in some embodiments, the ILRO may be further configured to generate the phases of 0, 90, 180, and 270 degrees of the phase-modulated carrier output signal.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may be further configured to align the plurality of phases of the phase-modulated carrier output signal into a plurality of pairs of phases.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may be configured to repeat a sequential process including: responsive to detecting a rising edge of a current phase of the plurality of phases, selecting a portion of a next phase of the plurality of phases; setting a next portion of the decoupled fractional frequency output signal equal to the selected portion of the next phase; and setting the current phase equal to the next phase.
Further according to the example apparatus, the example apparatus may further include, in some embodiments, a delay element coupled to the fractional frequency division circuit and configured to delay the current phase prior to detecting the rising edge of the current phase.
Another example apparatus disclosed herein in accordance with some embodiments may include: a processor; and a non-transitory computer-readable medium storing instructions that are operative, when executed by the processor, to perform the functions including: receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO) a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
The entities, connections, arrangements, and the like that are depicted in—and described in connection with—the various figures are presented by way of example and not by way of limitation. As such, any and all statements or other indications as to what a particular figure “depicts,” what a particular element or entity in a particular figure “is” or “has,” and any and all similar statements—that may in isolation and out of context be read as absolute and therefore limiting—may only properly be read as being constructively preceded by a clause such as “In at least one embodiment, . . . ” For brevity and clarity of presentation, this implied leading clause is not repeated ad nauseum in the detailed description of the drawings.
In accordance with some embodiments, to reduce frequency pulling, a fractional divider circuit may be used. Systems and methods described herein in accordance with some embodiments may use a fractional divider to reduce coupling between two or more inductive and/or capacitive elements for some embodiments. For example, an amplifier, such as a digital power amplifier, may have inductive elements that become coupled to inductive elements of a modulator circuit, such as a digitally-controlled oscillator circuit described herein.
The in-phase and quadrature signals from signal source 102 are provided to a coordinate rotation digital computer (CORDIC) logic circuit 104. The CORDIC logic circuit 104 converts the Cartesian I and Q signals to a corresponding polar signal that includes digital amplitude and phase signals. The amplitude signal Ain and the phase signal φin are provided through a polar signal input 106 to a polar transmitter 110. The polar transmitter 110 generates a phase-and-amplitude modulated radio-frequency (RF) output signal corresponding to the polar signal and transmits the signal at an antenna 108. In some embodiments, the radio-frequency signal, also referred to herein as a modulated carrier signal, has a frequency in the range of 2412 MHz-2484 MHz, although the use of the polar transmitter 110 is not limited to that frequency range. In general, a polar transmitter and/or transceiver in accordance with some of the embodiments disclosed herein may be used at any suitable frequency. Some particular frequency bands and ranges include those for LTE (4G) (e.g., 700 MHz-6 GHz), 5G (e.g., 600 MHz-6 GHz, 24-86 GHz), and any applicable frequency bands for standards such as LTE, GSM, WiMax and WiFi 802.11 standards (e.g., 2.4 GHz, 5 GHz, 900 MHz), although it will be understood that any frequency may be used in accordance with a particular implementation.
The polar transmitter 110 includes power amplifier circuitry (not shown) in
Some examples and implementations of, e.g., polar transmitter architecture and digital power amplifiers such as may be used, e.g., in the example polar coordinate conversion and polar transmission system 100 of
In some embodiments, the CORDIC logic circuit 104 may include a signal phase generator and a signal envelope generator (not shown in
In the example of
In some embodiments, the polar transmitter 110 of
In some embodiments, a frequency division circuit (FDC) 206 (including, e.g., phase generation and frequency division circuitry) may be placed between the DCO 204 and the power amplifier circuitry 208, as shown in
In accordance with some embodiments, to reduce frequency pulling, a fractional divider circuit may be used. Systems and methods described herein in accordance with some embodiments may use a fractional divider to reduce coupling between two or more inductive and/or capacitive elements for some embodiments. For example, an amplifier, such as a digital power amplifier, may have inductive elements that become coupled to inductive elements of a modulator circuit, such as a digitally-controlled oscillator circuit described herein.
A fractional divider circuit (FDC) 304 (such as FDC 206 of
An input of the fractional frequency division circuit 308 may be coupled to an output (e.g., one or more outputs) of the phase generation circuit 306. As will be described in more detail, in some embodiments, the fractional frequency division circuit 308 may be configured to select portions of the set of phase signals. In some embodiments, successively selecting later and later phases of a signal, the period of the signal may be extended. Due to the inverse relationship between the period and the frequency of the signal, the frequency decreases with increases in the period, and vice versa, and frequency division is performed. The fractional frequency division circuit 308 may generate a fractional frequency output signal with a center frequency equal to the phase-modulated carrier output signal's carrier center frequency divided by a non-integer divisor. In some embodiments, the fractional frequency division circuit 308 may generate an output signal with a duty cycle modified to correspond to an adjustment of the modulator carrier frequency. For example, the fractional frequency division circuit 308 may receive a set of phase signals with phases of 0, 90, 180, and 270 degrees, respectively. According to the example, each signal in the set of phase signals may have a duty cycle of 50% (such as a square wave with approximately 50% of the time with a voltage above 3.3V and approximately 50% of the time with a voltage below 0.8V). With some embodiments, the fractional frequency division circuit 308 may select portions of the phase signal inputs to generate an output signal with an adjusted duty cycle. For example, if the non-integer divisor is equal to 1.25, the output of the fractional frequency division circuit 308 may have a duty cycle of 40%. Of course, other duty cycles may be used. The output of the fractional frequency division circuit 308 may be generated by sequentially selecting portions of 4 quadrature phases (such as phase signals with phases of 0, 90, 180, and 270 degrees, respectively).
An input of a power amplifier (such as power amplifier circuitry 208 of
In some embodiments, an integer frequency division circuit such as a divide-by-N circuit (where N is a positive integer greater than 1) may be included before the DPA 310. In some embodiments, the fractional frequency division circuit 308 may include, e.g., a divide-by-N circuit such as a divide-by-2 (where N=2) circuit. In some embodiments, an integer frequency division circuit (a divide-by-N circuit, such as, e.g., a divide-by-2 circuit, where N=2) may be coupled between (not shown in
The present disclosure provides an example apparatus in accordance with some embodiments that includes: a processor; and a non-transitory computer-readable medium storing instructions that are operative, when executed by the processor, to perform functions including: receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase modulated carrier signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
For some embodiments, the DCO 402 may generate phase-modulated carrier output signals with phases of 0 degrees and 180 degrees, respectively, and a 50% duty cycle. In other embodiments, the DCO 402 may be used to generate phase-modulated carrier output signals with phases of 0 degrees and 180 degrees, respectively, and a 25% duty cycle.
For some embodiments, the ILRO 404 may be a sub-circuit of the phase generation circuit 306 shown in
In some embodiments, the ILRO 404 and/or the divider stages 406, 408 may be selectively disabled and, e.g., the output signals from the DCO may be provided directly to an output, e.g., to a DPA such as DPA 310 of
In some embodiments, each set of phase signals that are outputted by the ILRO 404 may be received by a non-integer fractional divider such as divide-by-1.25 circuit 406. Some embodiments of the divide-by-1.25 circuit 406 may be used to divide a carrier frequency of an input signal by a non-integer divisor equal to 1.25. For some embodiments, the divide-by-1.25 circuit 406 may output two phases of a fractional frequency output signal. The carrier frequency of the two phase signal outputs (or fractional frequency output signal(s)) may be divided by 2 by a divide-by-2 circuit 408 to generate 4 phase outputs. Some embodiments of the fractional frequency division circuit 308 of
In operation, with some embodiments, the DCO may operate at 2.5*f0, (e.g., 1.25*2=2.5) where f0 is the carrier frequency of an RF transmitted signal. In some embodiments, if f0 is between 1.6 GHz and 2.0 GHz, the DCO may operate at 2.5*f0, which correlates to a DCO frequency range of 4 GHz to 5 GHz.
Using one frequency range as a non-limiting illustrative example, in some embodiments, to transmit an RF signal in the mid-band (MB) and industrial, scientific, and medical (ISM) frequency ranges (1.7 GHz-2.5 GHz), the frequency of the DCO 402 may be set to a frequency between 4.25 GHz and 6.25 GHz, e.g., 2.5*f0, (e.g., 1.25*2=2.5). For example, at the lower end of the MB and ISM frequency range (1.7 GHz), if the DCO 402 is set to 4.25 GHz, the ILRO 404 may generate an input to the divide-by-1.25 circuit 406 with a carrier frequency of 4.25 GHz. The divide-by-1.25 circuit 406 may generate an input to the divide-by-2 circuit 408 with a carrier frequency of 3.4 GHz. The divide-by-2 circuit 408 may generate an output signal with a carrier frequency of 1.7 GHz.
Likewise, for the upper end of the MB and ISM frequency range (2.5 GHz), if the frequency of the DCO 402 is set to 6.25 GHz, the ILRO 404 may generate an input to the divide-by-1.25 circuit 406 with a carrier frequency of 6.25 GHz. The divide-by-1.25 circuit 406 may generate an input to the divide-by-2 circuit 408 with a carrier frequency of 5.0 GHz. The divide-by-2 circuit 408 may generate an output signal with a carrier frequency of 2.5 GHz. These are merely example frequencies and frequency ranges and other frequencies and ranges may be used.
It will be understood that the particular divider circuit block and divisor used are merely examples, and that other values (e.g., non-integer divisor(s) other than or in addition to 1.25, integer divisor(s) other than or in addition to 2) may be used in other implementations in accordance with some embodiments.
With some embodiments, generating a set of phase signals may include generating, from the pair of voltage-controlled oscillator signals 502, the set of phase signal pairs 508, 510, 512, 514, 516, 518, 520, 522. The set of phase signal pairs may be generated by a ring oscillator, such as the ILRO 506, as shown in
For some embodiments, an oscillation frequency of the ILRO 506 may be tuned to be substantially-near a carrier center frequency of a phase-modulated carrier output signal with the carrier center frequency. In some embodiments, the ILRO 506 may be coupled to the output of a DCO circuit, a VCO circuit, or the transconductance (gm) signal conditioning circuit 504. An injection circuit (such as the transconductance (gm) signal conditioning circuit 504) may inject the phase-modulated signal into the ILRO to generate a plurality of phases of the phase-modulated signal (such as the phase signals CK0 (508), CK90 (512), CK180 (516), and CK270 (520)) in some embodiments. Other sets of phase signals may be generated, such as CK0 (508), CK45 (510), CK90 (512), CK135 (514), CK180 (516), CK225 (518), CK270 (520), and CK315 (522). For some embodiments, the transconductance (gm) signal conditioning circuit 504 may inject a phase-modulated signal with phases of 0 degrees and 180 degrees into the ILRO 506.
For some embodiments, a multiplexer (MUX), such as a MUX 602 of
Some embodiments of the fractional frequency division circuit 308 of
For some embodiments, the initialization signal 634 may be configured to hold the first D-Flip-Flop 606 in a set state (which may occur by setting an “S” pin in a high state) and the second, third and fourth D-Flip-Flops 608, 610, 612 in a reset state (which may occur by setting an “R” pin in a high state). As a result, the Q pin output signals (S1618, S2620, S3622, and S4624) may be equal to 1, 0, 0, 0, respectively, while the initialization signal 634 is high. The left side of
As shown in
For example, the I signal 626, 702 may be a 50% duty cycle signal that is one of the inputs to the MUX 602. The I signal 626, 702 may correspond to a modulator input signal with a phase of 0 degrees. The Q 628, 704, IB 630, 706, and QB 632, 708 signals may correspond to phases of 90, 180, and 270 degrees, respectively. With the I signal 626, 702 equal to a 50% duty signal that corresponds to a 0 degree phase, the Q signal 628, 704 may correspond to a 90 degree phase and may be a quarter cycle delayed version of the I signal 626, 702. Likewise, the IB signal 630, 706 may correspond to a 180 degree phase and may be a half cycle delayed version of the I signal 626, 702. The QB signal 632, 708 may correspond to a 270 degree phase and may be a three quarters cycle delayed version of the I signal 626, 702 (or a half cycle delayed version of the Q signal 628, 704). The changes in the MUX select signals S1 (618, 712), S2 (620, 714), S3 (622, 716), and S4 (624, 718) cause changes in the source of the MUX output signal 720. For MUX input signals that are quarter cycle delayed versions of each other, changing the MUX select signals S1 (618, 712), S2 (620, 714), S3 (622, 716), and S4 (624, 718) may cause the MUX output signal 720 to insert quarter cycle delays. For MUX input signals I (626, 702), Q (628, 704), IB (630, 706), and QB (632, 708) with a 50% duty cycle and quarter cycle delays between each signal, the fractional frequency output signal 616, 720 may have a 40% duty cycle as shown in
For some embodiments, selecting portions of the set of phase signals 626, 702, 628, 704, 630, 706, 632, 708 may be a repeating process for generating a series of signals that includes: selecting a first phase signal 626, 702 as a first portion of the fractional frequency output signal 616, 720; responsive to detecting a rising edge of the first phase signal 626, 702, selecting a second phase signal 628, 704 as a second portion of the fractional frequency output signal 616, 720; responsive to detecting a rising edge of the second phase signal 628, 704, selecting a third phase signal 630, 706 as a third portion of the fractional frequency output signal 616, 720; responsive to detecting a rising edge of the third phase signal 630, 706, selecting a fourth phase signal 632, 708 as a fourth portion of the fractional frequency output signal 616, 720; and responsive to detecting a rising edge of the fourth phase signal 632, 708, repeating the process for generating the series of signals. With some embodiments, a fractional frequency division circuit (such as the circuit shown in
With some embodiments, sequentially selecting successive phases of the plurality of phases (of a phase-modulated carrier output signal) may include repeating a sequential process of responsively detecting a rising edge of a current phase signal (such as a rising edge of the I signal 702) and selecting a next phase signal (such as shown by dashed arrows 722, 724, 726, 728, 730, 732 of
Some embodiments for selecting portions of the set of phase signals 626, 702, 628, 704, 630, 706, 632, and 708 may include using the multiplexer selection ring oscillator 604 and may include initializing each element (or a set of states) in the multiplexer selection ring oscillator 604 and indicating a completion of initialization of the multiplexer selection ring oscillator 604 using a state change of the modulator input signal (such as the low to high transition of the I signal 702 triggering 734 the initialization line 710 to go low).
For some embodiments, an initialization signal 916 of
The initialization signal 1002 of
A series of states for the Q11010, 906 and Q21018, 908 output signals may repeat for some embodiments. Upon the rising edge of the INPUT signal with the INIT signal 1002 equal to a low state, the Q11010, 906 signal changes from high to low to match D11006, 910. Upon the next falling edge of the INPUT signal 1004, 914, the Q2 signal 1018, 908 changes from high to low to match the D2 signal 1014, 906. Upon the next rising edge of the INPUT signal 1004, 914, the Q1 signal 1010, 906 changes from low to high to match the D1 signal 1006, 910. The next falling edge of the INPUT signal 1004, 914 causes the Q2 signal 1018, 908 to change from low to high to match the D2 signal 1014, 906. With some embodiments, the input signal 914, 1004 with a 40% duty cycle may injected into the divide-by-2 circuit 900, and the output signal (Q1) 906, 1010 may be generated with a 50% duty cycle and a carrier center frequency that is half the carrier center frequency of the input signal 914, 1004, such as the example shown in
Some embodiments of the fractional frequency division circuit 308 of
For some embodiments, an initialization signal 1108 may be injected into a D-Flip-Flop 1106. The D-Flip-Flop 1106 outputs a Q signal 1110, which may be connected to an initialization pin of the MOD4 counter 1104 to initialize the MOD4 counter 1104 to the counter output signals (S01118, S11120, S21122, and S31124) equal to 1, 0, 0, 0, respectively, while the initialization signal 1108 is high. Initializing the select signals S01118, S11120, S21122, S31124 equal to 1000 may cause the MUX 1102 to select the I (P0) signal 1126 for the MUX output signal 1116.
As shown in
For example, the I signal 1126, 702 may be a 50% duty cycle signal that is one of the inputs to the MUX 1102. The I signal 1126, 702 may correspond to a modulator input signal with a phase of 0 degrees. The Q 1128, 704, IB 1130, 706, and QB 1132, 708 signals may correspond to phases of 90, 180, and 270 degrees, respectively. With the I signal 1126, 702 equal to a 50% duty signal that corresponds to a 0 degree phase, the Q signal 1128, 704 may correspond to a 90 degree phase and may be a quarter cycle delayed version of the I signal 1126, 702. Likewise, the IB signal 1130, 706 may correspond to a 180 degree phase and may be a half cycle delayed version of the I signal 1126, 702. The QB signal 1132, 708 may correspond to a 270 degree phase and may be a three quarters cycle delayed version of the I signal 1126, 702. The changes in the MUX select signals S0 (1118), S1 (1120), S2 (1122), and S3 (1124) cause changes in the source of the MUX output signal 1116. For the MUX input signals I (1126, 702), Q (1128, 704), IB (1130, 706), and QB (1132, 708) with a 50% duty cycle and quarter cycle delays between each signal, the MUX output signal 1116, 720 may have a 40% duty cycle as shown in
An example method disclosed herein in accordance with some embodiments may include: receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
According to the example method, in some embodiments, an oscillation frequency of the ILRO may be tuned to be substantially-near the carrier center frequency of the phase-modulated carrier output signal.
According to the example method, in some embodiments, generating the plurality of phases may further include tuning an oscillation frequency of the ILRO to be substantially near the carrier center frequency.
According to the example method, in some embodiments, generating the plurality of phases may further include injecting, by an injection circuit coupled to the ILRO, the phase-modulate carrier output signal into the ILRO.
The example method may further include, in some embodiments, transmitting the desired phase-modulated carrier output signal having the generated carrier center frequency equal to the desired carrier center frequency.
According to the example method, in some embodiments, the carrier center frequency of the phase-modulated carrier output signal may be 1.25 times the center frequency of the decoupled fractional frequency output signal.
According to the example method, in some embodiments, receiving the phase-modulated carrier output signal may include receiving phase-modulated carrier signals with phases of 0 degrees and 180 degrees.
According to the example method, in some embodiments, generating, by the ILRO, the plurality of phases of the phase-modulated carrier output signal generates phases of 0, 90, 180, and 270 degrees.
The example method may further include, in some embodiments, aligning the plurality of phases of the phase-modulated carrier output signal into a plurality of pairs of phases.
According to the example method, in some embodiments, generating the desired phase-modulated carrier output signal based on the decoupled fractional frequency output signal may include: dividing by 2 the center frequency of the decoupled fractional frequency output signal.
Further according to the example method, in some embodiments, dividing by 2 the center frequency of the decoupled fractional frequency output signal may include: triggering a divide-by-2 output signal to go high upon a rising edge of the decoupled fractional frequency output signal; and resetting the divide-by-2 output signal to low after an adjustable period of time, wherein a center frequency of the divide-by-2 output signal may be half the center frequency of the decoupled fractional frequency output signal.
According to the example method, in some embodiments, sequentially selecting successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases may include repeating a sequential process that may include: responsive to detecting a rising edge of a current phase of the plurality of phases, selecting a portion of a next phase of the plurality of phases; setting a next portion of the decoupled fractional frequency output signal equal to the selected portion of the next phase; and setting the current phase equal to the next phase.
Further according to the example method, in some embodiments, the sequential process may further include delaying the current phase prior to detecting the rising edge of the current phase.
An example apparatus disclosed herein in accordance with some embodiments may include: a digitally-controlled oscillator (DCO) circuit configured to output a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; an injection-locked ring oscillator (ILRO) configured to generate a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; and a fractional frequency division circuit coupled to the plurality of outputs of the ILRO, the fractional frequency division circuit configured to sequentially-select, using a multiplexer (MUX), successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases to generate a decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency.
According to the example apparatus, in some embodiments, the ILRO may be configured such that an oscillation frequency of the ILRO is tuned to be substantially-near the carrier center frequency of the phase-modulated carrier output signal.
The example apparatus may further include, in some embodiments, an injection circuit coupled to the ILRO and to an output of the DCO circuit and configured to inject the phase-modulate carrier output signal into the ILRO.
The example apparatus may further include, in some embodiments, an integer frequency division circuit coupled to the fractional frequency division circuit and configured to generate, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the DCO circuit, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
Further according to the example apparatus, in some embodiments, the integer frequency division circuit may be further configured to generate the desired phase-modulated carrier output signal based on the decoupled fractional frequency output signal by dividing by 2 the center frequency of the decoupled fractional frequency output signal. In some embodiments, the integer frequency division circuit may be further configured to trigger an integer frequency division output signal to go high upon a rising edge of the decoupled fractional frequency output signal. In some embodiments, the integer frequency division circuit may be further configured to reset the integer frequency division output signal to low after an adjustable period of time. In some embodiments, a center frequency of the integer frequency division output signal may be equal to half the center frequency of the fractional frequency output signal.
Further according to the example apparatus, the example apparatus may further include, in some embodiments, an amplifier configured to amplify the desired phase-modulated carrier output signal for transmission.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may include the MUX and multiple delay flip-flops, the multiple delay flip-flops having respective outputs configured to sequentially select the successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases.
According to the example apparatus, in some embodiments, the carrier center frequency of the phase-modulated carrier output signal may be 1.25 times the center frequency of the decoupled fractional frequency output signal.
According to the example apparatus, in some embodiments, the DCO circuit may be configured to output the phase-modulated carrier output signal with phases of 0 degrees and 180 degrees.
According to the example apparatus, in some embodiments, the ILRO may be further configured to generate the phases of 0, 90, 180, and 270 degrees of the phase-modulated carrier output signal.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may be further configured to align the plurality of phases of the phase-modulated carrier output signal into a plurality of pairs of phases.
According to the example apparatus, in some embodiments, the fractional frequency division circuit may be configured to repeat a sequential process including: responsive to detecting a rising edge of a current phase of the plurality of phases, selecting a portion of a next phase of the plurality of phases; setting a next portion of the decoupled fractional frequency output signal equal to the selected portion of the next phase; and setting the current phase equal to the next phase.
Further according to the example apparatus, the example apparatus may further include, in some embodiments, a delay element coupled to the fractional frequency division circuit and configured to delay the current phase prior to detecting the rising edge of the current phase.
Another example apparatus disclosed herein in accordance with some embodiments may include: a processor; and a non-transitory computer-readable medium storing instructions that are operative, when executed by the processor, to perform the functions including: receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO) a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.
In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings.
The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has”, “having,” “includes”, “including,” “contains”, “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a”, “has . . . a”, “includes . . . a”, “contains . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms “a” and “an” are defined as one or more unless explicitly stated otherwise herein. The terms “substantially”, “essentially”, “approximately”, “about” or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. The term “coupled” as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is “configured” in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
It will be appreciated that some embodiments may be comprised of one or more generic or specialized processors (or “processing devices”) such as microprocessors, digital signal processors, customized processors and field programmable gate arrays (FPGAs) and unique stored program instructions (including both software and firmware) that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of the method and/or apparatus described herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used.
Accordingly, some embodiments of the present disclosure, or portions thereof, may combine one or more processing devices with one or more software components (e.g., program code, firmware, resident software, micro-code, etc.) stored in a tangible computer-readable memory device, which in combination form a specifically configured apparatus that performs the functions as described herein. These combinations that form specially programmed devices may be generally referred to herein “modules”. The software component portions of the modules may be written in any computer language and may be a portion of a monolithic code base, or may be developed in more discrete code portions such as is typical in object-oriented computer languages. In addition, the modules may be distributed across a plurality of computer platforms, servers, terminals, and the like. A given module may even be implemented such that separate processor devices and/or computing hardware platforms perform the described functions.
Moreover, an embodiment can be implemented as a computer-readable storage medium having computer readable code stored thereon for programming a computer (e.g., comprising a processor) to perform a method as described and claimed herein. Examples of such computer-readable storage mediums include, but are not limited to, a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
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