The present invention relates to the field of electronic design automation and more particularly it relates to a system and methods for emulating a logic circuit design. Furthermore, the present invention pertains to emulation of any design or algorithm through hardware.
With the rapid progress in process technology; designers are integrating more functionality onto the same silicon die. However, the large size and complexity of these designs makes functional verification a very difficult task and hence the design cannot be thoroughly tested. If functional bugs are not found prior to fabrication, they will cause design re-spins which are both expensive and time consuming to the manufacturer of the silicon die.
As a result, several technologies have evolved to address the problem of functional verification. Some traditional simulation techniques fall short in terms of speed for today's Application Specific Integrated Circuits (ASICs). On the other extreme is a prototyping solution which is not flexible. Hardware verification tools using emulation are fast as well as flexible compared to software simulation tools. These types of emulation systems are built using commercial Field Programmable Gate Arrays (FPGAs).
FPGA based logic emulators are capable of emulating complex logic designs at clock speeds faster than an accelerated software simulator. The architecture of the emulation board has a major impact on the performance, efficiency, scalability, cost and flexibility of the emulation system. The system accepts a design in Register Transfer Level form (RTL) and maps it into the emulation hardware. Earlier the systems were single FPGA based non-piped systems, which have now evolved to a multi-FPGA piped system with distributed control.
In these prior systems, circuit-switching techniques are used to provide output signals from one chip to another chip. Other prior art systems do not partition the design for efficient utilization and hence do not allow for signal visibility. Also in these prior art solutions, the memory component on an FPGA is used, thereby degrading the efficiency of the overall process.
In order to provide an adequate emulation system, one embodiment of the present invention provides a computing system including a long term memory, a processor readable memory and a processor, in communication with one another, a long term memory including a recoding module, the recoding module in communication with a processor and the processor readable memory. This embodiment further comprises a recoding module that replaces a plurality of bi-directional ports connecting a plurality of the components in the logic circuit design with a plurality of unidirectional ports; a partitioning module for partitioning the logic circuit design into a plurality of independent logic circuit designs; a memory extractor and mapper module for performing memory transformations by extracting a plurality of components of the independent logic circuit design wherein each of the plurality of components comprises of a memory component and a logic component, and mapping the memory component onto an external system memory; a monitoring module for observing the visibility of internal signal buried in the logic circuit design, on the plurality of programmable logic device; and a time division multiplexing module for scheduling the nets.
Other embodiments of the present invention include a method of creating the recoded logic circuit comprising the steps of recoding the logic circuit design; assigning a first weight to each of one or more components to give a list of first weights, wherein each of the components comprises a memory component and a logic component; assigning a second weight to each of one or more ports, the ports interconnecting the components, wherein the second weight is equal to a number of wires, wherein the wires interconnect the components; generating a tree structure using the list of first weights; and partitioning the tree structure using a tree-partitioning algorithm into a plurality of independent logic circuit designs, such that an original connectivity of each of the components is maintained.
These and other embodiments described herein provide a solution for emulating, partitioning and testing logic circuits.
The accompanying figures together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
The present invention may be embodied in several forms and manners. The description provided below and the drawings show exemplary embodiments of the invention. Those of skill in the art will appreciate that the invention may be embodied in other forms and manners not shown below. The invention shall have the full scope of the claims and shall not be limited by the embodiments shown below. It is understood that the use of relational term, if any, such as first, second, top and bottom, front and rear and the like are used solely for distinguishing one entity or action from another, without necessarily requiring or implying any such actual relationship or order between such entities or actions.
The embodiments of the present emulation system 100 consist of hardware and a set of software tools that have been written to make the design mapable on this emulation hardware and also add extra functionality. The present system 100 accepts the design in RTL form and maps it into the emulation hardware using a number of modules. The embodiments allow full internal signal visibility just like software simulations and are scalable without much loss in performance. In this embodiment the emulation system is connected to a host PC 110 which has total control over the emulation process.
Embodiments of the emulation system may use commercial FPGAs. The board comprising of FPGAs 120 is designed to sit on a PCI slot of the host machine 110. It uses a PCI interface chip provides a high performance slave interface for PCI boards. The PCI interface chip is connected to the board controller through its local bus. The Complex Programmable Logic Device (CPLD) sits on the local bus to take care of the local bus protocol before the FPGAs are fully configured. After the configuration, the board controller starts communicating with the PCI chip over the local bus provided by the PCI interface chip. The host computer 110 directs all the actions on the board. It also acts as an interface to the user. A host PC controls 110 the emulation process by issuing commands to a board controller. In this way, the application on the host 110 can command the board controller to perform activities. The major type of commands are providing inputs, initiating an emulation cycle, setting up addresses to monitor, start monitoring and reading outputs. The input logic circuit design transformations of the present embodiments preserve the functionality of the original circuit design.
For the design to be mapped on to the emulator hardware, it has to be taken through a series of transformations. This transformations process makes changes in the RTL code to take into account the hardware architecture of the emulation system. These transformations do not change the functionality of the design in any way. All these transformations are VHDL-in-VHDL-out transformations. These transformations are realized by computer programs, that take in the RTL description of the design and give out a functional equivalent design. Numerous modules are provided in the present embodiments that combine the computer programs with the hardware as subsequently described with reference to
The host 110 and board 120 therefore provide one embodiment of the present invention that comprises a computing system that includes a long term memory, a processor readable memory and a processor, in communication with one another, a long term memory including a recoding module, the recoding module in communication with a processor and the processor readable memory. The host 110 and board 120 further provide a recoding module that replaces a plurality of bi-directional ports connecting a plurality of the components in the logic circuit design with a plurality of unidirectional ports; a partitioning module for partitioning the logic circuit design into a plurality of independent logic circuit designs; a memory extractor and mapper module for performing memory transformations by extracting a plurality of components of the independent logic circuit design wherein each of the plurality of components comprises of a memory component and a logic component, and mapping the memory component onto an external system memory; a monitoring module for observing the visibility of internal signal buried in the logic circuit design, on the plurality of programmable logic device; and a time division multiplexing module for scheduling the nets.
The method 200 comprises using the VHDL design as the input to step 205 to the system where it is read and analyzed. The recoding module recodes the input logic circuit design in step 210 by replacing the bi-directional ports by unidirectional ports. After the analysis and recoding of the input logic circuit design weights are assigned to components in step 215 of the logic circuit design using a lookup table. The number of wires needed to transfer the signals from one component to the other becomes the weight of the connecting ports between the components in step 220. The highest weight component becomes the top most entity. Further a tree structure is generated by the tree generation module with the top most entity forming a root-node of the tree in step 225 and the component instances form the children node in step 230. The ports weight that is the number of wires needed to transfer the signals for each entity forms the weights of the edges between its instance and the parent to that instance. The instances of entity with no component instances in its architecture, forms the leaf nodes in the tree in step 235. The generated tree structure maintains a comparable weight and the identified combined weight as the sum of weights of components and ports in step 240. The tree is then partitioned in step 250 into two or more pieces each of which can fit into one FPGA on the board. The design is then re-generated in step 255 however the size of the design partitions increases because each transformation is adding its own logic and some wrappers to the design.
Another embodiment of a method using the system hardware would comprise the steps of: partitioning the logic circuit design into a plurality of independent logic circuit designs; performing a memory transformation on a plurality of components of the independent logic circuit designs wherein each of the plurality of components comprises of a memory component and a logic component; whereby the plurality of components are one of the plurality of programmable logic devices; performing a monitoring transformation on the independent logic circuit designs to monitor a plurality of internal signals sent and received by the logic components; and interconnecting the independent logic circuit designs using a time phase schedule for communication maintaining an original functionality of the logic circuit design.
Another embodiment of the emulation system is shown in
During the Phase 1, FPGA0410 and FPGA3440 are in transmitting mode while FPGA1420 and FPGA2430 are in receiving mode. In this phase FPGA0410 sends signals simultaneously on Net_01 and Net_02, while FPGA3440 sends signals simultaneously on Net_31 and Net_32.
During the Phase 2, FPGA0410 and FPGA3440 are in receiving mode while FPGA1420 and FPGA2430 are in transmitting mode. In this phase FPGA1420 sends signals simultaneously on Net_10 and Net_13, while FPGA2430 sends signals simultaneously on Net_23 and Net_20.
During the Phase 3, FPGA0410 and FPGA3440 are in transmitting mode while FPGA1420 and FPGA2430 are in relay mode. FPGA0 transmits a signal for FPGA3440 along Net_03 where FPGA2 forward the incoming signals to FPGA3440. Similarly FPGA3440 transmits a signal for FPGA0410 along Net_30 where FPGA1 forwards the incoming signals to FPGA0410.
During the Phase 4, FPGA1420 and FPGA2430 are in transmitting mode while FPGA0410 and FPGA3440 are in relay mode. FPGA2430 transmits a signal for FPGA1420 along Net_21 where FPGA3440 forwards the incoming signals to FPGA1420. Similarly FPGA1420 transmits a signal for FPGA2430 along Net_12 where FPGA0410 forwards the incoming signals to FPGA1420.
Providing the connections as described above, another method provided by the present embodiments includes the steps of connecting at least two of the independent logic circuit design with a plurality of signal-communicating paths; communicating a plurality of signals between the independent logic circuit designs in a plurality of time phase schedules; and sending the plurality of signals through the signal-communicating path in the plurality of time phase schedules.
In another embodiment,
The PCI bus interface will double the bandwidth into the board and can potentially speed up the emulation rate by 2×. The emulation board 700, uses the data bus for communication between the host and the controller. The address bits of the PCI bus pass on commands and data. The CPLD 730 sits on the local bus to take care of the local bus protocol before the FPGAs are fully configured. After configuration, the board controller starts communicating with the PCI chip over the local bus provided by the PCI Interface Controller. An application running on the host gives the controller commands by writing into some registers that the PCI Interface provides for this purpose.
In this way, the application on the host can command the board controller to perform activities. The major type of commands are providing inputs, initiating an emulating cycle, setting up addresses to monitor, start monitoring and reading inputs. The FPGA0705 comprises of transmitter components TD01740 for transmission from FPGA0705 to FPGA1710, TD02745 for transmission from FPGA0705 to FPGA2715 and TD023750 for transmission from FPGA0705 to FPGA3720 through FPGA2715. Finally after the transmission, TD01, TD02 and TD 023 inform the FPGA change generator 751.
The FPGA1710 comprises of transmitter components TD10755 for transmitting from FPGA1710 to FPGA0705, TD102760 for transmitting from FPGA1710 to FPGA2715 through FPGA0705. Finally after the transmission, TD10, TD102 and TD13 inform the FPGA change generator 766.
The FPGA2715 comprises of transmitter components TD20770 for transmitting from FPGA2715 to FPGA0705, TD231775 for transmitting from FPGA2715 to FPGA1710 through FPGA0705 and TD 23 for transmitting from FPGA2715 to FPGA3720. Finally after the transmission, TD20, TD231 and TD 23 inform the FPGA change generator 781.
The FPGA3720 comprises of transmitter components TD31785 for transmitting from FPGA3720 to FPGA1710, TD 32 for transmitting from FPGA3720 to FPGA2715. TD310790 for transmitting from FPGA3720 to FPGA0705 through FPGA1710. Finally after the transmission, TD20, TD231 and TD 23 inform the FPGA change generator 791.
The final change generator 793 on FPGA0705, collects all the FPGA change generator signals from 751, 766, 781 and 791.
Another embodiment of the present invention is depicted in
As depicted in
The above description of the system and methods are meant to be illustrative and not restrictive. The present invention may be applied to emulate any design or algorithm. One skilled in the art will appreciate that although specific embodiments of the emulation system and methods have been described for purposes of illustration, various modifications can be made without deviating from the spirit and scope of the present invention. Accordingly, the invention is described by the appended claims.
Number | Date | Country | Kind |
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211/MUM/05 | Apr 2005 | IN | national |