Patent Application
20050060520
Not Applicable.
The research was sponsored by HPCS contract number NBCH020056 and ends Sep. 16, 2003.
Not Applicable.
The invention disclosed broadly relates to the field of information processing systems and more particularly relates to a system and method for increasing the number of architecturally visible registers in a central processing unit (CPU).
Most current CPU architectures, including the PowerPC™ architecture, limit the number of architecturally visible registers (both general purpose registers, or GPRs, and floating point registers, or FPRs) to a small number N (with N≦32 in general for RISC architectures). While these architectural registers may be backed up by a larger pool of physical renaming registers, the compiler (or assembly language programmer) must make register allocation and spilling decisions using only (N-K) general-purpose registers, where K is the number of registers reserved for specific uses by the application binary interface. This limitation on the number of architected registers increases register pressure, increases the number of register spills and restores, and limits the use of program transformations requiring a large number of registers (such as unroll-and-jam).
The main architectural limitation on the size of the register files is the number of bits available in the instruction to encode register specifiers. Fixed length instructions and dense instruction encoding are key features of RISC architectures. For example, the PowerPC™ ISA (instruction set architecture) uses 32 bits to encode an instruction, with five bits allocated for each register specifier. In this architecture, instructions have between one and four register sources and destinations, such that there are only 12 bits remaining to encode the operation. Instruction encoding is tight, so that any attempt to increase the width of the register specifier fields would result either in longer instructions and code bloat, or in two-address instructions rather than the traditional RISC three-address instructions. We now discuss some known solutions to the problem of encoding register specifiers to increase the number of usable registers.
Several register contexts are maintained to improve the performance of function call and return. However, while there may be more than N physical registers present in the machine, only N of them are architecturally visible and available for use at any point in time. The Zilog Z80 8-bit microprocessor had a primitive version of this feature in the form of two sets of registers that could be rapidly exchanged with one instruction.
More than N registers are physically present in super-scalar processors, but these registers are invisible to the user, being used by the hardware to transparently and dynamically map the N architecturally visible registers over time. The user does not have direct control over the management of this pool of registers.
The IA64 register file contains 128 architected registers encoded using 7 bit register specifier fields. This results in an instruction word that is 41 bits long, resulting in reduced code density.
U.S. Pat. No. 4,574,349 (issued to Rechtschaffen) interprets the register specifiers in an instruction as indices into an indirection table from which the actual register numbers are obtained. This solution suffers from the following drawbacks: (a) the indices to the indirection table are still limited to being log N bits wide—this makes the solution similar to a user managed register renaming scheme; (b) they encode each register field independently, which requires either multiple indirection tables or multiple access ports into a shared indirection table, whereas we encode in a single entry of the indirection table all the register specifiers in an instruction. A related solution is proposed in the ISCA '93 paper by Kiyohara et al., titled “Register Connections: A New Approach to Adding Registers into Instruction Set Architectures.”
The CodePack™ system is a hardware-software method for storing PowerPC™ instructions in memory in a compressed form and decompressing them on-the-fly, only as needed by the processor. This system relies on information-theoretic compression techniques to produce a variable-length encoding of PowerPC™ instructions that reduces the overall code footprint on average, but does not increase the number of architected registers.
There is thus a need for a method and system for encoding and decoding architected registers that overcomes the shortcomings of the prior art.
A system and method to extend the number of architecturally visible registers in a processor while preserving the number of bits of the instruction encoding. The system comprises: an indirection table whose entries encode register patterns for registers used by instructions; instructions to load and store register patterns to and from the indirection table; a mechanism to identify instructions that use the indirection table; and a mechanism to identify a set of bits in instructions that are used to index into the indirection table.
According to another embodiment, a method of encoding registers in a computer instruction comprises constructing a table having a plurality of entries. Each entry specifies a combination of a plurality of registers. The method also comprises generating an instruction having a reference to one of the entries in the table. The method then comprises accessing the plurality of registers using the reference in the table. The method further comprises merging said number of registers into an expanded instruction that is used for remaining stages of instruction processing.
The invention solves the problem of designing or enhancing the instruction set architecture (ISA) of a processor by increasing the number of architected registers, while fulfilling the following requirements: a) continuing to encode instructions in the architected instruction width; b) preserving the three-address nature of instructions; and when applied to an existing ISA; c) maintaining backwards compatibility, to allow existing binaries to execute unmodified on implementations of the new ISA, while being able to access only the bottom N registers (this requirement is vacuous when the invention is applied to a new ISA).
While in existing implementations of the PowerPC™ architecture 15 bits of the instruction are allocated for three register specifiers, programs do not use, and compilers do not generate, anywhere close to the 215 possible combinations of register specifiers. Thus, while the encoding of each register specifier is dense, the encoding of register specifier tuples is sparse. An ordered tuple of register specifiers occurring in a program is hereinafter referred to as a Register Access Pattern (RAP). Analysis of the SPECcpu2000 benchmarks shows 1000-3000 static RAPs per benchmark. Of the thousands of RAPs, a small number account for most of the dynamic references made by a program.
Thus a system according to the invention uses RAPs to enhance a processor architecture and its corresponding ISA with four components: an architecturally visible Register Access Pattern Table (RAPT), which is used as an indirection table for RAPs; instructions to explicitly load and store RAPT entries; a method of identifying instructions that use the RAPT; and a set of bits in instructions that are used to index into the RAPT.
A RAPT entry comprises a plurality of register specifiers that together encode one or more RAPs. The number M of register specifiers in a RAPT entry is hereinafter called the RAPT width. For example, assuming a RAPT width M=4 consider Table 1 below.
The first column is the location of the RAP in the RAPT. The second column is the contents of the RAP. Thus, entry 1 of the RAPT contains the four numbers 1, 2, 3, and 4, which identify architectural register numbers to be used by an instruction accessing RAPT entry 1.
The number of addressable registers is determined by the width of each field of a RAPT entry, hereinafter called the implementation width. An implementation width of W bits allows the addressing of 2W architectural registers. This limit is 256 for W=8 (32-bit RAPT entries for M=4) and 65536 for W=16 (64-bit RAPT entries for M=4). The number of bits used to index the RAPT is hereinafter denoted as B. The number of RAPT entries is therefore 2B.
Referring to
We provide the following instructions to manage the RAPT: (a) An instruction that, given a RAPT index and a memory address, loads the contents of the memory address into the RAPT entry specified by the index; (b) An instruction that, given a RAPT index and a memory address, stores into said memory address the contents of the RAPT entry specified by the index; and (c) Optionally, instructions may be provided for loading and storing all entries of the RAPT from/to a base memory address.
When applied to an existing ISA, the invention provides a mechanism, either explicit or implicit, to indicate for each instruction whether to interpret its register access fields directly (hereinafter referred to as compatibility mode), or using indirection through the RAPT (hereinafter referred to as extended mode). A correctness criterion for this mechanism is that it must interpret each instruction of an existing binary as being in compatibility mode. This mechanism includes, but is not limited to, the following situations: always using the RAPT (implicitly); never using the RAPT (implicitly); specifying a mode on a per instruction basis (explicitly); and specifying the mode of a group of instructions with a single mode context (the context is toggled explicitly, the classification of individual instructions is implicit).
A system according to the invention requires the ISA to specify, for each instruction, a plurality of B bits that are used to identify the RAPT entry to be used by an instance of that instruction (unconditionally, when the invention is applied to a new ISA; in extended mode, when the invention is applied to an existing ISA). These bits do not need to be contiguous in the instruction word. The collection of these bits is hereinafter called the RAPT index field of the instruction (e.g.,
Referring to
Referring to
For an instruction in extended mode, in step 310 the decoder extracts the RAPT index field of the instruction, uses it to index into the RAPT, and obtains the register specifiers from said RAPT entry. The specifiers are already represented at implementation width W.
In step 312 an appropriate number of extended register specifiers is merged with the remaining components of the instruction (i.e., after the register specifiers are extracted) and provided to the remainder of the instruction processing hardware. The actual number of register specifiers merged may vary from instruction to instruction; it is permissible for two instructions accessing the same RAPT entry to merge different numbers of register specifiers.
What has been shown and discussed is a highly-simplified depiction of a programmable computer apparatus. Those skilled in the art will appreciate that other low-level components and connections are required in any practical application of a computer apparatus.
