System and method for generating a plurality of models at different levels of abstraction from a single master model

Abstract

A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustrative flow diagram of a process to use a single input model to produce multiple equivalent models at different levels of abstraction.

FIG. 2 is a schematic drawing of an illustrative computer system that can be programmed to implement a novel translation system of FIG. 1 in accordance with an embodiment of the invention.

Claims

1. A method of producing models of a design of an integrated circuit, the method comprising: providing a master model of a design of an integrated circuit; andtranslating the master model to at least first and second models functionally equivalent to the master model and at different levels of abstraction from each other and wherein each of the first and second models includes timing information of the design accurate for its respective level of abstraction.

2. The method of claim 1, wherein translating the master model to a first model comprises using a synthesis tool to produce a register transfer level model; andtranslating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer model.

3. The method of claim 1, wherein translating the master model to first model comprises using a synthesis tool to produce a register transfer level model that specifies state-by-state execution between clock cycles of the design; andtranslating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer model, and that does not specify state-by-state execution between the clock cycles of the design.

4. the method of claim 1, wherein the master model includes behavior information of the design and does not include timing information of the design.

5. The method of claim 1, wherein the master model includes behavior information of the design and does not include timing information of the design; and wherein translating the master model to a second model comprises using a synthesis tool to produce a register transfer level model that specifies scheduling information between clock cycles of the design; andwherein translating the master model to a first model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer model, and that does not specify scheduling information between clock cycles of the design.

6. The method of claim 1, wherein translating the master model to a first model comprises using a synthesis tool to produce a register transfer level model of an operation of the design that specifies a value that will post at an output at a given integrated circuit clock cycle of the design and that specifies scheduling logic between clock cycles of the design during the operation; andtranslating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model that specifies a value that will post at an output of the register transfer model at the end of the operation without specifying sequencing logic between clock cycles of the register transfer model.

7. The method of claim 5, further comprising: inputting the transaction level model to a simulation tool; andusing the simulation tool to simulate executing software on the transaction level model.

8. The method of claim 5, further comprising: inputting the transaction level model to a simulation tool;using the simulation tool to simulate executing software on the transaction level model;inputting the register transfer level model to the synthesis tool; andusing the synthesis tool to produce a gate level model based on the register transfer level model.

9. The method of claim 1, wherein the master model comprises behavior information of the design and does not include timing information of the design;wherein translating the model to a first model comprises using a synthesis tool to produce a register transfer level model of an operation that specifies a value that will post at an output at a given clock cycle of the design and that specifies scheduling logic between clock cycles of the design during the operation; andwherein translating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model that specifies a value that will post at an output of the register transfer model at the end of the operation at the same clock cycle as in the register transfer model, without specifying sequencing logic between the clock cycles during the operation.

10. The method of claim 1, further comprising: translating the master model to a third model functionally equivalent to the master model and at a different level of abstraction than the first and second models, and which includes timing information of the design accurate for its respective level of abstraction.

11. The method of claim 1, further comprising: translating the master model to a third model functionally equivalent to the master model and at a different level of abstraction than the first and second models, and which includes timing information of the design accurate for its respective level of abstraction; andwherein the first model comprises a register transfer level model;wherein the second model comprises a cycle accurate model; andwherein the third model comprises a transaction level model.

12. The method of claim 1, wherein the master model does not include timing information of the design.

13. the method of claim 1, wherein the maaster model includes partial timing information of the design.

14. The method of claim 1, wherein translating the master model to a first model comprises using a synthesis tool to produce a register transfer level model that includes at least one register and control logic used for scheduling; andwherein translating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer model; and further comprising:in translating the master model to a register transfer model, marking the at least one register and the control logic used for scheduling; andomitting the marked at least one register and control logic from the at least onr transaction level model or cycle accurate model.

15. The method of claim 1, wherein translating the master model to a first model comprises using a synthesis tool to produce a register transfer level model;translating the master model to a second model comprises using the synthesis tool to produce at least one of a transaction level model or a cycle accurate model functionally equivalent to the register transfer model; andincluding at least one of integrated circuit power, noise or timing information of the design in the at least one transaction level model or cycle accurate model.

16. A computer readable storage medium storing code for performing the method of claim 1.

17. A computer system programmed to perform the method of claim 1.

18. A computer system comprising: a CPU;a storage; anda bus coupling the CPU to the storage;wherein the storage stores code for execution by the CPU, the code performing:providing a master model of a design of an integrated circuit; andtranslating the master model to at least first and second models functionally equivalent to the master model and at different levels of abstraction from each other and wherein each of the first and second models includes timing information of the design accurate for its respective level of abstraction.