Patent Application
20090160493
The invention is directed, in general, to manipulating a frequency spectrum and, more specifically, to manipulating a frequency spectrum of a spread-spectrum clock signal.
Clock signals are playing an increasingly important part of processor and computer system architectures. Whenever a transition within part of the processor and computer system architecture occurs, some electromagnetic energy is radiated. Therefore, generation and distribution of clock signals also generates radiated energy. However, this radiated energy can create problems in the processor and computer system architectures, such as static buildup or high-frequency interference. This is especially a problem at higher clock signal frequencies demanded by today's computer architecture.
Interestingly, clock signals waveforms can be regarded as a superposition of corresponding specific sine waves at various frequencies. The more energy a specific sine wave has, the stronger it is and the larger its amplitude. Unfortunately, the energy carried by a given sine wave can interfere with proper computer system operation, especially if some feature of the processor or computer architecture is particularly vulnerable to a particular radiated sine frequency.
To combat this problem, a changing range of clock signal frequencies can be used in today's processors and computer architecture systems. For instance, a clock signal could have a frequency of 1.01 Gigahertz for a first microsecond, and could have a frequency of 0.99 Gigahertz for a second microsecond, and 1.03 Gigahertz for a third microsecond.
Because the frequency of the clock signals change over time, the frequencies of their corresponding sine waves change over time as well. In other words, sine waves corresponding to changing clock signals are “spread” over a spectrum of sine frequencies (i.e., a “spread spectrum”). The average radiated energy of a given sine frequency can be reduced because this sine frequency may not be used during a given time period. Instead, the energy is radiated at some other sine wave frequency for the given time period.
Traditionally, the spread spectrum clock signal is generated by using phase-locked loop (PLL). Generating a spread spectrum clock signal may be achieved either by applying a signal on a control line of a voltage controlled oscillator (VCO) or by dithering a divider circuit inside the PLL. In these approaches, the resulting spread spectrum can be both inaccurate and hard to control.
To address the above-discussed deficiencies of the prior art, the invention provides, in one aspect, a circuit for generating a spread-spectrum clock signal. The circuit comprises (a) a modulator configured to generate a modulated control value and (b) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output.
Yet another aspect of the invention provides a system for generating a spread-spectrum clock source. The system comprises: (a) a generator configured to generate a plurality of equidistant phase-shifted clock signals, (b) a modulator configured to generate a modulated control value and (c) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output.
Yet another aspect of the invention provides a method of generating a spread spectrum clock signal. The method comprises: selecting a modulation pattern, generating a first modulated control value as a function of the modulation pattern, receiving the first control value into a frequency synthesizer having a directly-derivable frequency response, producing a first clock frequency as a function of the first modulated control value, generating a second modulated control value as a function of the selected modulation pattern, receiving the second modulated control value to the frequency synthesizer having the directly-derivable frequency response, and producing a second clock frequency as a function of the second modulated control value. In at least some embodiments, if the method does not end, a new second modulated control value is selected as a function of the selected modulation pattern.
For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The disclosure further recognizes that, for certain frequency synthesizers, as will be described later, a high degree of control over an SS clock output can indeed be maintained when generating and changing SS clock output signals. In the disclosure, this high level of control can occur through employment of a modulated control value, such as a modulated control word, which is used to control a synthesis of output frequencies by a certain types of frequency synthesizers.
This disclosure still further recognizes that, with employment of a “directly-derivable” output frequency synthesizer in conjunction with the modulated control value, an improved spread spectrum control can result. A “directly-derivable” output frequency generator is generally defined as a frequency generator that generates a frequency response from a given control value, through a precisely, mathematically describable mechanism. One such directly derivable output frequency generator is a “flying adder” frequency synthesizer.
Aspects of the improvement may include, in generating and controlling a spread spectrum clock output, the recognition and employment of: a) a directly-derivable output frequency generator having a correlated directly-derivable, precise output function, b) for small areas of a change of an input value (e.g., “a modulated word”), the change in the output frequencies of the SS output clock signals becomes linear, c) that the frequency synthesizer has an effectively-instantaneous response speed. More specifically, after the moment of control word update, the output frequency will be changed in next clock cycle and, d) the frequency resolution of the SSCGS 100 could be very fine, such as a fraction of a cycle per second. In some embodiments, this resolution is controllable through the number of fractional bits used in the control word used in a directly-derivable output frequency generator.
In some embodiments, the SSCSG 100 includes a crystal 102 coupled to a phased-locked loop (“PLL”) 105. The PLL 105 includes a phase and frequency detector (“PFD”) 110 coupled to a charge pump (“CP”) 120. The CP 120 is coupled to a filter 130. The filter 130 is coupled to a voltage controlled oscillator (VCO) 140. A divider 150 is also coupled between the VCO 140 and the PFD 110. The VCO 140 generates a plurality of trains of equidistantly phase-shifted clock inputs. In the illustrated embodiment, there are 32 separate clock pulse trains, n0-n31, each clock pulse train phase shifted by 2π/32 radians, although in other embodiments, there are other numbers of separate clock pulse trains.
The PLL 105 is also coupled to a “directly-derivable” output frequency generator (“DDOFG”) 170, such as a flying-adder frequency synthesizer (“FAFS”) constructed according to the principles of the invention, although other directly-derivable output frequency generators are within the scope of the disclosure. U.S. Pat. No. 6,329,850 to Mair, et al., entitled “Precision Frequency and Phase Synthesis,” U.S. Pat. No. 6,940,397 to Xiu, et al., entitled “Scalable High-Speed Precision Frequency and Phase Synthesis,” and “A Flying-Adder′ Architecture of Frequency and Phase Synthesis with Scalability” by Xiu, et al., I.E.E.E. Transactions on Very Large Scale Integration Systems, Vol. 10, No. 5, October 2002, pages 637-649, all incorporated herein by reference, contain more information on FAFS.
A modulator 160 is also coupled to the DDOFG 170. The modulator 160 generates the modulated control value, such as a modulated control word. As will be described below, the modulator 160 generates the modulated control word, which is derived from a modulation pattern input 161 and a parameter control 163. This modulated control word varies, at least in part, as a function of time.
In some embodiments, the modulation pattern is selected from a group including at least one of: a random number modulation pattern, a triangular wave modulation pattern, a saw-tooth wave modulation pattern, and a sigma delta modulation pattern, as will be described below when discussing
The DDOFG 170, as a function of the modulated control word, using the clock input trains n1-n32 to generate a spread spectrum (“SS”) clock signal (i.e., a first SS clock signal) with the corresponding frequency of the first control word. After a given amount of time or system cycles as controlled by an update clock signal, a second modulated control word is inputted to the DDOFG 170 and the SS clock signal's frequency is updated, (i.e., a second SS clock signal) which corresponds to this second control word.
The selection of the second control word alters the frequency components of the SS clock signal, which spreads the spectrum of the clock signal. This change from the first SS clock signal frequency to the second SS clock signal frequency is generally correlated to a change from the first modulated control word to the second modulated control word being employed by the DDOFG 170, such as described above.
Advantageously, in at least some embodiments, through use of the modulated control word, a control of the change of the SS clock signal occurs when employing the directly-derivable frequency generator, such as the DDOFG 170, although other directly-derivable frequency generators are within the scope of the disclosure. Use of a directly-derivable frequency generator with a modulated control value allows a directly-derivable relationship to occur between a change of the modulated control value and a change of a first to a second SS clock signal. In some embodiments, the directly-derivable frequency response relationship is a linear relationship between a change in the modulated control word and a change in the SS clock signal output.
When a control value, such as a control word, is used with a frequency synthesizer that has a directly-derivable frequency response, such as the SSCSG 100, an output clock signal results with a frequency corresponding to the control word. Advantageously, when the control words of the frequency synthesizer are updated in a selected pattern, the output frequency will follow in mathematically predictable fashion as a function of the selected pattern. In some cases, the output frequency will follow in a linear fashion.
In some embodiments, the parameter control 163 includes data selected from a group including at least one of: a magnitude of variation of a control word, a step size of a variation of a control word, an update rate for updating the control word, and an unmodulated frequency control word, as will be discussed below.
As is illustrated in
The frequency pattern stored in the frequency register 205 denotes the value about which the modulated control word periodically changes. For instance, the FREQ0 could be set at [1000:0000], which would be the median value of the modulated control word. Alternatively, the FREQ0 value could be set at [1011:1111], depending upon circumstances.
The magnitude register 207 stores the magnitude of the change of the modulated control word. In other words, this sets the limits of the change of the modulation of the control word. In some embodiments, this would be 1% of FREQO, 2% of FREQO, 5%, and so on.
The step size register 209 denotes the amount of change between modulated control word values generated by the modulated control word generator 201. These can be various levels of gradations. The update clock register 211 then is used by the modulated control word generator 201 to select a new modulated value after a certain time period has elapsed. Please note that the DDOFG 170 may, in some embodiments, have a cycle time that is significantly faster than the time referenced in the update clock register 211.
These values are then used by the modulated control word generator 201 to change the value of the modulated control word. The modulated control word is then conveyed to the DDOFG 170 of
Employment of a modulated control word gives more control over the output of a frequency synthesizer than found in conventional clock generator systems. This control is expressed as a directly-derivable output frequency response. The spread-spectrum clock frequency is a function of the equidistant phase-shifted clock signals and a variation of the varying control value.
The three distinct areas 311, 313, and 315 of
In step 720, a first modulated control value, such as a modulated control word, is generated as a function of the modulation pattern.
In a step 730, a first modulated control value is inputted into a frequency synthesizer. The frequency synthesizer has a directly-derivable output frequency response. In one embodiment, the frequency synthesizer is a FAFS. In step 740, a first clock frequency is outputted as a function of the first control value.
In a step 750, a second modulated control value is generated as a function of the selected variable modulation pattern. In a step 760, the second control value is input into a frequency synthesizer.
In a step 770, a second clock frequency is output as a function of the second control value.
In a step 780, it is determined whether the spread spectrum function of the SSGCS 100 is turned off. In some embodiments, this determination can be derived from contents of the update clock register 211. If it is finished, the method 700 ends. If the method does not end, a new second modulated value is selected in the step 750.
In some embodiments of method 700, if a change of a first control value to a second control value is a value of delta, a variation of output clock frequency between the first output clock frequency and the second output clock frequency is proportional to delta (by a constant value).
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.
