Claims
- 1. A method to generate a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency, said method comprising:
counting clock pulses of said first clock signal to generate a count value; generating a blanking signal when said count value reaches a predetermined blanking value; blanking at least one clock pulse of said first clock signal in response to said blanking signal; and repeating said counting, said generating, and said blanking at a predetermined rate corresponding to said predetermined blanking value to generate said second clock signal.
- 2. The method of claim 1 further comprising clocking at least one digital circuit with said first clock signal and said second clock signal.
- 3. The method of claim 1 wherein said second effective clock frequency is less than said first effective clock frequency.
- 4. The method of claim 1 wherein said blanking comprises eliminating said at least one clock pulse from said first clock signal.
- 5. The method of claim 1 wherein said second effective clock frequency comprises said first effective clock frequency reduced by a ratio of at least one less than said predetermined blanking value divided by said predetermined blanking value.
- 6. Apparatus to generate a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency, said apparatus comprising:
a clock source generating said first clock signal; a modulo counter counting clock pulses of said first clock signal and generating a mod signal when said modulo counter reaches a predetermined blanking value; an inverter to generate a blanking signal in response to said mod signal; and a logic circuit to generate said second clock signal in response to said first clock signal and said blanking signal.
- 7. The apparatus of claim 6 wherein said modulo counter resets itself and repeats counting up to said predetermined blanking value after said mod signal is generated.
- 8. The apparatus of claim 6 further comprising at least one digital circuit being clocked by said first clock signal and said second clock signal.
- 9. The apparatus of claim 6 wherein said second effective clock frequency is less than said first effective clock frequency.
- 10. The apparatus of claim 6 wherein said blanking signal eliminates at least one clock pulse from said first clock signal to generate said second clock signal.
- 11. The apparatus of claim 6 wherein said second effective clock frequency comprises said first effective clock frequency reduced by a ratio of at least one less than said predetermined blanking value divided by said predetermined blanking value.
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE
[0001] U.S. Pat. No. 6,424,194, U.S. application Ser. No. 09/540,243 filed on Mar. 31, 2000, U.S. Pat. No. 6,389,092, U.S. Pat. No. 6,340,899, U.S. application Ser. No. 09/919,636 filed on Jul. 31, 2001, U.S. application Ser. No. 09/860,284 filed on May 18, 2001, U.S. application Ser. No. 10/028,806 filed on Oct. 25, 2001, U.S. application Ser. No. 09/969,837 filed on Oct. 1, 2001, U.S. application Ser. No. 10/159,788 entitled “Phase Adjustment in High Speed CDR Using Current DAC” filed on May 30, 2002, U.S. application Ser. No. 10/179,735 entitled “Universal Single-Ended Parallel Bus; fka, Using 1.8V Power Supply in 0.13MM CMOS” filed on Jun. 21, 2002, and application Ser. No. ______ with attorney docket number 13910US02 filed on Jan. 10, 2003, are each incorporated herein by reference in their entirety.